From patchwork Tue Oct 17 05:24:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153914 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911516vqb; Mon, 16 Oct 2023 22:26:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEQw/mZVsjiAN/q/NFRb5GCB0OG0KBFrzxy4+O9ug1PolKHyBAB2oyHlrQW7+wFAVPiCp2Q X-Received: by 2002:a17:902:e746:b0:1bb:9e6e:a9f3 with SMTP id p6-20020a170902e74600b001bb9e6ea9f3mr1374585plf.4.1697520408526; Mon, 16 Oct 2023 22:26:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520408; cv=none; d=google.com; s=arc-20160816; b=K6EiZJb6SDX6msQjLfTr66xAPhh+eFu3XQeN285nuXraYmmWfrnpqnPtLHICH42RAH nDqrI2w9PkqZxe5e7j/dhDpXyuUiRyKbuP0HCCcdL5/g2aFkNvpJrU5bi2+/UtV6vQEU /nauNXEmoHg+HntzXSE1pYcScyh8NViV+uQ+AOszs5nDGcS57Y/+oPtPAevaOyP3meBW QC2wcXAaSo1apdgx3XAvkCsIDMQc2K3irk40WezEcHoCygozuEQgX2VhzT7UNRqRqmf5 AnrNHLp1nhndKo1X8Dlo1zPG3nZOjvEtGCwtzUZdnV4FJXa4wdYD4qC6nfWJ/iO3pbVf BC7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=BrL9oNxHAJ4W0imwykZtfH/XuOSWFdbOgwu0HnJTarY=; fh=O1j13Mu+YXmD8t08/npRM3Uw5SAxbjMOF7NW+nWn+v8=; b=WWih7yuQ773lztUah5dt3V0S6bCAQsK+WpoGashN66p2AlH6lmC95f1gak0IoFl95i PAYZpFMvEf7D4a9Oy25COSxvc/CVGx3OtWIc2Fc4Qc534GWXA6yY9ywLVUvLSixrCPXw dkop7yx0MMkWP4fk5q0pdjbRJfxi6MW1rwSqm6UAVQdOrQh3FsABzdou2RZkNkpwkP1Q yVGovHHCmxueuCNHrvWwk1Z5jVwou+adw5RM/cIUs1K+RkbV/mcfr8dqO3bsw7VBimlY c0zjo5wi6pGMbZvgNIFGH+QWGe3wyMafnLnD9WjGw77xaZVZgLAIGw0/Fehpf3Z/1WFB Og9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QW2al59w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id b11-20020a170902bd4b00b001c9d37ed06csi917880plx.389.2023.10.16.22.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:26:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=QW2al59w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id A892580A28FE; Mon, 16 Oct 2023 22:26:21 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234624AbjJQFZr (ORCPT + 19 others); Tue, 17 Oct 2023 01:25:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33268 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234455AbjJQFZQ (ORCPT ); Tue, 17 Oct 2023 01:25:16 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09146D60; Mon, 16 Oct 2023 22:25:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520307; x=1729056307; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=CQh+bZwgm8XQjgey0Vkw8VOLhpnt8WUpS87zpwPo/+4=; b=QW2al59wTJUCIautj6v0BYFMGz+G3zdhTxyKcw8/wwgod0gvPgIMp7de dVSLpKQDRikKdWluyDQaiHcJ0aklp39GgJqkkLrUSYI3jQocwqMyw/H5b jS0LnJIz7maBmIYD3iJ7/sjrSf7/G7SeSASnXqdIrBsUrpYeeq5j0ZTYq V3s9WnNCdFmUWEX9FFnUWwZEjecElm6Rn4Cj8dfdOHYv1FsyAQbnc9h0V v0Avn9MDGYKk0C5M7UsGmFGcHqf1j38Re4OjP5R9Mlyvcfg4EBqYXXR1X /2MJteiGP1c8YpiRQ7A2tO2iu52L9lLeZy/RCNhqd0fl4NJpnplwpxRB1 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561724" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561724" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087357980" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087357980" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:02 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 1/6] kernel/time: Add system time to system counter conversion Date: Tue, 17 Oct 2023 10:54:52 +0530 Message-Id: <20231017052457.25287-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:26:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979159149857892 X-GMAIL-MSGID: 1779979159149857892 From: Lakshmi Sowjanya D Support system-clock to system-counter conversion. Intel Timed IO hardware, using system counter as reference to schedule events. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong --- include/linux/timekeeping.h | 3 +++ kernel/time/timekeeping.c | 54 +++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index fe1e467ba046..e5eb6699d691 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -289,6 +289,9 @@ extern int get_device_system_crosststamp( struct system_time_snapshot *history, struct system_device_crosststamp *xtstamp); +extern int ktime_convert_real_to_system_counter(ktime_t sys_realtime, + struct system_counterval_t *ret); + /* * Simultaneously snapshot realtime and monotonic raw clocks */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 266d02809dbb..ff6a4c7387ee 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -371,6 +371,19 @@ static void tk_setup_internals(struct timekeeper *tk, struct clocksource *clock) /* Timekeeper helper functions. */ +static inline int timekeeping_ns_to_delta(const struct tk_read_base *tkr, u64 nsec, + u64 *cycles) +{ + if (BITS_TO_BYTES(fls64(nsec) + tkr->shift) > sizeof(nsec)) + return -ERANGE; + + *cycles = nsec << tkr->shift; + *cycles -= tkr->xtime_nsec; + do_div(*cycles, tkr->mult); + + return 0; +} + static inline u64 timekeeping_delta_to_ns(const struct tk_read_base *tkr, u64 delta) { u64 nsec; @@ -1303,6 +1316,47 @@ int get_device_system_crosststamp(int (*get_time_fn) } EXPORT_SYMBOL_GPL(get_device_system_crosststamp); +/** + * ktime_convert_real_to_system_counter - Convert system time to system counter + * value + * @sys_realtime: realtime clock value to convert + * @ret: Computed system counter value with clocksource pointer + * + * Converts a supplied, future realtime clock value to the corresponding + * system counter value. + * + * Return: 0 on success, -errno on failure. + */ +int ktime_convert_real_to_system_counter(ktime_t sys_realtime, + struct system_counterval_t *ret) +{ + struct timekeeper *tk = &tk_core.timekeeper; + ktime_t base_real; + unsigned int seq; + u64 ns_delta; + int err; + + do { + seq = read_seqcount_begin(&tk_core.seq); + + base_real = ktime_add(tk->tkr_mono.base, + tk_core.timekeeper.offs_real); + if (ktime_compare(sys_realtime, base_real) < 0) + return -EINVAL; + + ret->cs = tk->tkr_mono.clock; + ns_delta = ktime_to_ns(ktime_sub(sys_realtime, base_real)); + err = timekeeping_ns_to_delta(&tk->tkr_mono, ns_delta, &ret->cycles); + if (err < 0) + return err; + + ret->cycles += tk->tkr_mono.cycle_last; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return 0; +} +EXPORT_SYMBOL_GPL(ktime_convert_real_to_system_counter); + /** * do_settimeofday64 - Sets the time of day. * @ts: pointer to the timespec64 variable containing the new time From patchwork Tue Oct 17 05:24:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153909 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911244vqb; Mon, 16 Oct 2023 22:25:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF11pdluegjJW9kvQcMoY+/pb0o4nrJsy7gg7ZQ0Ko788Nx8okl3n3H+7HPLcBCZvPVh8vK X-Received: by 2002:a05:6a20:8f2a:b0:163:d382:ba84 with SMTP id b42-20020a056a208f2a00b00163d382ba84mr1286039pzk.5.1697520356038; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id h9-20020a170902748900b001c5de4a5b4esi901311pll.597.2023.10.16.22.25.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:25:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="UuJ/N1K0"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 70FB180473FE; Mon, 16 Oct 2023 22:25:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234410AbjJQFZn (ORCPT + 19 others); Tue, 17 Oct 2023 01:25:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33370 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234622AbjJQFZY (ORCPT ); Tue, 17 Oct 2023 01:25:24 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 205DCD7E; Mon, 16 Oct 2023 22:25:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520311; x=1729056311; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=jjh/SQd4MKcrmxk2Fa2s9sU0ZxSrHMLhxc5ThbaVuPc=; b=UuJ/N1K0xGPfPqRXX8bzCpvgU1tOAzBuBp5rQMqscuYk7fM0lqhN4I9x fWtRPfkGm/zpJhBHvvMiUaFyh0NXg3C1wuelRwLqKK3uxJfBOTY4tscSN vDhiVVkO4WL1nwIBMiAW81YRxQie+TdObq1FFCivcdUpqjSRWoENX6j+R Kmo4LTyOWnlO6s5yrBva3gJ9TDmqcqXzZ4sQciW8kk2/5IZhRBxcmHtG1 IM+fweb40tUuYdqfq3DosCNrZsRotOdAuHOaw8rUDS2IeoKX3xSU5Yb7k qrumuBRiDX/UnvEMzA4LhRL3HYuY3MqsMcIUJWOlTLRks2qJe54JJaoG6 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561735" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561735" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:10 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087357990" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087357990" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:06 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 2/6] x86/tsc: Convert Time Stamp Counter (TSC) value to Always Running Timer (ART) Date: Tue, 17 Oct 2023 10:54:53 +0530 Message-Id: <20231017052457.25287-3-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:25:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979104707108376 X-GMAIL-MSGID: 1779979104707108376 From: Lakshmi Sowjanya D PPS generators trigger pulses according to system time/TSC. Timed I/O hardware understands time in ART (Always Running Timer). There is a need to convert TSC time to ART. The conversion is done using the detected art_to_tsc_numerator and denominator. ART = TSC * tsc_to_art_denominator / tsc_to_art_numerator Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong --- arch/x86/include/asm/tsc.h | 3 +++ arch/x86/kernel/tsc.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 594fce0ca744..f5cff8d4f61e 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -8,6 +8,8 @@ #include #include +struct system_counterval_t; + /* * Standard way to access the cycle counter. */ @@ -27,6 +29,7 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles +extern int convert_tsc_to_art(const struct system_counterval_t *tsc, u64 *art); extern struct system_counterval_t convert_art_to_tsc(u64 art); extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 15f97c0abc9d..92b800015d8f 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -2,6 +2,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include +#include #include #include #include @@ -1294,6 +1295,37 @@ int unsynchronized_tsc(void) return 0; } +/* + * Converts input TSC to the corresponding ART value using conversion + * factors discovered by detect_art(). + * + * Return: 0 on success, -errno on failure. + */ +int convert_tsc_to_art(const struct system_counterval_t *system_counter, + u64 *art) +{ + u64 tmp, res, rem; + /* ART = TSC * tsc_to_art_denominator / tsc_to_art_numerator */ + struct u32_fract tsc_to_art = { + .numerator = art_to_tsc_denominator, + .denominator = art_to_tsc_numerator, + }; + + if (system_counter->cs != art_related_clocksource) + return -EINVAL; + + res = system_counter->cycles - art_to_tsc_offset; + rem = do_div(res, tsc_to_art.denominator); + + tmp = rem * tsc_to_art.numerator; + do_div(tmp, tsc_to_art.denominator); + + *art = res * tsc_to_art.numerator + tmp; + + return 0; +} +EXPORT_SYMBOL_GPL(convert_tsc_to_art); + /* * Convert ART to TSC given numerator/denominator found in detect_art() */ From patchwork Tue Oct 17 05:24:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153910 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911301vqb; Mon, 16 Oct 2023 22:26:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG0S4pL0ZFvsQO9c1UIIOceCbK84OnNVWQ1j46HgXYDyPbxCLRkvtjVBAN2Ik+NPuVNl23P X-Received: by 2002:a05:6a00:1d09:b0:6bc:ff89:a2fc with SMTP id a9-20020a056a001d0900b006bcff89a2fcmr1273457pfx.2.1697520367825; Mon, 16 Oct 2023 22:26:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520367; cv=none; d=google.com; s=arc-20160816; b=xv80AThn42y2XxEUFJVop9KxoYwhYYc8aPbY27QUQImAoj/mgBLygsWMjEY+InpbTS jkyVQEGgL4stOFUi0CccuUiFIMCMLc4yQO4i5k2Sx/xM+xl14hJEjh5HpuOETyY1zGmn d2hD/pVaNobuk+/eaNlnn/g8camm3rG4eMLil4scdR1CKYHND8ijGycCzP0vZCfPd6bI RfarUxoTzGNNMOInOx2FgM3Ke/xwouBAmaK5Cxq6hqea/6G4BWBs6A2qbsIZF7GpjSYa 7paSliRBMUN1UG32qUeSoy9+7KPUJppDIhaXesenApQOVGChVjaRlHtd2pk4Tyt7sFwU RtLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=5VHCL6QifMk3HdRf9SKU2n9b95r9/BHr+7Gp/8xzW4A=; fh=O1j13Mu+YXmD8t08/npRM3Uw5SAxbjMOF7NW+nWn+v8=; b=PHVKO2Kzr2THBzb1K2ivSN7hERa38o/I11Nr7ObQCwA83oqTuX3V9T52K4qHmp96v0 x886vQbrtdn0fd+885PTbVRWW00toGxlMqW1RjtGO8zD41pre4Cz9DEUrHGaMROPqlEX nLyG+hArUOV+87zft7W0Xy4FtXxt0wmuetFAN++6VoZWSOK0GArO3al4qIafppH0fZZq K7XO33sqtblwZGvgf2Q38Nf7YSsZV3OhHp4GcL0Lot2DmJe+YMBfCRc/WgR+IwBpzfhg HW5sbNSXq3Y8LCIuDp9yiM66iQYHGeCqLCxEDnlHsf0lg9qvQvlGExXHZy1TW537+uEY gnXA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BUrl9gV6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id g1-20020a056a0023c100b006be03d801basi887048pfc.331.2023.10.16.22.26.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:26:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=BUrl9gV6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 37CCD802FB1B; Mon, 16 Oct 2023 22:26:03 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234467AbjJQFZu (ORCPT + 19 others); Tue, 17 Oct 2023 01:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234562AbjJQFZa (ORCPT ); Tue, 17 Oct 2023 01:25:30 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41C5D10DD; Mon, 16 Oct 2023 22:25:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520315; x=1729056315; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=zZsZ6JtO9YdL4Vld6agzB3/nEAv9fTcA8dq0o18MW2g=; b=BUrl9gV65NscXhHRrpQkdwbJB368xbk72nFvkteUnVRSpVT5lW83MLEn pLoFtjzNH2XG2kj71JpG8EPgCplkef89h6mleAD0kfTxzCcHb6WYdbx3w b/n/oGu5u4w+aV81WRJ4e2N0Gb9VVYk6a3PJApATabtGi5WJv3ZGJ7Xdb 2O9HHeAaXLTLHGRsIepc+2J4sp7xlIIg2l9ibaSfP/sTQJHgCSold4LqY OdfMhjJWv5o66LdZI61gIoEA+cOpJ5uc7xbJypeCUZlwiXjKM/ii2IzNQ Swiaum5sbOKUOdixg5OWUK8vqpD7LLbWti3RUkSz9c9C9avVUY5njKm1V g==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561752" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561752" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087357996" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087357996" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:10 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 3/6] x86/tsc: Check if the current clock source is related to ART(Always Running Timer) Date: Tue, 17 Oct 2023 10:54:54 +0530 Message-Id: <20231017052457.25287-4-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:26:03 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979117227924011 X-GMAIL-MSGID: 1779979117227924011 From: Lakshmi Sowjanya D Add interface 'is_current_clocksource_art_related()' in tsc.c to check if the current clock source is ART related. Add helper function 'is_current_clocksource(clock)' in timekeeping.c to check if the provided clock matches the current clock source. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Signed-off-by: Lakshmi Sowjanya D --- arch/x86/include/asm/tsc.h | 1 + arch/x86/kernel/tsc.c | 12 ++++++++++++ include/linux/timekeeping.h | 2 ++ kernel/time/timekeeping.c | 15 +++++++++++++++ 4 files changed, 30 insertions(+) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index f5cff8d4f61e..cdfe34e55cf3 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -32,6 +32,7 @@ static inline cycles_t get_cycles(void) extern int convert_tsc_to_art(const struct system_counterval_t *tsc, u64 *art); extern struct system_counterval_t convert_art_to_tsc(u64 art); extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); +extern bool is_current_clocksource_art_related(void); extern void tsc_early_init(void); extern void tsc_init(void); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 92b800015d8f..2d6b1b5b5b3e 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -1295,6 +1296,17 @@ int unsynchronized_tsc(void) return 0; } +/* + * Checks if the current clocksource is ART related clocksource + * + * Return: 1 on success, 0 on failure. + */ +bool is_current_clocksource_art_related(void) +{ + return is_current_clocksource(art_related_clocksource); +} +EXPORT_SYMBOL_GPL(is_current_clocksource_art_related); + /* * Converts input TSC to the corresponding ART value using conversion * factors discovered by detect_art(). diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index e5eb6699d691..9bf7970b3b2f 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -292,6 +292,8 @@ extern int get_device_system_crosststamp( extern int ktime_convert_real_to_system_counter(ktime_t sys_realtime, struct system_counterval_t *ret); +extern bool is_current_clocksource(struct clocksource *clock); + /* * Simultaneously snapshot realtime and monotonic raw clocks */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index ff6a4c7387ee..986089d36ba5 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1357,6 +1357,21 @@ int ktime_convert_real_to_system_counter(ktime_t sys_realtime, } EXPORT_SYMBOL_GPL(ktime_convert_real_to_system_counter); +/** + * is_current_clocksource - Checks if the supplied clock source matches with the + * MONOTONIC clock. + * + * @clock: pointer to the clocksource to be checked + * + * Return: true if the clocks match, false otherwise. + */ +bool is_current_clocksource(struct clocksource *clock) +{ + struct tk_read_base *tkr = &tk_core.timekeeper.tkr_mono; + return clock == READ_ONCE(tkr->clock); +} +EXPORT_SYMBOL_GPL(is_current_clocksource); + /** * do_settimeofday64 - Sets the time of day. * @ts: pointer to the timespec64 variable containing the new time From patchwork Tue Oct 17 05:24:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153911 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911331vqb; Mon, 16 Oct 2023 22:26:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXymo263oG3ECeatV7bDC1BkuKQj8idPV79BZPiUIwC5uIdkaJ/6Ybn/ptfexOnZbsY2gg X-Received: by 2002:a17:90b:4b44:b0:27d:1593:2b08 with SMTP id mi4-20020a17090b4b4400b0027d15932b08mr1391231pjb.0.1697520372163; Mon, 16 Oct 2023 22:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520372; cv=none; d=google.com; s=arc-20160816; b=CmUJ7Fg/7SUQ2mTIBB01VnphnVh5m/cXmdM/IdCSZcLQvgLBbnVI+zvQZx+nxWF2Ps EZVKlxbVEGcRo9m3aMGT4QdQgzNz/vTAFYsMGMgyh1SfIy7qhukEJ3BKkaOBZVBNKCFj 9m9z7RWrOCcO8hGY3Mt1p9SDaocFzxmVJ14hFR8CLbStdxedS29zykI5qztO+2xdOVP5 VcIv4+DdGwxZYJIfWQ2eU0PWC6kZN6QJriZA6DROGK2XNenK2qh5Axmvsx8E+rENc/r5 LfoiWsTDkTPdkg04zuXp56j7pZHb8Tya27ubA3/U0o5+ctlJ/mUdm0djLou+H5NkplOi fYSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=S+UBsbTGlWlhYYTSVtUsXBRxv6VI8zH97uXyirTFOtc=; fh=O1j13Mu+YXmD8t08/npRM3Uw5SAxbjMOF7NW+nWn+v8=; b=R9AbUdVvyPRmUSb9+5Bt2mYFez16zLQFUSC33u7EztSZggnr21S1afB3CdJlWKJ0Zm WmNj6dZjLIFrTG2uiHynryyRG/NuK0KYa9NCUQbFEwZb9gacRjWofKV2XwdIXWnHMRs+ lf3Z0xTlu03VwS2l8EuaV0S7UyipAB6+9vs36A1QTxFah1r5tSUQjiejpqUUWlbeGr+i aHe7u2fBej6ynmf1MYHga5C9JvlUl043+17MsANCTsJWC81Zrcw9t/qZl7YpdyvvAURE qaGopsPH3CKrhQRVvRoGWDFKE9kAX9ec3Sh5IJvXJoeHgXnnnxwLYd+5ChRX+E30TOyf 5jPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lkzQAeS3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id ds6-20020a17090b08c600b00263860e1f4csi7450307pjb.16.2023.10.16.22.26.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:26:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lkzQAeS3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2587080D44F5; Mon, 16 Oct 2023 22:26:11 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234504AbjJQF0B (ORCPT + 19 others); Tue, 17 Oct 2023 01:26:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234592AbjJQFZe (ORCPT ); Tue, 17 Oct 2023 01:25:34 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2CCE51BF; Mon, 16 Oct 2023 22:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520319; x=1729056319; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=sMUr0p6GsDTt7jB2LuU724MrPrsFBlCWOk8zjOW+ydE=; b=lkzQAeS3lx1+nQ7AMCY/s9kvdL6APZLA/FzZOuwP3UE6OVnp4ARM6CXC B42roIzMUmNJpmp356ndixK2RzwzIElcMSmEjIy/umv5yjSFWjRTD2+P1 Xq3V+qtXPtKOsuuDQuGkdOslbREvXbJdGc4ZM+t6W8oIU8bdOf+9tuZiA z0OoFGegYBJKfA/FZjwsfN/K7GQebFE4q5xewsJxRVCaLu052I8qpzGNV jWM49ivvVNU+xN8r86p4Bz3S0d2dm4JdxYeL9zH1BSwwXyCwY/KqUa28n iANpiept5r3M/0qcIOfyU2pEq9rWjDwYidq23/Vr3kCOWSUGLU2yBhYO8 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561762" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561762" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:18 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087358003" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087358003" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:14 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 4/6] pps: generators: Add PPS Generator TIO Driver Date: Tue, 17 Oct 2023 10:54:55 +0530 Message-Id: <20231017052457.25287-5-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:26:11 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979121349130388 X-GMAIL-MSGID: 1779979121349130388 From: Lakshmi Sowjanya D The Intel PPS Generator Timed IO driver provides PPS signal generation functionality. It uses hrtimers to schedule output. The timer handler writes the ART trigger value - derived from the system time - to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 302 +++++++++++++++++++++++++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makefile index 2d56dd0495d5..07004cfd3996 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_PPS_GENERATOR_PARPORT) += pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) += pps_gen_tio.o ifeq ($(CONFIG_PPS_DEBUG),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c new file mode 100644 index 000000000000..4ab7020a5cb6 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,302 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define PREP_INTERVAL_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer early */ + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; +}; + +static inline u32 pps_ctl_read(struct pps_tio *tio) +{ + return readl(tio->base + TIOCTL); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + struct timespec64 ts; + + ktime_get_real_ts64(&ts); + + return ktime_set(ts.tv_sec + 1, NSEC_PER_SEC - PREP_INTERVAL_NS); +} + +static int translate_system_time_to_art_cycles(struct timespec64 ts, u64 *art_timestamp, + bool *real_to_tsc_result) +{ + struct system_counterval_t sys_counter; + ktime_t sys_realtime; + int err; + + sys_realtime = timespec64_to_ktime(ts); + err = ktime_convert_real_to_system_counter(sys_realtime, &sys_counter); + if (err) { + *real_to_tsc_result = true; + return err; + } + + return convert_tsc_to_art(&sys_counter, art_timestamp); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_ctl_read(tio); + pps_compv_write(tio, 0); + + ctrl &= ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + + return ctrl; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &= ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |= TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + + ctrl |= TIOCTL_EN; + pps_ctl_write(tio, ctrl); +} + +static int pps_tio_generate_output(struct pps_tio *tio, struct timespec64 time) +{ + bool real_to_tsc_result; + u64 art_timestamp; + int err; + + real_to_tsc_result = false; + err = translate_system_time_to_art_cycles(time, &art_timestamp, &real_to_tsc_result); + if (err) { + pps_tio_disable(tio); + dev_err(tio->dev, "Disabling PPS due to failure in conversion of %s", + real_to_tsc_result ? "realtime to system_counter" : "tsc to art"); + return err; + } + /* The timed IO hardware adds a two cycle delay on output */ + art_timestamp -= 2; + pps_compv_write(tio, art_timestamp); + + return 0; +} + +static int schedule_event(struct hrtimer *timer, struct timespec64 *next_event) +{ + struct pps_tio *tio = container_of(timer, struct pps_tio, timer); + struct timespec64 expire_time, cur_time, roundoff; + long half_sec_ns = NSEC_PER_SEC / 2; + + /* get the current time */ + ktime_get_real_ts64(&cur_time); + expire_time = ktime_to_timespec64(hrtimer_get_softexpires(timer)); + + /* + * Figure out if it is in "top half" or "bottom half" of the second + * and round-off to the nearest 500ms + */ + if (cur_time.tv_nsec > half_sec_ns) { + roundoff.tv_sec = cur_time.tv_sec + 1; + roundoff.tv_nsec = 0; + next_event->tv_sec = roundoff.tv_sec; + next_event->tv_nsec = half_sec_ns; + } else { + roundoff.tv_sec = cur_time.tv_sec; + roundoff.tv_nsec = half_sec_ns; + next_event->tv_sec = roundoff.tv_sec; + next_event->tv_nsec = roundoff.tv_nsec + half_sec_ns; + } + next_event->tv_nsec -= PREP_INTERVAL_NS; + + /* Check for elapsed time */ + if (expire_time.tv_sec != cur_time.tv_sec || + (cur_time.tv_nsec - PREP_INTERVAL_NS) > expire_time.tv_nsec) { + dev_warn(tio->dev, "Time expired, edge not scheduled at time: %lld.%09ld\n", + cur_time.tv_sec, cur_time.tv_nsec); + return 0; + } + + return pps_tio_generate_output(tio, roundoff); +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio = container_of(timer, struct pps_tio, timer); + struct timespec64 next_event; + int err = 0; + + scoped_guard(spinlock_irqsave, &tio->lock) { + if (tio->enabled) + err = schedule_event(timer, &next_event); + } + if (err) + return HRTIMER_NORESTART; + + hrtimer_set_expires(timer, ktime_set(next_event.tv_sec, next_event.tv_nsec)); + + return HRTIMER_RESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *attr, const char *buf, + size_t count) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + bool enable; + int err; + + err = kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + if (!is_current_clocksource_art_related()) { + dev_err(tio->dev, "PPS cannot be started as clock is not related to ART"); + return -EPERM; + } + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + tio->enabled = true; + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + tio->enabled = false; + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + u32 ctrl; + + ctrl = pps_ctl_read(tio); + ctrl &= TIOCTL_EN; + + return sysfs_emit(buf, "%u\n", ctrl); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] = { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_tio_probe(struct platform_device *pdev) +{ + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(&pdev->dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio = devm_kzalloc(&pdev->dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev = &pdev->dev; + tio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function = hrtimer_callback; + spin_lock_init(&tio->lock); + tio->enabled = false; + platform_set_drvdata(pdev, tio); + + return 0; +} + +static int pps_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio = platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + + return 0; +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_tio_driver = { + .probe = pps_tio_probe, + .remove = pps_tio_remove, + .driver = { + .name = "intel-pps-generator", + .acpi_match_table = intel_pmc_tio_acpi_match, + .dev_groups = pps_tio_groups, + }, +}; +module_platform_driver(pps_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); From patchwork Tue Oct 17 05:24:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153913 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911437vqb; Mon, 16 Oct 2023 22:26:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEK4tMwoDv3fJo0Ss4mF72Nyka+hTG2Q72q866evf8mSWprJOtFSZm+EgBnct9qDGJrZXqf X-Received: by 2002:a54:448e:0:b0:3a9:f25d:d917 with SMTP id v14-20020a54448e000000b003a9f25dd917mr1485813oiv.4.1697520392739; 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[23.128.96.36]) by mx.google.com with ESMTPS id cm18-20020a056a020a1200b00578d7a3a4fdsi882914pgb.563.2023.10.16.22.26.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:26:32 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Nbm82nea; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 70E4A802FA6A; Mon, 16 Oct 2023 22:26:30 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234673AbjJQF0D (ORCPT + 19 others); Tue, 17 Oct 2023 01:26:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34530 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234656AbjJQFZh (ORCPT ); Tue, 17 Oct 2023 01:25:37 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8171D1B5; Mon, 16 Oct 2023 22:25:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520323; x=1729056323; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=Ui1Hqm41JSxotFlyE4G0v69tZLA9xc0/FYrcSUnN77Y=; b=Nbm82neaf8pjai/Dy54azXizfXgtaURLoYmzxufKk6uy9d3WxcIzQOTT L+hlwlb7fnxLpcxqUavMUwmTi5g8z/HHGIaQro14o2U6/XEaPAkwR/f4L DNmlby21/WU0ohkl7jd4LMBEs8zIMAet8ohI+wkFYaCfSyO8+I51EZ8YF 3rIULRvrdQhEBSJEvdoixFkrefb8CRXkWWFTMtdyi3ZkzT/wOXVI24ITi rEVJnZ7BmQgxHVKI52SpQ+2j67FgTb6aeFut32VlE74vIp6W0csMesqXF PGxaM3ONt3Yh8jPjxu1vfEJk/hn312MjYemNmq7CyZ6gaYe/5FUdQAH9H w==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561779" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561779" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087358019" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087358019" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:18 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 5/6] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Tue, 17 Oct 2023 10:54:56 +0530 Message-Id: <20231017052457.25287-6-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:26:30 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979143658207976 X-GMAIL-MSGID: 1779979143658207976 From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pps.rst index 2d6b99766ee8..35bba2bf98a8 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -240,3 +240,25 @@ delay between assert and clear edge as small as possible to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signal. + +Timed I/O and system time are both driven by same hardware clock, The signal +generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +Share your clock with a device that receives PPS signal, generated by +Timed I/O device. There are dedicated Timed I/O pins to deliver PPS signal +to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable From patchwork Tue Oct 17 05:24:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 153912 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3911390vqb; Mon, 16 Oct 2023 22:26:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEd1oapcRfajb+N+OUzCB8DeLshrNbuTf5vXSAK7uwXogE28PfIBHpXTQULitDjXTjlW/NV X-Received: by 2002:a05:6a20:c182:b0:13d:fff1:c672 with SMTP id bg2-20020a056a20c18200b0013dfff1c672mr1257203pzb.4.1697520383907; Mon, 16 Oct 2023 22:26:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520383; cv=none; d=google.com; s=arc-20160816; b=nOxWVrU4zFhpCgpRTIPbReh0Ix1We2aive8N90L1NvA6kDQP1ymSmtb9qVCMOeGbbd 6X1AUzb2VU/BmJy/b5+Vk0B9BcZFJKUGJKk95Tz3X3WIorplQ9tuHsRIaHhi1e3CYOZh LQrKa49E2q/AhENTdCQ0WIEHznobh/vtxL0F80goukphtv/F3DMdBCxNiQhRZ5se4fPR UIe9G9UO0Tr+Sa4CyoqfvaoeSgMj2AK7ftWzGltA/2J8QOnZL9IKi/asu4uMdHB8Mt7H TqO7ExJ+zWx9LfSTM829U9nC5a3BddbpwxuJIvJ4A1ejjhMQyLuLGrz5gkNbSJeWYSiq NA2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=oSJBz9wyw9+lDrmiamGBkyJuFjic6nxBfhFPmuJbPo0=; fh=O1j13Mu+YXmD8t08/npRM3Uw5SAxbjMOF7NW+nWn+v8=; b=VX7HEhWdLyWYzRkwK94f6bHm8o8QW0pBOWGjAmiz8nlqwit9O6llfWZkY6U4Tpg23T 0PhNvRzuMnfhhn5AkHyvxu3GEnKLILd64iYwJjOM9dUJAIVfme06cI7sStdYp52hf6st YxEh+6DqqeldSI8LTWjFhC5sPjxEE/oR8oM9nduM9sj3il7WDoVd/nCd39y4yF2FEy5v ymyGNaQJrO/alSwvhmujnWMSPZzguyS918Fb8gRmH70qZoT0HgagAtDPFACfwdZNOuxL b+EwzS9qELlE4F91jVV9rAbLyCh7wouu7B8TMGNpu6RMak2HlpVIrIMRsdRbUzzwnP2J piHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CdCx5rS+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id c4-20020a170902c1c400b001c9af5305dasi919061plc.126.2023.10.16.22.26.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:26:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=CdCx5rS+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id D5953802FB18; Mon, 16 Oct 2023 22:26:21 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234399AbjJQF0H (ORCPT + 19 others); Tue, 17 Oct 2023 01:26:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234541AbjJQFZi (ORCPT ); Tue, 17 Oct 2023 01:25:38 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B541E8; Mon, 16 Oct 2023 22:25:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697520327; x=1729056327; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=R2Jsg78czvuZbCB0J7ctuq7XItBBFyIcdUtpVY0Wy+4=; b=CdCx5rS+vsR1U94YyuI5Nd84A9pvyQHaeW86dL3IBm9kKk8rlNALP+nm Vq0vSgi78cne8l1VGUbQOKz+NiMTircQV6dRfv0p7icsnTxzKh09d+gNA p1AqxAYbPUXhDqxtvw6ryOcavdVsD9PiTibHPzx201iswcg3zl6PT6l5G 9aMAZMtmYpuB2yY9qEklFLR+cdP8XHiHDqvRQORznl8sy6euo3Acp2T6q k62rsK7rHtxbGaafat3E1fHk4lruVNZPE+lwKCVTz5Vb7SsiAZAPTL7PG zmJ/AZ7xb6AUQB9O1QrjtUvZzxIvGMQMs9CIvilN0TiZdLkIOfSIpHQ7R g==; X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="388561793" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="388561793" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Oct 2023 22:25:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10865"; a="1087358023" X-IronPort-AV: E=Sophos;i="6.03,231,1694761200"; d="scan'208";a="1087358023" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmsmga005.fm.intel.com with ESMTP; 16 Oct 2023 22:25:22 -0700 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, linux-doc@vger.kernel.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v1 6/6] ABI: pps: Add ABI documentation for Intel TIO Date: Tue, 17 Oct 2023 10:54:57 +0530 Message-Id: <20231017052457.25287-7-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> References: <20231017052457.25287-1-lakshmi.sowjanya.d@intel.com> X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:26:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779979133806400358 X-GMAIL-MSGID: 1779979133806400358 From: Lakshmi Sowjanya D Document sysfs interface for Intel Timed I/O PPS driver Signed-off-by: Lakshmi Sowjanya D --- Documentation/ABI/testing/sysfs-platform-pps-tio | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentation/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..d8be3a6d5795 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,7 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: January 2024 +KernelVersion 6.8 +Contact: Lakshmi Sowjanya D +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware(Enabled/Disabled).