From patchwork Tue Oct 17 05:23:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 153898 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3910578vqb; Mon, 16 Oct 2023 22:23:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIYbz5DQ2J3WgzI8uHj+zOPaTSQBDRb73JIInaO5j2M6Vq9dZFV6yYiie2TZnld/2PPxK0 X-Received: by 2002:a05:6870:b494:b0:1ea:bb5:a534 with SMTP id y20-20020a056870b49400b001ea0bb5a534mr1286140oap.5.1697520225502; Mon, 16 Oct 2023 22:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520225; cv=none; d=google.com; s=arc-20160816; b=oC/NLEFTXOcNAe7zBZb0n7Q2Pppnk6ctVs0jtsckuzRbteGQKUMYqL0Uuq+y/SUik2 26RptpOMZs9Lkv814GCYrtT2zUNVQjsIsgcvTiUxwoP5j1wQIikGDqXSNuKRLPSGzyl/ H5ixJxPE4RScIV7UICUe9vmQt0jAwe5BgYrspLWJigLu4GxmciP+lOP73Z+O4Z2ktYRd j2S6RB7BQ03t4UvcYRKQ21WGgHWtJolwfBUv0mLEIvaiDUkZbzhIP1rkYAXIvhQQlaRd ArFpRyYhs8k/f17WTNe3ewHSd/KRsOcSVD5S2tCs3TGHafyxKZsuRuPL9f2YfX+PKXgd eEtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZyMGwZpnewEhjYPyY9zqBgCiT27UfdJFK5InUe6YZsc=; fh=b707ZlehUqHbBbDb3qCjPEW7g+Wmx1If0BLFmHa/lXg=; b=PI7Q6XI+QiW6/vVzVKt11qTl+YvtaVjqES8yRfBtP7dvZvXlRlNcLsZmmSQOKw3mvZ x8MJXUYua9LDwfYJrtYf98i7u74o04xNG/SU2UXHbR9qiWLvvg4Gw5sHnzhsk0CDq6Yn 17www0mNFy7HVLMeMLIkFd8HRlUAzQRQaHWS23Jmh9+PjDZLx5stxN1WBuAWKFxFU40L /BS4K6Gwio/1vmznSEfZ6NefJfo6gKbWKEoHkJ4QFITocoi9BeLPtLr+1cZbzbo+YXgw JWgDnuOGGKUJ9ED3JpLSOtv0bNnFMAO9xUnW19PqDMeQvGJxKzK92b7ebwLI82c2w/1t jpbg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id y64-20020a636443000000b005b32ca3f714si981815pgb.718.2023.10.16.22.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:23:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DA34180D44D5; Mon, 16 Oct 2023 22:23:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234399AbjJQFXh (ORCPT + 19 others); Tue, 17 Oct 2023 01:23:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234284AbjJQFXf (ORCPT ); Tue, 17 Oct 2023 01:23:35 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 9D6FCA4 for ; Mon, 16 Oct 2023 22:23:33 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BD9D72F4; Mon, 16 Oct 2023 22:24:13 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0347E3F5A1; Mon, 16 Oct 2023 22:23:32 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 1/3] arm64: cpufeature: Display the set of cores with a feature Date: Tue, 17 Oct 2023 00:23:20 -0500 Message-ID: <20231017052322.1211099-2-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:23:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779978967802285281 X-GMAIL-MSGID: 1779978967802285281 The AMU feature can be enabled on a subset of the cores in a system. Because of that, it prints a message for each core as it is detected. This becomes tedious when there are hundreds of cores. Instead, for CPU features which can be enabled on a subset of the present cores, lets wait until update_cpu_capabilities() and print the subset of cores the feature was enabled on. Signed-off-by: Jeremy Linton Reviewed-by: Ionela Voinescu Tested-by: Ionela Voinescu Reviewed-by: Punit Agrawal Tested-by: Punit Agrawal --- arch/arm64/include/asm/cpufeature.h | 2 ++ arch/arm64/kernel/cpufeature.c | 22 +++++++++++++--------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 5bba39376055..19b4d001d845 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -23,6 +23,7 @@ #include #include #include +#include /* * CPU feature register tracking @@ -380,6 +381,7 @@ struct arm64_cpu_capabilities { * method is robust against being called multiple times. */ const struct arm64_cpu_capabilities *match_list; + const struct cpumask *cpus; }; static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 444a73c2e638..2dd695fc3472 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1944,8 +1944,6 @@ int get_cpu_with_amu_feat(void) static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap) { if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) { - pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n", - smp_processor_id()); cpumask_set_cpu(smp_processor_id(), &amu_cpus); /* 0 reference values signal broken/disabled counters */ @@ -2405,16 +2403,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { #endif /* CONFIG_ARM64_RAS_EXTN */ #ifdef CONFIG_ARM64_AMU_EXTN { - /* - * The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y. - * Therefore, don't provide .desc as we don't want the detection - * message to be shown until at least one CPU is detected to - * support the feature. - */ + .desc = "Activity Monitors Unit (AMU)", .capability = ARM64_HAS_AMU_EXTN, .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .matches = has_amu, .cpu_enable = cpu_amu_enable, + .cpus = &amu_cpus, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, AMU, IMP) }, #endif /* CONFIG_ARM64_AMU_EXTN */ @@ -2981,7 +2975,7 @@ static void update_cpu_capabilities(u16 scope_mask) !caps->matches(caps, cpucap_default_scope(caps))) continue; - if (caps->desc) + if (caps->desc && !caps->cpus) pr_info("detected: %s\n", caps->desc); __set_bit(caps->capability, system_cpucaps); @@ -3330,6 +3324,7 @@ unsigned long cpu_get_elf_hwcap2(void) static void __init setup_system_capabilities(void) { + int i; /* * We have finalised the system-wide safe feature * registers, finalise the capabilities that depend @@ -3338,6 +3333,15 @@ static void __init setup_system_capabilities(void) */ update_cpu_capabilities(SCOPE_SYSTEM); enable_cpu_capabilities(SCOPE_ALL & ~SCOPE_BOOT_CPU); + + for (i = 0; i < ARM64_NCAPS; i++) { + const struct arm64_cpu_capabilities *caps = cpucap_ptrs[i]; + + if (caps && caps->cpus && caps->desc && + cpumask_any(caps->cpus) < nr_cpu_ids) + pr_info("detected: %s on CPU%*pbl\n", + caps->desc, cpumask_pr_args(caps->cpus)); + } } void __init setup_cpu_features(void) From patchwork Tue Oct 17 05:23:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 153900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3910660vqb; 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[23.128.96.38]) by mx.google.com with ESMTPS id r3-20020aa79ec3000000b006be0b790ebfsi832605pfq.255.2023.10.16.22.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:24:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 478F380A236F; Mon, 16 Oct 2023 22:23:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234284AbjJQFXl (ORCPT + 19 others); Tue, 17 Oct 2023 01:23:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234391AbjJQFXg (ORCPT ); Tue, 17 Oct 2023 01:23:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id E1B70B6 for ; Mon, 16 Oct 2023 22:23:34 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1A283FEC; Mon, 16 Oct 2023 22:24:15 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 507A03F5A1; Mon, 16 Oct 2023 22:23:34 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 2/3] arm64: cpufeature: Change DBM to display enabled cores Date: Tue, 17 Oct 2023 00:23:21 -0500 Message-ID: <20231017052322.1211099-3-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:23:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779978983473848502 X-GMAIL-MSGID: 1779978983473848502 Now that we have the ability to display the list of cores with a feature when its selectivly enabled, lets convert DBM to use that as well. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 33 ++++++++------------------------- 1 file changed, 8 insertions(+), 25 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2dd695fc3472..b7b67bac0e60 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1848,6 +1848,8 @@ static int __init parse_kpti(char *str) early_param("kpti", parse_kpti); #ifdef CONFIG_ARM64_HW_AFDBM +static struct cpumask dbm_cpus __read_mostly; + static inline void __cpu_enable_hw_dbm(void) { u64 tcr = read_sysreg(tcr_el1) | TCR_HD; @@ -1883,35 +1885,22 @@ static bool cpu_can_use_dbm(const struct arm64_cpu_capabilities *cap) static void cpu_enable_hw_dbm(struct arm64_cpu_capabilities const *cap) { - if (cpu_can_use_dbm(cap)) + if (cpu_can_use_dbm(cap)) { __cpu_enable_hw_dbm(); + cpumask_set_cpu(smp_processor_id(), &dbm_cpus); + } } static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap, int __unused) { - static bool detected = false; /* * DBM is a non-conflicting feature. i.e, the kernel can safely * run a mix of CPUs with and without the feature. So, we * unconditionally enable the capability to allow any late CPU * to use the feature. We only enable the control bits on the - * CPU, if it actually supports. - * - * We have to make sure we print the "feature" detection only - * when at least one CPU actually uses it. So check if this CPU - * can actually use it and print the message exactly once. - * - * This is safe as all CPUs (including secondary CPUs - due to the - * LOCAL_CPU scope - and the hotplugged CPUs - via verification) - * goes through the "matches" check exactly once. Also if a CPU - * matches the criteria, it is guaranteed that the CPU will turn - * the DBM on, as the capability is unconditionally enabled. + * CPU, if it is supported. */ - if (!detected && cpu_can_use_dbm(cap)) { - detected = true; - pr_info("detected: Hardware dirty bit management\n"); - } return true; } @@ -2448,18 +2437,12 @@ static const struct arm64_cpu_capabilities arm64_features[] = { }, #ifdef CONFIG_ARM64_HW_AFDBM { - /* - * Since we turn this on always, we don't want the user to - * think that the feature is available when it may not be. - * So hide the description. - * - * .desc = "Hardware pagetable Dirty Bit Management", - * - */ + .desc = "Hardware dirty bit management", .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, .capability = ARM64_HW_DBM, .matches = has_hw_dbm, .cpu_enable = cpu_enable_hw_dbm, + .cpus = &dbm_cpus, ARM64_CPUID_FIELDS(ID_AA64MMFR1_EL1, HAFDBS, DBM) }, #endif From patchwork Tue Oct 17 05:23:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeremy Linton X-Patchwork-Id: 153899 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3910615vqb; Mon, 16 Oct 2023 22:23:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFo3CNMUtn4uHxWIbB2D547Wt0aGj3ugReCPhw62HrJ8R6qw+yqJdlzL+xuONtgOWNzKuPd X-Received: by 2002:a05:6359:320a:b0:166:d975:8dab with SMTP id rj10-20020a056359320a00b00166d9758dabmr1130686rwb.1.1697520230926; Mon, 16 Oct 2023 22:23:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697520230; cv=none; d=google.com; s=arc-20160816; b=SirNrNycmHMkcR9B6/W6rzT+zluR1mQa3smOHJhYsyrmZDOAAObyztAXN6mOfULNXl cMxM4s+eXCptiC5ubdI7J+YYBIUeU2cFYSWPDR+o6Fusi6lP3bMPt6XGJ7s6rgbPbpzz 0qjIWcm5JsGiG3fPzfYhdTYPX87wDSQdRxaBYsMEEb1wn8cePubtGYHFRE6UN/cPZC83 R05zCxjGl3k4WL+x3ptYhYsSZe1wZbTmcrV0GQgDAE9w3rdiHFVbacnf7mWQhvz7tx5K CoSlycknQgYXT3LEBtOC0iF6SEXphL7eTxuaIPE9GmyTj9O+Df1caxKzqtgK6dSzxRhP azaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ufqTjBedOVdrSTOHaVd1HxFVfqH9408NzbgFWLYz7Fg=; fh=b707ZlehUqHbBbDb3qCjPEW7g+Wmx1If0BLFmHa/lXg=; b=L3/OgKbNpeq9U15FXO34a9XJOVWWjKX9uo/t6iD9+7Lwvr8V127Na11/Cuk2H4pf6n LxwQ4/ZjjII0N6nFZ7MdWEXBjrXiKjTqE0W1NX76NP2fkzRVywvIK0gImrGeR+J8e9ye CwXBfq3uS0JPVR+81UpUHWbfh4+N8xNeAoO8cF/7lwHAHSCQEh0ySUp/HRBZMJgcv77m 65qk124kt7mVLxP3SCQajB34RiTevfTZI2ifK38P1qT29nNz+EHOLGac/I6XgutNoSUI QZpB+d8fQSLkKyszQoq/mmWhUFgz+gvUVAAKR6b3pvqGGNY6n3MZeyyJLjiwq/FLCI0z U2NA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id o10-20020a656a4a000000b005ae39764b64si1401401pgu.135.2023.10.16.22.23.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 22:23:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 536BC80D44E9; Mon, 16 Oct 2023 22:23:50 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234441AbjJQFXq (ORCPT + 19 others); Tue, 17 Oct 2023 01:23:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234396AbjJQFXh (ORCPT ); Tue, 17 Oct 2023 01:23:37 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 0C0AEA4 for ; Mon, 16 Oct 2023 22:23:36 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3C2961007; Mon, 16 Oct 2023 22:24:16 -0700 (PDT) Received: from u200865.usa.arm.com (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 724BB3F5A1; Mon, 16 Oct 2023 22:23:35 -0700 (PDT) From: Jeremy Linton To: linux-arm-kernel@lists.infradead.org Cc: catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, maz@kernel.org, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org, Jeremy Linton Subject: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores Date: Tue, 17 Oct 2023 00:23:22 -0500 Message-ID: <20231017052322.1211099-4-jeremy.linton@arm.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231017052322.1211099-1-jeremy.linton@arm.com> References: <20231017052322.1211099-1-jeremy.linton@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 16 Oct 2023 22:23:50 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779978973527845144 X-GMAIL-MSGID: 1779978973527845144 Now that we have the ability to display the list of cores with a feature when it is selectivly enabled, lets display the cores enabled for 32-bit use at EL0. Signed-off-by: Jeremy Linton --- arch/arm64/kernel/cpufeature.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7b67bac0e60..512cbe446b41 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) if (!has_cpuid_feature(entry, scope)) return allow_mismatched_32bit_el0; - if (scope == SCOPE_SYSTEM) - pr_info("detected: 32-bit EL0 Support\n"); + if (scope == SCOPE_SYSTEM) { + struct arm64_cpu_capabilities *has_32bit; + + has_32bit = (struct arm64_cpu_capabilities *)entry; + + has_32bit->cpus = system_32bit_el0_cpumask(); + if (has_32bit->cpus == cpu_possible_mask) + has_32bit->cpus = cpu_online_mask; + if (has_32bit->cpus == cpu_none_mask) + has_32bit->cpus = NULL; + } return true; } @@ -2307,9 +2316,11 @@ static const struct arm64_cpu_capabilities arm64_features[] = { ARM64_CPUID_FIELDS(ID_AA64MMFR2_EL1, NV, IMP) }, { + .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0_DO_NOT_USE, .type = ARM64_CPUCAP_SYSTEM_FEATURE, .matches = has_32bit_el0, + .cpus = cpu_none_mask, ARM64_CPUID_FIELDS(ID_AA64PFR0_EL1, EL0, AARCH32) }, #ifdef CONFIG_KVM