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Mon, 16 Oct 2023 09:43:00 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779931122509605212 X-GMAIL-MSGID: 1779931122509605212 Difference layerscape chip have not difference exit_from_l2() method. Using function pointer for ls1028. It prepare for other layerscape suspend/resume support. Signed-off-by: Frank Li --- Notes: Change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index b931d597656f..20c48c06e224 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -39,6 +39,8 @@ struct ls_pcie_drvdata { const u32 pf_off; + const struct dw_pcie_host_ops *ops; + void (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; }; @@ -180,6 +182,7 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, + .exit_from_l2 = ls_pcie_exit_from_l2, }; static const struct of_device_id ls_pcie_of_match[] = { @@ -213,7 +216,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->drvdata = of_device_get_match_data(dev); pci->dev = dev; - pci->pp.ops = &ls_pcie_host_ops; + pci->pp.ops = pcie->drvdata->ops ? pcie->drvdata->ops : &ls_pcie_host_ops; pcie->pci = pci; @@ -251,7 +254,7 @@ static int ls_pcie_resume_noirq(struct device *dev) if (!pcie->drvdata->pm_support) return 0; - ls_pcie_exit_from_l2(&pcie->pci->pp); + pcie->drvdata->exit_from_l2(&pcie->pci->pp); return dw_pcie_resume_noirq(pcie->pci); } From patchwork Mon Oct 16 16:17:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 153564 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3578709vqb; Mon, 16 Oct 2023 09:27:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE32UfWwHU0eILepGc/dKwnS3DF9WMPIfwnmB8xM3SGPaMssN5AkvH2MGNFRvpNF7oQLpnO X-Received: by 2002:a05:6a00:1622:b0:6bc:ff89:a2fc with SMTP id e2-20020a056a00162200b006bcff89a2fcmr5650024pfc.2.1697473643187; Mon, 16 Oct 2023 09:27:23 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697473643; cv=pass; d=google.com; s=arc-20160816; b=xDUOpmsPbnTNcAmMA9g0WnRpago1Gc6MySH+t0B1GPkLVCYsc7jABeU7TnEd6j4buf OoSwj1QdXwsYX+OZMk2ZJqrKVA4BrSKNw0F+c7IvOIGAMqyxIVSgmtUDxfFCnCbO6sGI 8l2R7I49RXYHVkyypEMcw0BE7und3xgmD/iGjaEbHrCGdwOMRsFksGeub5HMWbt0SIKN npckpKZfQfPBarKUeJ93txUQ4IrqqVo4PHAqhF2e51G0KbPb9Kfq0oishkmfd/wWMTLU hcKKTizoGyUhtUCZ3DkYRQ+ekXBOEsdRya9gaGofd3ruNoF9Nphp4QDme/wtzPUvbh50 Vz9A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IOR1gcPXA5TFwOrIuNws68vaKmjJdzXEgvOYYEXiSLk=; fh=hcaUxgS2XlQHla+W5HfOGEcJunKFhPD6I/OsnpJytRE=; b=OyeKO9sIySVh6+gZzkQEtmYBePOMkrWWBJobq9n7T2qlOy7+bQkfAcPL/tBj6dzo0d dYvfg28GsT3KLI/hS/neYGTCyX2mN+F8HAyaQpsfrUkmvKwhtFM9e1mZ5EIxA5xpqcNA dp54RM9TUJYjSHueCga6xC32SokW/76spKJKtLCswCQ7/5GKcTPqzr2X7WacYeJgW9mG OtjNj9gq1GWPDfV18RcSrAjMXzpaQl5wSIOwO3q9qAmUOdsIbg+C9lDndunh08NwLDN8 8ZQpWnJxLU6DpbHDIB++CqMooIafPVZxDOlOfuzNDPIRBT14KSDMo4dUVMRbvf10oKle cXDg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=hyP5aQX4; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from pete.vger.email (pete.vger.email. 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Mon, 16 Oct 2023 09:27:17 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779930122864206178 X-GMAIL-MSGID: 1779930122864206178 ls1021a add suspend/resume support. Signed-off-by: Frank Li --- Notes: change from v1 to v2 - change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 88 ++++++++++++++++++++- 1 file changed, 87 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index 20c48c06e224..bc5a8ff1a26c 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -35,6 +35,12 @@ #define PF_MCR_PTOMR BIT(0) #define PF_MCR_EXL2S BIT(1) +/* LS1021A PEXn PM Write Control Register */ +#define SCFG_PEXPMWRCR(idx) (0x5c + (idx) * 0x64) +#define PMXMTTURNOFF BIT(31) +#define SCFG_PEXSFTRSTCR 0x190 +#define PEXSR(idx) BIT(idx) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { @@ -48,6 +54,8 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + struct regmap *scfg; + int index; bool big_endian; }; @@ -170,13 +178,91 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) return 0; } +static void ls1021a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val |= PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); + + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), &val); + val &= ~PMXMTTURNOFF; + regmap_write(pcie->scfg, SCFG_PEXPMWRCR(pcie->index), val); +} + +static void ls1021a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val |= PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); + + regmap_read(pcie->scfg, SCFG_PEXSFTRSTCR, &val); + val &= ~PEXSR(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXSFTRSTCR, val); +} + +static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + struct device *dev = pcie->pci->dev; + u32 index[2]; + int ret; + + ret = ls_pcie_host_init(pp); + if (ret) + return ret; + + pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node, "fsl,pcie-scfg"); + if (IS_ERR(pcie->scfg)) { + ret = PTR_ERR(pcie->scfg); + dev_err(dev, "No syscfg phandle specified\n"); + pcie->scfg = NULL; + return ret; + } + + ret = of_property_read_u32_array(dev->of_node, "fsl,pcie-scfg", index, 2); + if (ret) { + pcie->scfg = NULL; + return ret; + } + + pcie->index = index[1]; + + return ret; +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, }; +static const struct dw_pcie_host_ops ls1021a_pcie_host_ops = { + .host_init = ls1021a_pcie_host_init, + .pme_turn_off = ls1021a_pcie_send_turnoff_msg, +}; + static const struct ls_pcie_drvdata ls1021a_drvdata = { - .pm_support = false, + .pm_support = true, + .ops = &ls1021a_pcie_host_ops, + .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; static const struct ls_pcie_drvdata layerscape_drvdata = { From patchwork Mon Oct 16 16:17:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 153553 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3574778vqb; Mon, 16 Oct 2023 09:20:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMBm82IrjHFwucRQppshP45MihqdbOcQpE21mtOAaN76fOju/R5lB99czPXu9DzcfKpeQy X-Received: by 2002:a05:6870:e86:b0:1ea:7463:1b8f with SMTP id mm6-20020a0568700e8600b001ea74631b8fmr860350oab.0.1697473253288; Mon, 16 Oct 2023 09:20:53 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697473253; cv=pass; d=google.com; s=arc-20160816; b=sYEkRNCz8UjC4nGANa0YqEmpp5zfqWT5kvOBB3LY2qgiwDPhdK9BEmepR7ARaFXwFt nItE5cCp1a106N7xPiw7ldFcQltqyCvXNWizI864NP3/u0SyLkclpPX4VQXY/DaPV7Je wj+t8PJOv9AjTbzf16pdTuSvi4KqUtx3vSshv26m7ad0gm+DK5IxI3TK5a9oSibmuj2Q +kmCuP5dUDk+wPHdRbBVby6Opcl5BHFXPdfYxdADC/2mNuK2DlJSqzaQW+yFmXEkNdh4 RRWzjl1X5EZ69WU0ffa90oDMpZ4+6fN5WTN7mdBMfj/26ZuIU5UDATrJvYyCaIF5KZo5 s94A== ARC-Message-Signature: i=2; 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Mon, 16 Oct 2023 09:20:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779929713943411385 X-GMAIL-MSGID: 1779929713943411385 ls1043a add suspend/resume support. Signed-off-by: Frank Li --- Notes: Change from v1 to v2 - Change subject 'a' to 'A' drivers/pci/controller/dwc/pci-layerscape.c | 91 ++++++++++++++++++++- 1 file changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index bc5a8ff1a26c..debabb9bb41f 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -41,10 +41,20 @@ #define SCFG_PEXSFTRSTCR 0x190 #define PEXSR(idx) BIT(idx) +/* LS1043A PEX PME control register */ +#define SCFG_PEXPMECR 0x144 +#define PEXPME(idx) BIT(31 - (idx) * 4) + +/* LS1043A PEX LUT debug register */ +#define LS_PCIE_LDBG 0x7fc +#define LDBG_SR BIT(30) +#define LDBG_WE BIT(31) + #define PCIE_IATU_NUM 6 struct ls_pcie_drvdata { const u32 pf_off; + const u32 lut_off; const struct dw_pcie_host_ops *ops; void (*exit_from_l2)(struct dw_pcie_rp *pp); bool pm_support; @@ -54,6 +64,7 @@ struct ls_pcie { struct dw_pcie *pci; const struct ls_pcie_drvdata *drvdata; void __iomem *pf_base; + void __iomem *lut_base; struct regmap *scfg; int index; bool big_endian; @@ -116,6 +127,23 @@ static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) iowrite32(val, pcie->pf_base + off); } +static u32 ls_pcie_lut_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->lut_base + off); + + return ioread32(pcie->lut_base + off); +} + +static void ls_pcie_lut_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + iowrite32be(val, pcie->lut_base + off); + else + iowrite32(val, pcie->lut_base + off); +} + + static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -249,6 +277,54 @@ static int ls1021a_pcie_host_init(struct dw_pcie_rp *pp) return ret; } +static void ls1043a_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + if (!pcie->scfg) { + dev_dbg(pcie->pci->dev, "SYSCFG is NULL\n"); + return; + } + + /* Send Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val |= PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); + + /* There are not register to check ACK, so wait PCIE_PME_TO_L2_TIMEOUT_US */ + mdelay(PCIE_PME_TO_L2_TIMEOUT_US/1000); + + /* Clear Turn_off message */ + regmap_read(pcie->scfg, SCFG_PEXPMECR, &val); + val &= ~PEXPME(pcie->index); + regmap_write(pcie->scfg, SCFG_PEXPMECR, val); +} + +static void ls1043a_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val |= LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_SR; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); + + val = ls_pcie_lut_readl(pcie, LS_PCIE_LDBG); + val &= ~LDBG_WE; + ls_pcie_lut_writel(pcie, LS_PCIE_LDBG, val); +} + static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, .pme_turn_off = ls_pcie_send_turnoff_msg, @@ -265,6 +341,18 @@ static const struct ls_pcie_drvdata ls1021a_drvdata = { .exit_from_l2 = ls1021a_pcie_exit_from_l2, }; +static const struct dw_pcie_host_ops ls1043a_pcie_host_ops = { + .host_init = ls1021a_pcie_host_init, /* the same as ls1021 */ + .pme_turn_off = ls1043a_pcie_send_turnoff_msg, +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .lut_off = 0x10000, + .pm_support = true, + .ops = &ls1043a_pcie_host_ops, + .exit_from_l2 = ls1043a_pcie_exit_from_l2, +}; + static const struct ls_pcie_drvdata layerscape_drvdata = { .pf_off = 0xc0000, .pm_support = true, @@ -275,7 +363,7 @@ static const struct of_device_id ls_pcie_of_match[] = { { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, - { .compatible = "fsl,ls1043a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, @@ -314,6 +402,7 @@ static int ls_pcie_probe(struct platform_device *pdev) pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; if (!ls_pcie_is_bridge(pcie)) return -ENODEV;