From patchwork Mon Oct 16 06:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 153208 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3269319vqb; Sun, 15 Oct 2023 23:26:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHSPIJTIYX8+htOnpyT9ecGAOBuOHweqWpkR969qPQ1UrzF8u/GJ/U0ORRdMJiRrFYHOVmB X-Received: by 2002:a05:622a:14cc:b0:41b:774b:b1a2 with SMTP id u12-20020a05622a14cc00b0041b774bb1a2mr200075qtx.22.1697437601341; Sun, 15 Oct 2023 23:26:41 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697437601; cv=pass; d=google.com; s=arc-20160816; b=C/b736osQtZNYs9ImqxdHFeCRqZR1tzZi3TE0Vjf4rY5WI3ktdofHD5JGqW0tA69Fp 6II3AWbH26TSuEPnwnrkEwSkSlmzmC6LOxvLOvPZnbCzGKQIg4N3Nc9cOM0M4xkYeYm2 qo+Q2lBr1etiAo1hizLNOc6v6HTMECtaGN/0Gah3w6fM8p45RhTgV/gCfckGbUHzjxs6 9GIOUI3zmkWhmYHcUKqoB2jAki9r14dPtJzlfPpim69rGraGbEnhUlosYxPxIjjEuRfE luKsMubNw1j8kzmNiXsj0fbLg6/W2knmVUCJ85eTsPAlvGU8m/QvrJDwpFXoSp853x+X /tdw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=4fkZbvZAqdIP9xJhE3F6ItuoitrfBBkW5mlilsqL8JE=; fh=M9HM6ASxJ13myMyxe6+D5Y8nbneXlY5qT/Udj6S6pN8=; b=j/lnpFDVB5phRkHmVQWoqbPzAQw7JKE8Xi5JYxM1Dl3kmmis90Mk8mTK4nGq/DEhCr tXeg15/D8vjyaAkrEqKtlI8gGYS7VFnPtJ/1N7AASF7b0cD3fiRiVwL+Mb2zCn2C9Yxr meLR0QHNWkMYg4DOkcmvCk2JoYVefZ7OPOaCqwdrxpLZNRbSt6Y/hmPi6Hx122dA60mb rkwnXFV38liHsm+PuFsepUdjX3sdxw8Y+/Y4/hdzH6GgHzSjURk1aSyyXMTprbKbfug7 seesS/st6T34diAlOjbtjZgCpG8wtjWAmh4T1RE51Q498mOh0XskwUpRayES90geCJya QK+w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dXyVkpqU; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id d2-20020a05622a15c200b00418194af9ecsi4886307qty.51.2023.10.15.23.26.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Oct 2023 23:26:41 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dXyVkpqU; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1EB463858433 for ; Mon, 16 Oct 2023 06:26:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 2BF363858C39 for ; Mon, 16 Oct 2023 06:25:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2BF363858C39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 2BF363858C39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.88 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437551; cv=none; b=XV2HcS2d+fH9lS8vyNh3fc6XHSGtKjM9MR18vBdfWCw+UfsUc5FYUmuRc2DcBsG1nB8+kGAt9rllzKRuPs2NuWCUkAsT57ViIuI/2z30pjGQyBRWzMKxmUs8ZvtfvxfWt6FslYaY0MUyenK8RRv0ez/syPfj2hOVteRZG7FE9dQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437551; c=relaxed/simple; bh=HvBCZ0O1qBeELHf3bEQuYyblRagW81Ray/Z/lSPErF4=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=wkGatrWlz7xEK1JmcbRD1QRLOO8il9971g0dpyM0CFMFW/5C2JYfQd3/d/kkwk227ZaHoUCqhlLg1wqhEv7ofwV70Sg0fgPGdjB1RC4M9QIC4Kk5aYpyiNOMpWg5izpO/pj8GsxD10MOonhwdDtX9j8yPkihxN20WmDILdZpQ8Y= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697437549; x=1728973549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HvBCZ0O1qBeELHf3bEQuYyblRagW81Ray/Z/lSPErF4=; b=dXyVkpqUteUKVzG+9EB6Bm/HgFg1q3Up9M56wQM08Mx/cW3KHKdMVS5t Gh2v0RmoBn1ScTE3fa7JXgwnLGEHq7XxlMuGYq9WUpyY8o8N0JrHJ9hIU beBFcjkslL689wq8oFKA0Tjt/pxyAW1YSA2Qdon5wxhW6NdHSIlmfAwmM bwUNdFdkjbOmE1HXoDXPX67Qfz42vi4AphRaFofqYIcWpWN+modAE/SzP ZV5JE6I1HiSY93ce7b8VU4JXkZAheyy5s8bLMdAFpJMFx8UVsbqARt29c B3cYUsRLWGxPyyXLSLD9ciM2sFGV3aXPk1St7t6BjNgEdEjJOlWv1aT9v g==; X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="416523706" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="416523706" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2023 23:25:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="705483457" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="705483457" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 15 Oct 2023 23:25:44 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 164861005682; Mon, 16 Oct 2023 14:25:43 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 1/3] Initial Clear Water Forest Support Date: Mon, 16 Oct 2023 14:23:38 +0800 Message-Id: <20231016062340.2639697-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231016062340.2639697-1-haochen.jiang@intel.com> References: <20231016062340.2639697-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779892330274949922 X-GMAIL-MSGID: 1779892330274949922 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_intel_cpu): Handle Clear Water Forest. * common/config/i386/i386-common.cc (processor_name): Add Clear Water Forest. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_CLEARWATERFOREST. * config.gcc: Add -march=clearwaterforest. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle clearwaterforest. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_CLEARWATERFOREST): New. (m_CORE_ATOM): Add clearwaterforest. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march. --- gcc/common/config/i386/cpuinfo.h | 6 ++++++ gcc/common/config/i386/i386-common.cc | 3 +++ gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.cc | 5 ++++- gcc/config/i386/i386-c.cc | 7 +++++++ gcc/config/i386/i386-options.cc | 4 +++- gcc/config/i386/i386.h | 3 +++ gcc/doc/extend.texi | 3 +++ gcc/doc/invoke.texi | 9 +++++++++ gcc/testsuite/g++.target/i386/mv16.C | 6 ++++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + 12 files changed, 47 insertions(+), 3 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 0f86b44730b..57394a18c67 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -608,6 +608,12 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_type = INTEL_COREI7; cpu_model->__cpu_subtype = INTEL_COREI7_ARROWLAKE_S; break; + case 0xdd: + /* Clear Water Forest. */ + cpu = "clearwaterforest"; + CHECK___builtin_cpu_is ("clearwaterforest"); + cpu_model->__cpu_type = INTEL_CLEARWATERFOREST; + break; case 0x17: case 0x1d: /* Penryn. */ diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 13e423deceb..903034d2afd 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -2077,6 +2077,7 @@ const char *const processor_names[] = "tremont", "sierraforest", "grandridge", + "clearwaterforest", "knl", "knm", "skylake", @@ -2246,6 +2247,8 @@ const pta processor_alias_table[] = M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2}, {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE, M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2}, + {"clearwaterforest", PROCESSOR_CLEARWATERFOREST, CPU_HASWELL, + PTA_CLEARWATERFOREST, M_CPU_TYPE (INTEL_CLEARWATERFOREST), P_PROC_AVX2}, {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL, M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F}, {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 47e9dcfb8f7..44db6a07076 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -62,6 +62,7 @@ enum processor_types ZHAOXIN_FAM7H, INTEL_SIERRAFOREST, INTEL_GRANDRIDGE, + INTEL_CLEARWATERFOREST, CPU_TYPE_MAX, BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX }; diff --git a/gcc/config.gcc b/gcc/config.gcc index fa192637a52..2d045d6d00f 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -708,7 +708,7 @@ skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \ sierraforest graniterapids graniterapids-d grandridge arrowlake arrowlake-s \ -native" +clearwaterforest native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 08d0aed6183..a21f2dfe82f 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -591,8 +591,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* This is unknown family 0x6 CPU. */ if (has_feature (FEATURE_AVX)) { + /* Assume Clear Water Forest. */ + if (has_feature (FEATURE_USER_MSR)) + cpu = "clearwaterforest"; /* Assume Arrow Lake S. */ - if (has_feature (FEATURE_SM3)) + else if (has_feature (FEATURE_SM3)) cpu = "arrowlake-s"; /* Assume Grand Ridge. */ else if (has_feature (FEATURE_RAOINT)) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 042ad8b9d9c..7ac95a923be 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -210,6 +210,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__grandridge"); def_or_undef (parse_in, "__grandridge__"); break; + case PROCESSOR_CLEARWATERFOREST: + def_or_undef (parse_in, "__clearwaterforest"); + def_or_undef (parse_in, "__clearwaterforest__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__knl"); def_or_undef (parse_in, "__knl__"); @@ -415,6 +419,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_GRANDRIDGE: def_or_undef (parse_in, "__tune_grandridge__"); break; + case PROCESSOR_CLEARWATERFOREST: + def_or_undef (parse_in, "__tune_clearwaterforest__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__tune_knl__"); break; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 818954d6dbc..1d28258b4fa 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -141,7 +141,8 @@ along with GCC; see the file COPYING3. If not see #define m_GRANDRIDGE (HOST_WIDE_INT_1U< X-Patchwork-Id: 153207 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3269236vqb; Sun, 15 Oct 2023 23:26:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IESPqwCmdybLsOKVfZ0Fx/yFB0FKs0yFxgJh8JZotqHiju3KboTZ7L7zjjW/YhBzmyW1T4F X-Received: by 2002:a05:622a:13c6:b0:418:cd5:ac9d with SMTP id p6-20020a05622a13c600b004180cd5ac9dmr36046341qtk.64.1697437585359; Sun, 15 Oct 2023 23:26:25 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697437585; cv=pass; d=google.com; s=arc-20160816; b=mrfNIynHT8K0tJcfOP7IC6C93+PAI5xAzxUDnFNBLJrCBqaNoGS5JBqSumX+hPf+uc NB7sPjodM8Mo0ooPIH8cRi4BfHtRn+Qs7fD/9LomIb/f7vPsZASjL/e3Sp1aqVFFycbj 5umFAr8oFqu9e5hN5tS+t6Oyh6p/JZu/U9KOgaN0nFLmpBz59qdFDcMqnSgoZ6hPfQOd Tq5oKnuo4R6bix0eJTcouc3WhFKonpsDxyi4tJzlh8wbRbT/4d5KQnU3/ZKFlkvQSYjI h6tGd3AgoVa2/1t9IGcaubNYKc/IQO2GeHDzUOP5OC0HF/tv7xsfP8jwmQlQQu1Qfqmm wsCw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=5iobD9ZKZrLUJcStrojivnihvFPZL/1A5NejUukfKKk=; fh=M9HM6ASxJ13myMyxe6+D5Y8nbneXlY5qT/Udj6S6pN8=; b=ZCn9NoFBisGWpu4irFw5LCUw8NeNgNnqGPRpIRqAzmhRNFT3CRP65K4raRDimUjZEr BNFiG8CunbseCIKDzxHj/5fo1jZIcTnNcEGM7aoTlU+k5wyAapAiPeX5SABINneuzEEK WoDGsupANy1DtjGt3MrXRvPTTGzLO4Js7TBBv1FDSwWwcAEhY9moGbtM8AZCS2WBoaoF +CqzBnEJMt9uxFnJbcKjRzeL4Spo3oZq+Jt3ghWOZ09CsB1aq1Gb0B8GesSlOKYElPRV 8KoYclMS3xBu1s2DkfNjqrB8eJ7VhRym9O0/42COWoMW8cRnUaCBpO8MHALXAve5JEOB gSdQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LaGu4phk; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id a2-20020a05622a02c200b004195a719fdcsi4911837qtx.563.2023.10.15.23.26.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Oct 2023 23:26:25 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LaGu4phk; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2555A385702F for ; Mon, 16 Oct 2023 06:26:25 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id ABB67385800C for ; Mon, 16 Oct 2023 06:25:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org ABB67385800C Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org ABB67385800C Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.88 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437554; cv=none; b=CbvLsXwRDsR4G/LVxmxZz86+pNSa2YQyycd2iNtqD4kUfljfhyCA6KF0fJsMbjgN8Q2ewWSPwZ69IGO4zNnQbtqQOkdr8pJNtp/oUH6lOasR1Iy0Raarw7Xsnf6ILsAGqw6JigS5y5+7i1QIdR7AlBNR9o1/NfEMhmYMqMiZvOc= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437554; c=relaxed/simple; bh=s/1iGbbKXlV14oRQuS6nhfdXNY3XiEDJURFvQBydHeM=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=bsLkSwwl9WRvOm3OziF2Usj+3F9zBPsupzRv43O6EvhpcebGz9ViecITaPkTSefsHY5xmULz1BbPUlFk47V66HBVOuhkq8SAKihYzC7kkenQ4vgxe6e2miZWOLxFBbNiuymDuon1sSsmkjkTvxZiRX1HWdlcNQFkZwxwduTB/2k= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697437551; x=1728973551; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=s/1iGbbKXlV14oRQuS6nhfdXNY3XiEDJURFvQBydHeM=; b=LaGu4phkm02mOFxY/ORTiSw3rL1A4UUlEdznE2h4VGsZnO4/BzPNpURt 807K12cxduKDnLSqZ8KWmiJfBdI2j6/Kj/sgPtsO3muTEV2jK7/5K52/0 luWBkgPm7uz7tpULo+qSf5y0JTSW7SQQdFUFc20ON6SB0lP6chJusniXx ihhBI9XVRzj7lmNu5oJVlKxVe8nO7v/WWQNtoRetogTylak3U4AxL8CjJ aC1SQ7jXv1tBJI7hPZtTh87IPYaMAn3q1Hvl4BEYjQ4g+Hyf+7jCNwELj 1Fwe7BrRr7n6mIgKrOc/S7bGRjRFa7YmTZS7+KmC9zPFsnBSfpvYMTrlL A==; X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="416523710" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="416523710" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2023 23:25:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="705483468" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="705483468" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 15 Oct 2023 23:25:44 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1B51B1005684; Mon, 16 Oct 2023 14:25:43 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 2/3] x86: Add m_CORE_HYBRID for hybrid clients tuning Date: Mon, 16 Oct 2023 14:23:39 +0800 Message-Id: <20231016062340.2639697-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231016062340.2639697-1-haochen.jiang@intel.com> References: <20231016062340.2639697-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779892313256810169 X-GMAIL-MSGID: 1779892313256810169 gcc/Changelog: * config/i386/i386-options.cc (m_CORE_HYBRID): New. * config/i386/x86-tune.def: Replace hybrid client tune to m_CORE_HYBRID. --- gcc/config/i386/i386-options.cc | 1 + gcc/config/i386/x86-tune.def | 113 ++++++++++++++------------------ 2 files changed, 52 insertions(+), 62 deletions(-) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 1d28258b4fa..952cfe54da0 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -143,6 +143,7 @@ along with GCC; see the file COPYING3. If not see #define m_ARROWLAKE_S (HOST_WIDE_INT_1U<> (W-1) ^ x) - @@ -386,8 +381,7 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop", ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT - | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM - | m_GENERIC)) + | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) @@ -396,8 +390,8 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE - | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC) + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID + | m_CORE_ATOM | m_GENERIC) /*****************************************************************************/ /* SSE instruction selection tuning */ @@ -412,17 +406,16 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM - | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_AMDFAM10 | m_BDVER - | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) + | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID + | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI + | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM - | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S| m_CORE_ATOM | m_BDVER | m_ZNVER - | m_LUJIAZUI | m_GENERIC) + | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID + | m_CORE_ATOM | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single precision 128bit instructions instead of double where possible. */ @@ -431,15 +424,14 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */ DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores", - m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC) + m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_CORE_HYBRID + | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to xorps/xorpd and other variants. */ DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S - | m_CORE_ATOM | m_GENERIC) + | m_LUJIAZUI | m_TREMONT | m_CORE_HYBRID | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer to SSE registers. If disabled, the moves will be done by storing @@ -485,14 +477,14 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", - m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_INTEL) + m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_CORE_HYBRID + | m_CORE_ATOM | m_INTEL) /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_CORE_HYBRID + | m_CORE_ATOM | m_GENERIC | m_GDS)) /* X86_TUNE_USE_SCATTER_2PARTS: Use scater instructions for vectors with 2 elements. */ @@ -502,8 +494,8 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_2PARTS, "use_scatter_2parts", /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_ALDERLAKE - | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ZNVER4 | m_CORE_HYBRID + | m_CORE_ATOM | m_GENERIC | m_GDS)) /* X86_TUNE_USE_SCATTER_4PARTS: Use scater instructions for vectors with 4 elements. */ @@ -513,8 +505,8 @@ DEF_TUNE (X86_TUNE_USE_SCATTER_4PARTS, "use_scatter_4parts", /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_8PARTS, "use_gather_8parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_ALDERLAKE | m_ARROWLAKE - | m_ARROWLAKE_S | m_CORE_ATOM | m_GENERIC | m_GDS)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER4 | m_CORE_HYBRID | m_CORE_ATOM + | m_GENERIC | m_GDS)) /* X86_TUNE_USE_SCATTER: Use scater instructions for vectors with 8 or more elements. */ @@ -528,8 +520,7 @@ DEF_TUNE (X86_TUNE_AVOID_128FMA_CHAINS, "avoid_fma_chains", m_ZNVER1 | m_ZNVER2 /* X86_TUNE_AVOID_256FMA_CHAINS: Avoid creating loops with tight 256bit or smaller FMA chain. */ DEF_TUNE (X86_TUNE_AVOID_256FMA_CHAINS, "avoid_fma256_chains", m_ZNVER2 | m_ZNVER3 - | m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_SAPPHIRERAPIDS - | m_CORE_ATOM) + | m_CORE_HYBRID | m_SAPPHIRERAPIDS | m_CORE_ATOM) /* X86_TUNE_AVOID_512FMA_CHAINS: Avoid creating loops with tight 512bit or smaller FMA chain. */ @@ -573,14 +564,12 @@ DEF_TUNE (X86_TUNE_AVX512_SPLIT_REGS, "avx512_split_regs", m_ZNVER4) /* X86_TUNE_AVX256_MOVE_BY_PIECES: Optimize move_by_pieces with 256-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX256_MOVE_BY_PIECES, "avx256_move_by_pieces", - m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_AVX2 | m_ZNVER1 - | m_ZNVER2 | m_ZNVER3) + m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3) /* X86_TUNE_AVX256_STORE_BY_PIECES: Optimize store_by_pieces with 256-bit AVX instructions. */ DEF_TUNE (X86_TUNE_AVX256_STORE_BY_PIECES, "avx256_store_by_pieces", - m_ALDERLAKE | m_ARROWLAKE | m_ARROWLAKE_S | m_CORE_AVX2 | m_ZNVER1 - | m_ZNVER2 | m_ZNVER3) + m_CORE_HYBRID | m_CORE_AVX2 | m_ZNVER1 | m_ZNVER2 | m_ZNVER3) /* X86_TUNE_AVX512_MOVE_BY_PIECES: Optimize move_by_pieces with 512-bit AVX instructions. */ From patchwork Mon Oct 16 06:23:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Jiang, Haochen" X-Patchwork-Id: 153209 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3269455vqb; Sun, 15 Oct 2023 23:27:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGSMJ1d/xcDMljVYNpiwNRokcPKAE2qR2l+3TwXoL1FsSKS37GSz3/q2iNssGnu2gy8ER3J X-Received: by 2002:a05:620a:2416:b0:775:9f94:16f1 with SMTP id d22-20020a05620a241600b007759f9416f1mr8923750qkn.22.1697437631226; Sun, 15 Oct 2023 23:27:11 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697437631; cv=pass; d=google.com; s=arc-20160816; b=lhPNSvc/rJgqcGLCl7h+gdkTZj9drKBvY2mLWlrILNs7B7wzsexL1SmHJw57CRJ8lq 0QdCGErpjOt5tvX+qHC8MhjsdM6mEqfCPYeV/vgw4QuBhFtRgBZg7gcIK27Qv1yvjfly FwGHUNue4LGZsLM+u3Sg4hh0i2+PaYjiFm5WRX5P0+Mm+eCddJ9eJljjwQwg5jYIgw+i YjjzJfotSnEf/o5HexlmqEDSt9pCfyHVpTqvBudzhyCzZDBZchZGhgPi3HQYRY0iiIKD 6XdQBLiTiv/Y/6dJEAvWrnhYUwdgsmycrtUtIcP50bx3kaCwzmsL8eMilytJJuZBgiv6 UOUg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature:arc-filter:dmarc-filter:delivered-to; bh=REAgk8rwBG2YlLbdSO2TDcuNAqlVteJnyFmTjcAdvso=; fh=M9HM6ASxJ13myMyxe6+D5Y8nbneXlY5qT/Udj6S6pN8=; b=0m3IBMjjIrHj1eyByputTr9dtvuw4acZ9oDBvAmhxiR2LK54o0oAQIw/LmfFRf4WYW qU3gRUj1vwWsl2EWRqhltsKKAf0a2TKyIPRzQ5tWkDEMKSSxF8WTS/s9wbjqzN7q31Oa KVKwehKieBTgROqhSy0PmfO6oZkDD4naAhSFYZThqCZl2sDo9xfci2JkZ1pGetsaaej/ f9B4eOwFjeJorh3xd4Zc8Jrzug318Ce5loY4vaAaQ5fCydDtyT5vM+XltmQ2rz1IYME2 zubYbwELXxR55F1KWw7UmF1UoHq5fD1SlMZh/JwxTY1NmU3TZxarsbXz/wvQR2Wuf+6b Nu0Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bZn+bZCs; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id bl9-20020a05620a1a8900b007740257b80esi4945714qkb.311.2023.10.15.23.27.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 15 Oct 2023 23:27:11 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bZn+bZCs; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id F3A623857B9B for ; Mon, 16 Oct 2023 06:27:10 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 4B6313858C3A for ; Mon, 16 Oct 2023 06:25:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4B6313858C3A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4B6313858C3A Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.88 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437551; cv=none; b=kooTn5gol2a54n2erWl56wIaCAcJgAtYSlvabR0mGNaKlgh17J+DZKChNh6etrKq+rKVVKE+TzicZVUOf7riLrlACBi62+hJI0+PMMsV8J0aJTXNkMQJblZCAAqMvc2YNiHvV4rBMY5rOad72xjYaWuTbivOGK30T+oCmsDEgik= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697437551; c=relaxed/simple; bh=XZphhNIRZ2XDseahhiiRNYHS+1aHa93DD2rgZ1kzTpE=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=W89NomGhOav28ycb5O+01+pOAepblkHBrZKNCyAd48Z5g4FZfkNvtrjlMSwYcoj/m/VLGRN8ViubTxs2KNfzJ8ybFPNjISc9+5ab3bZofeOjmhxxBqwhGCHjQ49Zw4Gsl7QvBWxHDbbIWMLY9HgaPkPuX2vAl+yuIiW9QnbSVJU= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697437549; x=1728973549; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XZphhNIRZ2XDseahhiiRNYHS+1aHa93DD2rgZ1kzTpE=; b=bZn+bZCs+eSPfsg5NuAKTvogIMORZR0YwrxlxFQED+XCvJR7A7pjMsS/ I3xqdvG51kniefcS69bJkFXUzDt3B6n59Y0G3IBJRKII0DlHllrJ/OOTc zdzl7tRffJ72eKneDZaeJxp7rbOzsC5YPlPCQ/LzWY2ZYlAh3IQIahC3z IueRogxzAYsSujdb304FKC+C3H2H71Hx4JdE1/3jCwxOqnUEaCuh9vdIE Nqn1AFql4qM/uz8FanDIKP2vjfIGSlQ7H4vtjbfp67wWY31FKduubd27G 6JAvcxVf57Xmv3+wh3m9C5Kpr8JTBoko/OLUuX96yYWho5yVAqd/c4fIi g==; X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="416523708" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="416523708" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Oct 2023 23:25:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10863"; a="705483466" X-IronPort-AV: E=Sophos;i="6.03,228,1694761200"; d="scan'208";a="705483466" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 15 Oct 2023 23:25:44 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 1EC651005686; Mon, 16 Oct 2023 14:25:43 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH 3/3] Initial Panther Lake Support Date: Mon, 16 Oct 2023 14:23:40 +0800 Message-Id: <20231016062340.2639697-4-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231016062340.2639697-1-haochen.jiang@intel.com> References: <20231016062340.2639697-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779892361863758073 X-GMAIL-MSGID: 1779892361863758073 gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_name): Add Panther Lake. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h (enum processor_types): Add INTEL_PANTHERLAKE. * config.gcc: Add -march=pantherlake. * config/i386/driver-i386.cc (host_detect_local_cpu): Refactor the if clause. Handle pantherlake. * config/i386/i386-c.cc (ix86_target_macros_internal): Handle pantherlake. * config/i386/i386-options.cc (processor_cost_table): Ditto. (m_PANTHERLAKE): New. (m_CORE_HYBRID): Add pantherlake. * config/i386/i386.h (enum processor_type): Ditto. * doc/extend.texi: Ditto. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/mv16.C: Ditto. * gcc.target/i386/funcspec-56.inc: Handle new march. --- gcc/common/config/i386/cpuinfo.h | 8 ++ gcc/common/config/i386/i386-common.cc | 3 + gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.cc | 92 ++++++++++--------- gcc/config/i386/i386-c.cc | 7 ++ gcc/config/i386/i386-options.cc | 5 +- gcc/config/i386/i386.h | 2 + gcc/doc/extend.texi | 3 + gcc/doc/invoke.texi | 9 ++ gcc/testsuite/g++.target/i386/mv16.C | 6 ++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + 12 files changed, 94 insertions(+), 45 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 57394a18c67..f7060ed7254 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -614,6 +614,14 @@ get_intel_cpu (struct __processor_model *cpu_model, CHECK___builtin_cpu_is ("clearwaterforest"); cpu_model->__cpu_type = INTEL_CLEARWATERFOREST; break; + case 0xcc: + /* Panther Lake. */ + cpu = "pantherlake"; + CHECK___builtin_cpu_is ("corei7"); + CHECK___builtin_cpu_is ("pantherlake"); + cpu_model->__cpu_type = INTEL_COREI7; + cpu_model->__cpu_subtype = INTEL_COREI7_PANTHERLAKE; + break; case 0x17: case 0x1d: /* Penryn. */ diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 903034d2afd..79b1b35ad6c 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -2095,6 +2095,7 @@ const char *const processor_names[] = "graniterapids-d", "arrowlake", "arrowlake-s", + "pantherlake", "intel", "lujiazui", "geode", @@ -2227,6 +2228,8 @@ const pta processor_alias_table[] = M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2}, {"lunarlake", PROCESSOR_ARROWLAKE_S, CPU_HASWELL, PTA_ARROWLAKE_S, M_CPU_SUBTYPE (INTEL_COREI7_ARROWLAKE_S), P_PROC_AVX2}, + {"pantherlake", PROCESSOR_PANTHERLAKE, CPU_HASWELL, PTA_PANTHERLAKE, + M_CPU_SUBTYPE (INTEL_COREI7_PANTHERLAKE), P_PROC_AVX2}, {"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3}, {"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 44db6a07076..533b7481c16 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -102,6 +102,7 @@ enum processor_subtypes INTEL_COREI7_GRANITERAPIDS_D, INTEL_COREI7_ARROWLAKE, INTEL_COREI7_ARROWLAKE_S, + INTEL_COREI7_PANTHERLAKE, CPU_SUBTYPE_MAX }; diff --git a/gcc/config.gcc b/gcc/config.gcc index 2d045d6d00f..37311fcd075 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -708,7 +708,7 @@ skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \ sierraforest graniterapids graniterapids-d grandridge arrowlake arrowlake-s \ -clearwaterforest native" +clearwaterforest pantherlake native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index a21f2dfe82f..2b4d6afe8db 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -589,26 +589,14 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (arch) { /* This is unknown family 0x6 CPU. */ - if (has_feature (FEATURE_AVX)) + if (has_feature (FEATURE_AVX512F)) { - /* Assume Clear Water Forest. */ - if (has_feature (FEATURE_USER_MSR)) - cpu = "clearwaterforest"; - /* Assume Arrow Lake S. */ - else if (has_feature (FEATURE_SM3)) - cpu = "arrowlake-s"; - /* Assume Grand Ridge. */ - else if (has_feature (FEATURE_RAOINT)) - cpu = "grandridge"; /* Assume Granite Rapids D. */ - else if (has_feature (FEATURE_AMX_COMPLEX)) + if (has_feature (FEATURE_AMX_COMPLEX)) cpu = "graniterapids-d"; /* Assume Granite Rapids. */ else if (has_feature (FEATURE_AMX_FP16)) cpu = "graniterapids"; - /* Assume Sierra Forest. */ - else if (has_feature (FEATURE_AVXVNNIINT8)) - cpu = "sierraforest"; /* Assume Tiger Lake */ else if (has_feature (FEATURE_AVX512VP2INTERSECT)) cpu = "tigerlake"; @@ -621,36 +609,54 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* Assume Ice Lake Server. */ else if (has_feature (FEATURE_WBNOINVD)) cpu = "icelake-server"; - /* Assume Ice Lake. */ - else if (has_feature (FEATURE_AVX512BITALG)) - cpu = "icelake-client"; - /* Assume Cannon Lake. */ - else if (has_feature (FEATURE_AVX512VBMI)) - cpu = "cannonlake"; - /* Assume Knights Mill. */ - else if (has_feature (FEATURE_AVX5124VNNIW)) - cpu = "knm"; - /* Assume Knights Landing. */ - else if (has_feature (FEATURE_AVX512ER)) - cpu = "knl"; - /* Assume Skylake with AVX-512. */ - else if (has_feature (FEATURE_AVX512F)) - cpu = "skylake-avx512"; - /* Assume Alder Lake */ - else if (has_feature (FEATURE_SERIALIZE)) + /* Assume Ice Lake. */ + else if (has_feature (FEATURE_AVX512BITALG)) + cpu = "icelake-client"; + /* Assume Cannon Lake. */ + else if (has_feature (FEATURE_AVX512VBMI)) + cpu = "cannonlake"; + /* Assume Knights Mill. */ + else if (has_feature (FEATURE_AVX5124VNNIW)) + cpu = "knm"; + /* Assume Knights Landing. */ + else if (has_feature (FEATURE_AVX512ER)) + cpu = "knl"; + /* Assume Skylake with AVX-512. */ + else + cpu = "skylake-avx512"; + } + else if (has_feature (FEATURE_AVX)) + { + /* Assume Panther Lake. */ + if (has_feature (FEATURE_PREFETCHI)) + cpu = "pantherlake"; + /* Assume Clear Water Forest. */ + if (has_feature (FEATURE_USER_MSR)) + cpu = "clearwaterforest"; + /* Assume Arrow Lake S. */ + else if (has_feature (FEATURE_SM3)) + cpu = "arrowlake-s"; + /* Assume Grand Ridge. */ + else if (has_feature (FEATURE_RAOINT)) + cpu = "grandridge"; + /* Assume Sierra Forest. */ + else if (has_feature (FEATURE_AVXVNNIINT8)) + cpu = "sierraforest"; + /* Assume Alder Lake. */ + else if (has_feature (FEATURE_SERIALIZE)) cpu = "alderlake"; - /* Assume Skylake. */ - else if (has_feature (FEATURE_CLFLUSHOPT)) - cpu = "skylake"; - /* Assume Broadwell. */ - else if (has_feature (FEATURE_ADX)) - cpu = "broadwell"; - else if (has_feature (FEATURE_AVX2)) - /* Assume Haswell. */ - cpu = "haswell"; - else - /* Assume Sandy Bridge. */ - cpu = "sandybridge"; + /* Assume Skylake. */ + else if (has_feature (FEATURE_CLFLUSHOPT)) + cpu = "skylake"; + /* Assume Broadwell. */ + else if (has_feature (FEATURE_ADX)) + cpu = "broadwell"; + /* Assume Haswell. */ + else if (has_feature (FEATURE_AVX2)) + cpu = "haswell"; + /* Assume Sandy Bridge. */ + else + cpu = "sandybridge"; } else if (has_feature (FEATURE_SSE4_2)) { diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index 7ac95a923be..ebe6a63ed41 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -282,6 +282,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__arrowlake_s"); def_or_undef (parse_in, "__arrowlake_s__"); break; + case PROCESSOR_PANTHERLAKE: + def_or_undef (parse_in, "__pantherlake"); + def_or_undef (parse_in, "__pantherlake__"); + break; /* use PROCESSOR_max to not set/unset the arch macro. */ case PROCESSOR_max: @@ -476,6 +480,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_ARROWLAKE_S: def_or_undef (parse_in, "__tune_arrowlake_s__"); break; + case PROCESSOR_PANTHERLAKE: + def_or_undef (parse_in, "__tune_pantherlake__"); + break; case PROCESSOR_INTEL: case PROCESSOR_GENERIC: break; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 952cfe54da0..3a03de5ceca 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -142,8 +142,10 @@ along with GCC; see the file COPYING3. If not see #define m_ARROWLAKE (HOST_WIDE_INT_1U<