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Sun, 15 Oct 2023 22:11:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779887631534257587 X-GMAIL-MSGID: 1779887631534257587 The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige --- changes in v5: - None changes in v4: - None changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else From patchwork Mon Oct 16 05:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 153177 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3244822vqb; Sun, 15 Oct 2023 22:12:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFuUhgWCZ/wYo61YeWvxoavH7X+c81EOBaKC2ANmwvoKf/5egES/ivz62qRhzdZvmwmQ7CO X-Received: by 2002:a17:902:e5d2:b0:1c4:1cd3:8062 with SMTP id u18-20020a170902e5d200b001c41cd38062mr37665143plf.2.1697433128576; Sun, 15 Oct 2023 22:12:08 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697433128; cv=pass; d=google.com; s=arc-20160816; b=beG+dAzfZP5SEUqFuS7yhmccxZ14+9dmDJs3QCgb/5fwetORAa5AgNUukw2uVIPtg2 pcndMCOfARcUcysLSlWEvWVMhyMYXvVHMyNeW40AHLfBb7/pEbL2k0eaFCUnNADbmUNP srGQ7KKP/NpcmTWVHAsEtvCdRqLblLYts16r44sYqbF63Ua3ca2EE1pqxmIuJXgMM1GV O/VQNOOxXhFdI6IQopexnPT4tJiJiKo7g/xNoECyoYQBJzIWJbGxc2EOU/ZWG9cbbe9V przN1VfPB7hxusw/m01CqMyRhgqZcAuhpalvcIJAhxCZw3GNIiWHPM+m2S9Yev1dLktm QBGw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aljHyMWt8R/QLn5d6xJ+f8RBv6t6/Cj1hmwBAKY8Yjw=; fh=BOMH9MWeDZ9ZGK5xs4800vvHgkhBV5JbZuS3kNbCbLc=; b=c+BZS7mfzBN1RgGeoYCWt7QwKSfu7N9xtLUccf/tNc5zZlKBw2dY0myvlC5t3heXDf p6dTz8KCcYAWd5Qzw0CUN+jChHU2wZ4Ph1MziiTq91jg8lzMZezRgH/lwo0c1h+TnX+U 0/iZXAZLiYNbQFEo8CigZgG6C8qbd7IFD/DoBCijU1SzdcwpP+irlx/jqBaNmZ4cKuwD gYt70eagDRWaoqluQpNpgztQF6GIlKaP3yj6fVNOH5bZeMFTn6UM6IF11SNTDQyhCV1X dp9W8gxF5wq8OxPbd8QRd6yqP99/ibODYY3piquPf8eePA934P1l/ZFNhNonZdcFBQEs gstQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=ILF8PN4y; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from groat.vger.email (groat.vger.email. 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Sun, 15 Oct 2023 22:12:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779887640532930302 X-GMAIL-MSGID: 1779887640532930302 Update ECAM size in example to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige Acked-by: Rob Herring --- changes in v5: None changes in v4: None changes in v3: Remove period at end of subject line changes in v2: None. changes in v1: None. --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; From patchwork Mon Oct 16 05:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 153178 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3244913vqb; Sun, 15 Oct 2023 22:12:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9c3XXMpj4edAiGT1n2JfQrv6YwfX25J1EoZpcewSL8VRR7PY8Lu60UbIk4MGW+sR4rVkJ X-Received: by 2002:a17:903:2306:b0:1bb:ac37:384b with SMTP id d6-20020a170903230600b001bbac37384bmr37514897plh.6.1697433148566; Sun, 15 Oct 2023 22:12:28 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697433148; cv=pass; d=google.com; s=arc-20160816; b=CGcqBMl2W5WMhQ73qPlF8RotWDotA9D37q0Ou9iNNKWmMfEhdTOP6DsCZspIfKiz0C rxzgEn31HFU4QyDXAhPV3eC3xYmKHYcqPs+mN9c5OfZ/xMB03CY2+w2UAxdJ0Pv0/XVh pSRhRtmLqg6XYLt23zPi8IhvfOuVPyD+BqDQngVO3+h+HgBw0cNbTv33vHvAxD31dwaj d4+ZQmqgk97r7yzsT2tzoucco/kl81X2t2YPFnJwn7uAP3JSHBMrEEW1vUUDnW9FMM44 K8XH9rT4El9fpU10yL33okWF1t7Uc2RvEkjP8ix+N1B1bMQKBEALYAhigPDm8CORhgnc dVMg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/ESYLK1Re4VerwS7kWjWSjaIYrADQbJMwrXP7iIWn9w=; fh=BOMH9MWeDZ9ZGK5xs4800vvHgkhBV5JbZuS3kNbCbLc=; b=ia/hiuW8hFHhEZJQKfsk50cQ8vPnZAieCi+ekP/pu96Q17jC9tsl15yFCUbQ61LQhL UqREyaKo9tkB/Q5OSiT0DkGdbPqIinjp+It92a00HZ1vzNjawRCkaMFS+hHubmE27gW9 j0YvHYVIXZNqardKqxwqvwruNTf0wkvK+xWLiQ5jm3al0Qn0pKIhnWOOAupgieNtBkhC lqsZ7ALtBFb4pt762a1yPJOiFEFVMTIv5U7dHLKqX5d+4uOw+7pgAUnFr+nA6umQknuN i8JCHhRbewl96wV6daEnQu0p9KkVZNJMWvzsLnhofx3Tsd/Gq8b7A70vmsxjg91FeSnf y7CQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=yFT4xlDV; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from agentk.vger.email (agentk.vger.email. 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Sun, 15 Oct 2023 22:12:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779887661356366910 X-GMAIL-MSGID: 1779887661356366910 Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code Signed-off-by: Thippeswamy Havalige --- changes in v5: Remove period at end of subject line. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Mon Oct 16 05:11:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 153179 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3244934vqb; Sun, 15 Oct 2023 22:12:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHr8y7N+o0rkkGYvKCB67wwb/xdJEexnlJW1PZ+gUhp27En7HCN9NOc0YZ3mglgRAQfgobB X-Received: by 2002:a17:903:2306:b0:1bb:ac37:384b with SMTP id d6-20020a170903230600b001bbac37384bmr37515025plh.6.1697433154301; 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Sun, 15 Oct 2023 22:12:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779887667433999062 X-GMAIL-MSGID: 1779887667433999062 Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)