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([213.149.38.59]) by smtp.googlemail.com with ESMTPSA id rn4-20020a170906d92400b0099bc038eb2bsm12531902ejb.58.2023.10.13.09.40.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 09:40:28 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko , Krzysztof Kozlowski Subject: [PATCH v3 1/2] dt-bindings: clocks: qcom,gcc-ipq8074: allow QMP PCI PHY PIPE clocks Date: Fri, 13 Oct 2023 18:39:33 +0200 Message-ID: <20231013164025.3541606-1-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 13 Oct 2023 09:41:13 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779659238933086831 X-GMAIL-MSGID: 1779659238933086831 QMP PCI PHY PIPE clocks are inputs for the GCC clock controller. In order to describe this in DTS, allow passing them as the inputs to GCC. This has a benefit that it avoids doing a global matching by name. Signed-off-by: Robert Marko Reviewed-by: Krzysztof Kozlowski --- Changes in v3: * Change the commit message to describe the relationship between PIPE clocks and GCC controller Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml index 52e7831a8d6d..2d44ddc45aab 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml @@ -27,11 +27,15 @@ properties: items: - description: board XO clock - description: sleep clock + - description: Gen3 QMP PCIe PHY PIPE clock + - description: Gen2 QMP PCIe PHY PIPE clock clock-names: items: - const: xo - const: sleep_clk + - const: pcie0_pipe + - const: pcie1_pipe required: - compatible From patchwork Fri Oct 13 16:39:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 152675 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp2018507vqb; Fri, 13 Oct 2023 09:41:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaxPfMFrDIZoMMQPR+Inlb4DAzIAc0a1aNbMNvNSJKyzxCEwPfJgqAW5I5Yguj/gnNFT73 X-Received: by 2002:a05:6602:2a44:b0:792:9b50:3c3d with SMTP id k4-20020a0566022a4400b007929b503c3dmr33567393iov.1.1697215283882; Fri, 13 Oct 2023 09:41:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697215283; cv=none; d=google.com; s=arc-20160816; b=TU3eKz710QMavxHF2DV/+zh4h7pHZELYV6hPmP1oNmgi5N6oDgrKqKrKtCxTA4w+Os gjNq4/So/HO7yTL9uBXVu8TejTu5L9K5tt1z468ux9rNeKuqcgHE/3loObmXc04PxmV+ 9ehk5XyzDy4avdGl4VGbNjJWEd7fITHLEVpNwUldpuIO+P/7Dvrrc6be6LaO+k5hj003 dxBroMMcKdzqG3ycy6oEpfCpbZxX0g+7wLgSWy7tomBdXP3raeFhsGmWxpk6TMhnp9VE KubIGeNu/NcpAN8Z/TP34hWoHs5rg64c1KKVLHvffakmbzsA2kvSO0VtaQGl0Y8NMIVh huZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qbunySK2ORAUFspaIT6piWBLusGPbytUTvQrXLVvdqg=; fh=Xi8z58Oc9C8/wCwA8903DuVuYO2mSdgRZzvvpDPgyjQ=; b=CozRrMSuZ2pFnfXTr2CHeVT6j2Fq/gUSiOsfdlo2GApDweW2QB+9xj2I7d5auDacb2 hvqOQFJAleIlM9HCxV+r2mf8LipgLx+I2KIp5tC0komfE1QJ2w3O8tggTgkCvUpg+obe JPubApjucfBLz3Kjen+ktF8xLJFzP/f4jQn3AI7YKhAmHfwaV76Gb3W0Ey+Zr4b1fc2k kLsEQIbO8Zp9xdKFNYpE8b4sPlU+viuvAkDTeoo1xpDD91Xtn5S+rLkho8JLS9HJzv2A PIWL3vecJMMBfx8CdFhjeZ/9r86gfzztjxiJ9yCQdVLpFUOAvAfBGf3RS3bcqSseJ926 EduA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=mPmROBSl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from lipwig.vger.email (lipwig.vger.email. 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([213.149.38.59]) by smtp.googlemail.com with ESMTPSA id rn4-20020a170906d92400b0099bc038eb2bsm12531902ejb.58.2023.10.13.09.40.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 09:40:29 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH v3 2/2] arm64: dts: qcom: ipq8074: pass QMP PCI PHY PIPE clocks to GCC Date: Fri, 13 Oct 2023 18:39:34 +0200 Message-ID: <20231013164025.3541606-2-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231013164025.3541606-1-robimarko@gmail.com> References: <20231013164025.3541606-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 13 Oct 2023 09:41:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779659213336246352 X-GMAIL-MSGID: 1779659213336246352 Pass QMP PCI PHY PIPE clocks to the GCC controller so it does not have to find them by matching globaly by name. If not passed directly, driver maintains backwards compatibility by then falling back to global lookup. Signed-off-by: Robert Marko Reviewed-by: Dmitry Baryshkov --- Changes in v2: * Make clocks and clock-names one-per-line arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 38fcb2675b9a..d8e8a5cded64 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -579,8 +579,14 @@ qpic_pins: qpic-state { gcc: gcc@1800000 { compatible = "qcom,gcc-ipq8074"; reg = <0x01800000 0x80000>; - clocks = <&xo>, <&sleep_clk>; - clock-names = "xo", "sleep_clk"; + clocks = <&xo>, + <&sleep_clk>, + <&pcie_qmp0>, + <&pcie_qmp1>; + clock-names = "xo", + "sleep_clk", + "pcie0_pipe", + "pcie1_pipe"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>;