From patchwork Fri Oct 13 14:59:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 152604 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1952991vqb; Fri, 13 Oct 2023 08:00:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpLv/puHsAsQRkLTLv4wal7vvhSt80UV5KPH6PhE3uugf3uYOsmHfHN4RQ4E/w3m/wsFE5 X-Received: by 2002:a05:6a20:7d85:b0:163:57ba:2ad4 with SMTP id v5-20020a056a207d8500b0016357ba2ad4mr32060215pzj.2.1697209259031; Fri, 13 Oct 2023 08:00:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697209259; cv=none; d=google.com; s=arc-20160816; b=W6JFMV5k2Q0lJjLb7K97AIRqdPm86pztwfw8+bjhKVNk+c5udiQWDMpf13haocm5V9 ugYoJFTyKkl729ZwtQMtyvInGUkoXvMPYjN87Gw84mZlzMs/NVgbk29qkm+mQhtu/Wm9 ND0Wv2n8cNC/2hbzCXsnlKdXNbvRBqDRXctDk6icPCOBPzi2rhUpj633Uhujc2kx7n2q T6vHInqu1x/QPKFFYVT372mhoAyxwt5dt8WCk9bFIcuGedAKgTlDQyBK1WFBaIkngXs8 n/Uqv05vyDB6BUXVuI+yQs1BGEHgcQ3X+EkAnc2dZTn2K/LQNrG+RBquMh5nVAnGWKCO EdVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6XixNF8rcGeT14/86b+PK/uBZUvKiNOeydeAMM5h+qM=; fh=w3rm+CQktc1gAyyspusQtQaPLBzhwgYhEEkERsJRJ8U=; b=RwsmQpmothoUY4OWNvAxFcuwlWihEAGyX+WOE2SBuLpRFpuSKquPeYrR58SchQFR38 mGXGBPmTBqMnj5o7wURCnWSp6N7TSZLytDX8QgGfap/Nz/6E70SKZ0V46yDA2amPHPg1 LEMzhUc3wa1wsqe9JmvTypXPvpPX5DE5hJDH4HCQgkiSbgjD/L5KgstsxhjtC/KFwmG2 MP484kXUschYnxI04ChtD8/ScNG8w2HbFzE1ljrifC9I8INWoP3LH0GWgP3CWQxfamCk XoJBxiTEhnrpaQJJ/DrIgbf4KbfcRRAyLdby5gHYtg17q0MWXx1GSqII4YLdoQyKpLgp 5/xg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lsi3e3LG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from agentk.vger.email (agentk.vger.email. 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([178.197.219.100]) by smtp.gmail.com with ESMTPSA id dh13-20020a0560000a8d00b00327cd5e5ac1sm6428267wrb.1.2023.10.13.07.59.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 07:59:39 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 1/2] pinctrl: qcom: lpass-lpi: split slew rate set to separate function Date: Fri, 13 Oct 2023 16:59:34 +0200 Message-Id: <20231013145935.220945-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> References: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 13 Oct 2023 08:00:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779652895594401709 X-GMAIL-MSGID: 1779652895594401709 Setting slew rate for each pin will grow with upcoming Qualcomm SoCs, so split the code responsible for this into separate function for easier readability and maintenance. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes in v2: 1. None --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 53 +++++++++++++++--------- 1 file changed, 33 insertions(+), 20 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 9651aed048cf..4fb808545f7f 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -186,6 +186,35 @@ static int lpi_config_get(struct pinctrl_dev *pctldev, return 0; } +static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, + const struct lpi_pingroup *g, + unsigned int group, unsigned int slew) +{ + unsigned long sval; + int slew_offset; + + if (slew > LPI_SLEW_RATE_MAX) { + dev_err(pctrl->dev, "invalid slew rate %u for pin: %d\n", + slew, group); + return -EINVAL; + } + + slew_offset = g->slew_offset; + if (slew_offset == LPI_NO_SLEW) + return 0; + + mutex_lock(&pctrl->lock); + + sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); + sval |= slew << slew_offset; + iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + + mutex_unlock(&pctrl->lock); + + return 0; +} + static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned long *configs, unsigned int nconfs) { @@ -193,8 +222,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2; bool value, output_enabled = false; const struct lpi_pingroup *g; - unsigned long sval; - int i, slew_offset; + int i, ret; u32 val; g = &pctrl->data->groups[group]; @@ -226,24 +254,9 @@ static int lpi_config_set(struct pinctrl_dev *pctldev, unsigned int group, strength = arg; break; case PIN_CONFIG_SLEW_RATE: - if (arg > LPI_SLEW_RATE_MAX) { - dev_err(pctldev->dev, "invalid slew rate %u for pin: %d\n", - arg, group); - return -EINVAL; - } - - slew_offset = g->slew_offset; - if (slew_offset == LPI_NO_SLEW) - break; - - mutex_lock(&pctrl->lock); - - sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); - sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); - sval |= arg << slew_offset; - iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); - - mutex_unlock(&pctrl->lock); + ret = lpi_config_set_slew_rate(pctrl, g, group, arg); + if (ret) + return ret; break; default: return -EINVAL; From patchwork Fri Oct 13 14:59:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 152605 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1953211vqb; Fri, 13 Oct 2023 08:01:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH6+Ms7y9w3d/4l+0omFpOGYY0fXlB+rgM7U9wfLBtr82Tk/wBLqvMqGnlXVNYOljqgjyl8 X-Received: by 2002:a92:db4f:0:b0:34e:2a69:883c with SMTP id w15-20020a92db4f000000b0034e2a69883cmr27105627ilq.1.1697209276038; Fri, 13 Oct 2023 08:01:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697209276; cv=none; d=google.com; s=arc-20160816; b=Ucs0wDp6TDUBxOpTOKUINPYQK0X/g4y3jn7k86JBEQZAuPe+RMsVl3rwiSf6qxGxl7 nm4uel9NJ8mktVrmRoSFy7sZwgW0f/9mcqbJKsAKk4+gRcd4+Fl9sSQEDoZjZL1s3f7m uWo0pcAJ2nqEno2wc6cBYxL/46WoOuo12E+ACaEYN146eumCx5A/15GXsTXx2EyKaY74 ZZ3wViqYJ75B1rgB4AYc2oM2jWCBJefIFnXFgjzOGmAxIv6Ss0DHfO5cflOfh2N3PCWr hXzlhoazhjhMR1VU8Lw84RnM14tYPVWEQaSKty3ucofewOtJomFcMo1pTKSJYxZWJPXL birw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Os1SaGixPymAzc87N0J0x0jFQUdmX5KiKLLsTm7SPUs=; fh=w3rm+CQktc1gAyyspusQtQaPLBzhwgYhEEkERsJRJ8U=; b=McIIDyiXs6IgqFKm+pt6TW2hTzxukVdiZg72pAm3bdu+WJpLT34Ne0IFE7VTRL56II YgHzDmvIjB5JYQdvYUhjjG0D5uWv7clVRJ3tOllVAQOLNHPcVETGuL+T8ys55x6Y/nsS v7s5kVaqNijwDLOy0278jzPFgNBNdQUDxY9s7yCDLvYWUoTbLyzHiJhnJ3oWvjcYhj+o sZlhpXUuYIP3eEUrbGkowuqq8hh5VOBOg1zMnImh8takDn4Lm9yrFFKEarhXqFNtkcdE LlJACFJ7rCgLy43E1jrNn4EBn5f5Ho9BSTUuRO3vZCuJHsd7uM9NgR/f5xyPwilZIW44 VAFQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R3O9SfM1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from pete.vger.email (pete.vger.email. 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([178.197.219.100]) by smtp.gmail.com with ESMTPSA id dh13-20020a0560000a8d00b00327cd5e5ac1sm6428267wrb.1.2023.10.13.07.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 07:59:41 -0700 (PDT) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH v2 2/2] pinctrl: qcom: lpass-lpi: allow slew rate bit in main pin config register Date: Fri, 13 Oct 2023 16:59:35 +0200 Message-Id: <20231013145935.220945-3-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> References: <20231013145935.220945-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Fri, 13 Oct 2023 08:00:20 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779652826578930062 X-GMAIL-MSGID: 1779652914207580199 Existing Qualcomm SoCs have the LPASS pin controller slew rate control in separate register, however this will change with upcoming Qualcomm SoCs. The slew rate will be part of the main register for pin configuration, thus second device IO address space is not needed. Prepare for supporting new SoCs by adding flag customizing the driver behavior for slew rate. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- Changes in v2: 1. Reversed xmas tree v1: https://lore.kernel.org/all/20230901090224.27770-1-krzysztof.kozlowski@linaro.org/ --- drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 20 ++++++++++++++------ drivers/pinctrl/qcom/pinctrl-lpass-lpi.h | 7 +++++++ 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c index 4fb808545f7f..9e410a281bfa 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c @@ -191,6 +191,7 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, unsigned int group, unsigned int slew) { unsigned long sval; + void __iomem *reg; int slew_offset; if (slew > LPI_SLEW_RATE_MAX) { @@ -203,12 +204,17 @@ static int lpi_config_set_slew_rate(struct lpi_pinctrl *pctrl, if (slew_offset == LPI_NO_SLEW) return 0; + if (pctrl->data->flags & LPI_FLAG_SLEW_RATE_SAME_REG) + reg = pctrl->tlmm_base + LPI_TLMM_REG_OFFSET * group + LPI_GPIO_CFG_REG; + else + reg = pctrl->slew_base + LPI_SLEW_RATE_CTL_REG; + mutex_lock(&pctrl->lock); - sval = ioread32(pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + sval = ioread32(reg); sval &= ~(LPI_SLEW_RATE_MASK << slew_offset); sval |= slew << slew_offset; - iowrite32(sval, pctrl->slew_base + LPI_SLEW_RATE_CTL_REG); + iowrite32(sval, reg); mutex_unlock(&pctrl->lock); @@ -452,10 +458,12 @@ int lpi_pinctrl_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(pctrl->tlmm_base), "TLMM resource not provided\n"); - pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(pctrl->slew_base)) - return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), - "Slew resource not provided\n"); + if (!(data->flags & LPI_FLAG_SLEW_RATE_SAME_REG)) { + pctrl->slew_base = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(pctrl->slew_base)) + return dev_err_probe(dev, PTR_ERR(pctrl->slew_base), + "Slew resource not provided\n"); + } ret = devm_clk_bulk_get_optional(dev, MAX_LPI_NUM_CLKS, pctrl->clks); if (ret) diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h index 387d83ee95b5..206b2c0ca828 100644 --- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h +++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.h @@ -60,6 +60,12 @@ struct pinctrl_pin_desc; .nfuncs = 5, \ } +/* + * Slew rate control is done in the same register as rest of the + * pin configuration. + */ +#define LPI_FLAG_SLEW_RATE_SAME_REG BIT(0) + struct lpi_pingroup { struct group_desc group; unsigned int pin; @@ -82,6 +88,7 @@ struct lpi_pinctrl_variant_data { int ngroups; const struct lpi_function *functions; int nfunctions; + unsigned int flags; }; int lpi_pinctrl_probe(struct platform_device *pdev);