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Fri, 13 Oct 2023 03:15:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779634960849571324 X-GMAIL-MSGID: 1779634960849571324 Add zynqmp_pm_efuse_access API in the ZynqMP firmware for read/write access of efuse memory. Signed-off-by: Praveen Teja Kundanala --- drivers/firmware/xilinx/zynqmp.c | 25 +++++++++++++++++++++++++ include/linux/firmware/xlnx-zynqmp.h | 8 ++++++++ 2 files changed, 33 insertions(+) diff --git a/drivers/firmware/xilinx/zynqmp.c b/drivers/firmware/xilinx/zynqmp.c index f8c4eb2b43f8..b0f6272e0844 100644 --- a/drivers/firmware/xilinx/zynqmp.c +++ b/drivers/firmware/xilinx/zynqmp.c @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2022 Xilinx, Inc. + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. * * Michal Simek * Davorin Mista @@ -1390,6 +1391,30 @@ int zynqmp_pm_aes_engine(const u64 address, u32 *out) } EXPORT_SYMBOL_GPL(zynqmp_pm_aes_engine); +/** + * zynqmp_pm_efuse_access - Provides access to efuse memory. + * @address: Address of the efuse params structure + * @out: Returned output value + * + * Return: Returns status, either success or error code. + */ +int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + u32 ret_payload[PAYLOAD_ARG_CNT]; + int ret; + + if (!out) + return -EINVAL; + + ret = zynqmp_pm_invoke_fn(PM_EFUSE_ACCESS, upper_32_bits(address), + lower_32_bits(address), 0, 0, + ret_payload); + *out = ret_payload[1]; + + return ret; +} +EXPORT_SYMBOL_GPL(zynqmp_pm_efuse_access); + /** * zynqmp_pm_sha_hash - Access the SHA engine to calculate the hash * @address: Address of the data/ Address of output buffer where diff --git a/include/linux/firmware/xlnx-zynqmp.h b/include/linux/firmware/xlnx-zynqmp.h index 9dda7d9898ff..721cebae3f14 100644 --- a/include/linux/firmware/xlnx-zynqmp.h +++ b/include/linux/firmware/xlnx-zynqmp.h @@ -3,6 +3,7 @@ * Xilinx Zynq MPSoC Firmware layer * * Copyright (C) 2014-2021 Xilinx + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. * * Michal Simek * Davorin Mista @@ -130,6 +131,7 @@ enum pm_api_id { PM_CLOCK_GETPARENT = 44, PM_FPGA_READ = 46, PM_SECURE_AES = 47, + PM_EFUSE_ACCESS = 53, PM_FEATURE_CHECK = 63, }; @@ -521,6 +523,7 @@ int zynqmp_pm_set_requirement(const u32 node, const u32 capabilities, const u32 qos, const enum zynqmp_pm_request_ack ack); int zynqmp_pm_aes_engine(const u64 address, u32 *out); +int zynqmp_pm_efuse_access(const u64 address, u32 *out); int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_load(const u64 address, const u32 size, const u32 flags); int zynqmp_pm_fpga_get_status(u32 *value); @@ -714,6 +717,11 @@ static inline int zynqmp_pm_aes_engine(const u64 address, u32 *out) return -ENODEV; } +static inline int zynqmp_pm_efuse_access(const u64 address, u32 *out) +{ + return -ENODEV; +} + static inline int zynqmp_pm_sha_hash(const u64 address, const u32 size, const u32 flags) { From patchwork Fri Oct 13 10:14:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 152476 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1785205vqb; Fri, 13 Oct 2023 03:16:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEKJZ5MHQkDT8ttU79mwnOB3y0nzJUw41xZVPLVmLXEQYz4Hn4F7uxE7FfWjUS/qRa1bc2J X-Received: by 2002:a05:6a20:8f01:b0:163:d382:ba99 with SMTP id b1-20020a056a208f0100b00163d382ba99mr31888428pzk.5.1697192171080; Fri, 13 Oct 2023 03:16:11 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697192171; cv=pass; d=google.com; s=arc-20160816; b=IRZpZrEkic4XCorzXVvOfwLLQ4NNAuaRiHfeuDM/8II7SDNAMtEIBdg4a1WFdl1MCf WJI2xObhdiOqHrGWGMOq8OOhUAhoUrggVqR5+WSn3pJiMLoiSlCda6Uy4a381R1EdvIG KnZZlrEMrZ5aQqG+QuUGYmAuUg2PYhVddpb2+Mqs2VYqweM8rnT5ZbPHVi/4r/g2LkDv zRMXRjde1GY8P4biBJ7RtiK8TttO5Hub7rcwvyh1dLlraa3Al59liernPb+eDTo63tyF qOsYC9nOedPzw9vWzxH4IhvwVFqK84cSBgAks2maW13f7m1BOPCxHlMDOrIJjJBr64no Weag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=METhKhQvMOTZF6vjMillbwIoUKU267ppH0f9uY07vdc=; fh=IXubkxwkwiJd9WxmQyN+6x4JcuX2UDmHVbBq2cGhPeY=; b=seQY146iCX9W6Hk+Wf5iK99X/FEWBJi4z/3rYLOTAsoQve26s8rFt9hVZTrBeRdDNl 4TwIJMdVEfWY7HSEQb7wwwW2wIy+1H4j1x41IEoeX9FUo/R5MnVTZQzwDsNqjLP7+5jB bIscjqgOquuDpm7xqkHGxiFklcq2tsuTdFUX7OXYSFBn3D8EPaSP0/zimXUWRivHpXk0 ubgOCEbREH3BF3JOXvhQrmRk1Gc+RFc09GjXu8xUkurF2ZNgFNoqBn89Vsh6bvGJ+MPg RXzdJBYwOZfuw6x0qGimmDgiWqnctc8GyFvIvsrGBsMtwFNyONt+CDBuEVJ9TIDByuwf 7KBA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=oVqaZ12L; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from howler.vger.email (howler.vger.email. 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Fri, 13 Oct 2023 03:16:03 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779634978133285101 X-GMAIL-MSGID: 1779634978133285101 Convert the xlnx,zynqmp-nvmem.txt to yaml. Signed-off-by: Praveen Teja Kundanala --- .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 46 --------------- .../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 59 +++++++++++++++++++ 2 files changed, 59 insertions(+), 46 deletions(-) delete mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt deleted file mode 100644 index 4881561b3a02..000000000000 --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt +++ /dev/null @@ -1,46 +0,0 @@ --------------------------------------------------------------------------- -= Zynq UltraScale+ MPSoC nvmem firmware driver binding = --------------------------------------------------------------------------- -The nvmem_firmware node provides access to the hardware related data -like soc revision, IDCODE... etc, By using the firmware interface. - -Required properties: -- compatible: should be "xlnx,zynqmp-nvmem-fw" - -= Data cells = -Are child nodes of silicon id, bindings of which as described in -bindings/nvmem/nvmem.txt - -------- - Example -------- -firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - method = "smc"; - - nvmem_firmware { - compatible = "xlnx,zynqmp-nvmem-fw"; - #address-cells = <1>; - #size-cells = <1>; - - /* Data cells */ - soc_revision: soc_revision { - reg = <0x0 0x4>; - }; - }; - }; -}; - -= Data consumers = -Are device nodes which consume nvmem data cells. - -For example: - pcap { - ... - - nvmem-cells = <&soc_revision>; - nvmem-cell-names = "soc_revision"; - - ... - }; diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml new file mode 100644 index 000000000000..e03ed8c32537 --- /dev/null +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/nvmem/xlnx,zynqmp-nvmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Zynq UltraScale+ MPSoC Non Volatile Memory interface + +description: | + The ZynqMP MPSoC provides access to the hardware related data + like SOC revision, IDCODE. + +maintainers: + - Kalyani Akula + - Praveen Teja Kundanala + +allOf: + - $ref: "nvmem.yaml#" + +properties: + compatible: + const: xlnx,zynqmp-nvmem-fw + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + +required: + - compatible + +patternProperties: + "^soc_revision@0$": + type: object + description: + This node is used to read SOC version and IDCODE of ZynqMP. Read-only. + + properties: + reg: + maxItems: 1 + + required: + - reg + +additionalProperties: false + +examples: + - | + nvmem_firmware { + compatible = "xlnx,zynqmp-nvmem-fw"; + #address-cells = <1>; + #size-cells = <1>; + + /* Data cells */ + soc_revision: soc_revision@0 { + reg = <0x0 0x4>; + }; + }; From patchwork Fri Oct 13 10:14:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 152478 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1785409vqb; Fri, 13 Oct 2023 03:16:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHkcZEomlUeH6mgfckwoNiYhUqWZaj8amFTy6rnUsj/sr6TL7Jbr9fOmL/LZ/8HMM2T9yWE X-Received: by 2002:a05:6a20:daa8:b0:171:947f:465b with SMTP id iy40-20020a056a20daa800b00171947f465bmr13157385pzb.4.1697192197316; Fri, 13 Oct 2023 03:16:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697192197; cv=pass; d=google.com; s=arc-20160816; b=KwkdIQQC9EYuTjSIyZG8OcvG8VvuQ71icqBFMVKuZYMOb9qp2EF4lR+jilMod1igYg QAREVbH7Nu+G4FWx171F+wzp1L82B4maXcvvzZKm2vyluyqIOA8oc3AB783/9pjMgToI KI8efe5DHDaJ1jQ5racdmsmjtCf8fo0Fomq90aTFauVO+mv7DDSvqHaAEpjHyMPFyYuz R+yi+G7ih6URX5R6/9RCKkC+LkP0bhrcr4hUF6try+T+xzq1qYp4F8p5LsqMo9F8E+Xh +7gBsy6tyNkb6b4sSHJXq53PZtodZwD1bWXj6IP9Ont9gPVZbQwnprcPymzxLOJ5VnFs xiHQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=C3aiIK1J/uxTumQDI4aYsDbzu79nt0ZPEBe//iwH6XA=; fh=IXubkxwkwiJd9WxmQyN+6x4JcuX2UDmHVbBq2cGhPeY=; b=WHeNivRlgPjAZlb4//rELPK7xZbcfzD8i0n661S4HVMGOWGoa/9YkZrMCRU/3ECcgD lcvq5TBYa98lEstfo+YtY77VQ0t/8QJfjlSzTmcSkg2BtW5tKJrxf2q7Z1BOvrDF+47/ 9J2ZcJMsceyE9L2kLHM/tbbTknuV5DUTEBFnp0I7XruwzaC852GGtlnVrzk/Kkyi2Ond IUUIoVuTtBNoeGQi4n+LgwgBwHbr5JUrOerzQGqg9btYOOmUMDwhJw7d8Iz21bSn1p/v pDsovHseMHHF2BlvNGRFeyg0XKXrkZk1r5091rwy0dBAEHITlL9UkShK169YnIZ0Hgfo kDDA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=DmwfaumX; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from fry.vger.email (fry.vger.email. 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Fri, 13 Oct 2023 03:16:34 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779635005640461713 X-GMAIL-MSGID: 1779635005640461713 Added nodes for ZynqMP specific purpose and PUF user efuses Signed-off-by: Praveen Teja Kundanala --- .../bindings/nvmem/xlnx,zynqmp-nvmem.yaml | 213 +++++++++++++++++- 1 file changed, 212 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml index e03ed8c32537..d2a036a80cda 100644 --- a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml +++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.yaml @@ -8,7 +8,7 @@ title: Zynq UltraScale+ MPSoC Non Volatile Memory interface description: | The ZynqMP MPSoC provides access to the hardware related data - like SOC revision, IDCODE. + like SOC revision, IDCODE and specific purpose efuses. maintainers: - Kalyani Akula @@ -43,6 +43,140 @@ patternProperties: required: - reg + "^efuse_dna@c$": + type: object + description: + This node is used to read DNA of ZynqMP SOC. Read-only. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_usr(0@20|1@24|2@28|3@2c|4@30|5@34|6@38|7@3c)$": + type: object + description: + Eight 32-bit user efuses. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_miscusr@40$": + type: object + description: + 32-bit MISC user efuse space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_chash@50$": + type: object + description: + 32-bit PUF chash space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_pufmisc@54$": + type: object + description: + 32-bit PUF MISC control space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_sec@58$": + type: object + description: + 32-bit secure control space. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_spkid@5c$": + type: object + description: + 32-bit SPK ID. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_aeskey@60$": + type: object + description: + 256-bit aes key. Only Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_ppk0hash@a0$": + type: object + description: + 384-bit PPK0 hash. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_ppk1hash@d0$": + type: object + description: + 384-bit PPK1 hash. Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + + "^efuse_pufuser@100$": + type: object + description: + This node represents the 127(0x7F) 32-bit PUF(Physical Unclonable Function) + helper data efuses which are repurposed as user fuses. + Read and Write is supported. + + properties: + reg: + maxItems: 1 + + required: + - reg + additionalProperties: false examples: @@ -56,4 +190,81 @@ examples: soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; + /* + * efuse memory access: + * all the efuse fields need to be read + * with the exact size specified in the node + */ + /* DNA */ + efuse_dna: efuse_dna@c { + reg = <0xc 0xc>; + }; + /* User 0 */ + efuse_usr0: efuse_usr0@20 { + reg = <0x20 0x4>; + }; + /* User 1 */ + efuse_usr1: efuse_usr1@24 { + reg = <0x24 0x4>; + }; + /* User 2 */ + efuse_usr2: efuse_usr2@28 { + reg = <0x28 0x4>; + }; + /* User 3 */ + efuse_usr3: efuse_usr3@2c { + reg = <0x2c 0x4>; + }; + /* User 4 */ + efuse_usr4: efuse_usr4@30 { + reg = <0x30 0x4>; + }; + /* User 5 */ + efuse_usr5: efuse_usr5@34 { + reg = <0x34 0x4>; + }; + /* User 6 */ + efuse_usr6: efuse_usr6@38 { + reg = <0x38 0x4>; + }; + /* User 7 */ + efuse_usr7: efuse_usr7@3c { + reg = <0x3c 0x4>; + }; + /* Misc user control bits */ + efuse_miscusr: efuse_miscusr@40 { + reg = <0x40 0x4>; + }; + /* PUF chash */ + efuse_chash: efuse_chash@50 { + reg = <0x50 0x4>; + }; + /* PUF misc */ + efuse_pufmisc: efuse_pufmisc@54 { + reg = <0x54 0x4>; + }; + /* SEC_CTRL */ + efuse_sec: efuse_sec@58 { + reg = <0x58 0x4>; + }; + /* SPK ID */ + efuse_spkid: efuse_spkid@5c { + reg = <0x5c 0x4>; + }; + /* AES Key */ + efuse_aeskey: efuse_aeskey@60 { + reg = <0x60 0x20>; + }; + /* PPK0 hash */ + efuse_ppk0hash: efuse_ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + /* PPK1 hash */ + efuse_ppk1hash: efuse_ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + /* PUF user fuses */ + efuse_pufuser: efuse_pufuser@100 { + reg = <0x100 0x7F>; + }; }; From patchwork Fri Oct 13 10:14:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 152479 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1785646vqb; Fri, 13 Oct 2023 03:17:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGIMI1VeRrdjm/Adt/B/717EnJI+cmClSSLcJSlkqjAu37ZcTk6dup6eCrFYG+OB6Rkt3Nb X-Received: by 2002:a05:6870:c689:b0:1e1:e6ee:94b6 with SMTP id cv9-20020a056870c68900b001e1e6ee94b6mr28849437oab.4.1697192236483; Fri, 13 Oct 2023 03:17:16 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697192236; cv=pass; d=google.com; s=arc-20160816; b=I7VseOAm/mfoPkWK4kacM+Td+iF/Uv4UfggHjn9t6aAy3q1xVAvdYHhZsmm2xsC/kT mv1peezxaW3QwHMqdoBYx1Xb7Wo2M3uAm9/NpneCvQ0mDazj0romoMO/mKzLbbwZf++V l95N/5qN64S6Abj6kU3xhFgBQqo6qtpJEj0uJ2H+FfSOLRRDQeicRYhevTBZg5RrxGEn raH6qO5E5fdTPd20L+5SPYJJ9fDgAFsF2vpdjcc/Foc4Wg6P+BgIKuLRpX/q++ICdLMF /9Q3Sq+0W/SrT+cjrlGhaKRl/q0cEti6rffFdW+q3kWA2xRAN4peLpnYZIXWsevubMgl B+vw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=H0j79BCH9vq4RGAV4Pitapaa36NIzmPJw6i6r15vYQw=; fh=IXubkxwkwiJd9WxmQyN+6x4JcuX2UDmHVbBq2cGhPeY=; b=kXJMOxIfoI/Wk0OWaOH6syE9gVjoWoLWIEk1zGMxnZb3NnSgmjAOGmgfuQn1PDXHIv w+OPDFUqJ7kPmrS+0ClkAMdOP5D0X5Fwh5nKIXzihPVykgR7g4KB3N40EhU6RobZdHLw Zhj5VrfvwoUDTfOGVdkf3r2dZcdlaxOPh7s8ZoQQKxhMV0UKIqwA0IXNQRnu2hiyZ5X9 6GgxOg6+heFF79bxpXaUBK12gz6kx8Qe57apyBapdt4pJxhr6WN7xP95AZ+NEQVasp6p WbByZpJF+1tOpU2YNSmf27XyvGqTA0BTy9gZTv0HFNgj1CTdSs8GRSpJpSdWGNle/jbD O1bA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="E/r6AXqP"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Fri, 13 Oct 2023 03:16:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779635046385339548 X-GMAIL-MSGID: 1779635046385339548 Add nvmem DT nodes for ZynqMP SOC Signed-off-by: Praveen Teja Kundanala --- arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 55 ++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi index 02cfcc716936..b8807dcce442 100644 --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi @@ -190,6 +190,61 @@ nvmem_firmware { soc_revision: soc_revision@0 { reg = <0x0 0x4>; }; + /* efuse access */ + efuse_dna: efuse_dna@c { + reg = <0xc 0xc>; + }; + efuse_usr0: efuse_usr0@20 { + reg = <0x20 0x4>; + }; + efuse_usr1: efuse_usr1@24 { + reg = <0x24 0x4>; + }; + efuse_usr2: efuse_usr2@28 { + reg = <0x28 0x4>; + }; + efuse_usr3: efuse_usr3@2c { + reg = <0x2c 0x4>; + }; + efuse_usr4: efuse_usr4@30 { + reg = <0x30 0x4>; + }; + efuse_usr5: efuse_usr5@34 { + reg = <0x34 0x4>; + }; + efuse_usr6: efuse_usr6@38 { + reg = <0x38 0x4>; + }; + efuse_usr7: efuse_usr7@3c { + reg = <0x3c 0x4>; + }; + efuse_miscusr: efuse_miscusr@40 { + reg = <0x40 0x4>; + }; + efuse_chash: efuse_chash@50 { + reg = <0x50 0x4>; + }; + efuse_pufmisc: efuse_pufmisc@54 { + reg = <0x54 0x4>; + }; + efuse_sec: efuse_sec@58 { + reg = <0x58 0x4>; + }; + efuse_spkid: efuse_spkid@5c { + reg = <0x5c 0x4>; + }; + efuse_aeskey: efuse_aeskey@60 { + reg = <0x60 0x20>; + }; + efuse_ppk0hash: efuse_ppk0hash@a0 { + reg = <0xa0 0x30>; + }; + efuse_ppk1hash: efuse_ppk1hash@d0 { + reg = <0xd0 0x30>; + }; + efuse_pufuser: efuse_pufuser@100 { + reg = <0x100 0x7F>; + }; }; zynqmp_pcap: pcap { From patchwork Fri Oct 13 10:14:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveen Teja Kundanala X-Patchwork-Id: 152477 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1785279vqb; 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Fri, 13 Oct 2023 03:16:18 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779634988600410568 X-GMAIL-MSGID: 1779634988600410568 Add support to read/write efuse memory map of ZynqMP Below are the offsets of ZynqMP efuse memory map 0 - SOC version(read only) 0xC - 0xFC -ZynqMP specific purpose efuses 0x100 - 0x17F - Physical Unclonable Function(PUF) efuses repurposed as user efuses Signed-off-by: Praveen Teja Kundanala --- drivers/nvmem/zynqmp_nvmem.c | 216 ++++++++++++++++++++++++++++++----- 1 file changed, 185 insertions(+), 31 deletions(-) diff --git a/drivers/nvmem/zynqmp_nvmem.c b/drivers/nvmem/zynqmp_nvmem.c index f49bb9a26d05..e6123a32268a 100644 --- a/drivers/nvmem/zynqmp_nvmem.c +++ b/drivers/nvmem/zynqmp_nvmem.c @@ -1,8 +1,10 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2019 Xilinx, Inc. + * Copyright (C), 2022 - 2023 Advanced Micro Devices, Inc. */ +#include #include #include #include @@ -10,36 +12,190 @@ #include #define SILICON_REVISION_MASK 0xF +#define P_USER_0_64_UPPER_MASK GENMASK(31, 16) +#define P_USER_127_LOWER_4_BIT_MASK GENMASK(3, 0) +#define WORD_INBYTES 4 +#define SOC_VER_SIZE 0x4 +#define EFUSE_MEMORY_SIZE 0x177 +#define UNUSED_SPACE 0x8 +#define ZYNQMP_NVMEM_SIZE (SOC_VER_SIZE + UNUSED_SPACE + \ + EFUSE_MEMORY_SIZE) +#define SOC_VERSION_OFFSET 0x0 +#define EFUSE_START_OFFSET 0xC +#define EFUSE_END_OFFSET 0xFC +#define EFUSE_PUF_START_OFFSET 0x100 +#define EFUSE_PUF_MID_OFFSET 0x140 +#define EFUSE_PUF_END_OFFSET 0x17F +#define EFUSE_NOT_ENABLED 29 -struct zynqmp_nvmem_data { - struct device *dev; - struct nvmem_device *nvmem; +/* + * efuse access type + */ +enum efuse_access { + EFUSE_READ = 0, + EFUSE_WRITE +}; + +/** + * struct xilinx_efuse - the basic structure + * @src: address of the buffer to store the data to be write/read + * @size: read/write word count + * @offset: read/write offset + * @flag: 0 - represents efuse read and 1- represents efuse write + * @pufuserfuse:0 - represents non-puf efuses, offset is used for read/write + * 1 - represents puf user fuse row number. + * + * this structure stores all the required details to + * read/write efuse memory. + */ +struct xilinx_efuse { + u64 src; + u32 size; + u32 offset; + enum efuse_access flag; + u32 pufuserfuse; }; -static int zynqmp_nvmem_read(void *context, unsigned int offset, - void *val, size_t bytes) +static int zynqmp_efuse_access(void *context, unsigned int offset, + void *val, size_t bytes, enum efuse_access flag, + unsigned int pufflag) { + struct device *dev = context; + struct xilinx_efuse *efuse; + dma_addr_t dma_addr; + dma_addr_t dma_buf; + size_t words = bytes / WORD_INBYTES; int ret; - int idcode, version; - struct zynqmp_nvmem_data *priv = context; - - ret = zynqmp_pm_get_chipid(&idcode, &version); - if (ret < 0) - return ret; + int value; + char *data; + + if (bytes % WORD_INBYTES != 0) { + dev_err(dev, "Bytes requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag == 0 && offset % WORD_INBYTES) { + dev_err(dev, "Offset requested should be word aligned\n"); + return -EOPNOTSUPP; + } + + if (pufflag == 1 && flag == EFUSE_WRITE) { + memcpy(&value, val, bytes); + if ((offset == EFUSE_PUF_START_OFFSET || + offset == EFUSE_PUF_MID_OFFSET) && + value & P_USER_0_64_UPPER_MASK) { + dev_err(dev, "Only lower 4 bytes are allowed to be programmed in P_USER_0 & P_USER_64\n"); + return -EOPNOTSUPP; + } + + if (offset == EFUSE_PUF_END_OFFSET && + (value & P_USER_127_LOWER_4_BIT_MASK)) { + dev_err(dev, "Only MSB 28 bits are allowed to be programmed for P_USER_127\n"); + return -EOPNOTSUPP; + } + } + + efuse = dma_alloc_coherent(dev, sizeof(struct xilinx_efuse), + &dma_addr, GFP_KERNEL); + if (!efuse) + return -ENOMEM; - dev_dbg(priv->dev, "Read chipid val %x %x\n", idcode, version); - *(int *)val = version & SILICON_REVISION_MASK; + data = dma_alloc_coherent(dev, sizeof(bytes), + &dma_buf, GFP_KERNEL); + if (!data) { + ret = -ENOMEM; + goto efuse_data_fail; + } + + if (flag == EFUSE_WRITE) { + memcpy(data, val, bytes); + efuse->flag = EFUSE_WRITE; + } else { + efuse->flag = EFUSE_READ; + } + + efuse->src = dma_buf; + efuse->size = words; + efuse->offset = offset; + efuse->pufuserfuse = pufflag; + + zynqmp_pm_efuse_access(dma_addr, (u32 *)&ret); + if (ret != 0) { + if (ret == EFUSE_NOT_ENABLED) { + dev_err(dev, "efuse access is not enabled\n"); + ret = -EOPNOTSUPP; + } else { + dev_err(dev, "Error in efuse read %x\n", ret); + ret = -EPERM; + } + goto efuse_access_err; + } + + if (flag == EFUSE_READ) + memcpy(val, data, bytes); +efuse_access_err: + dma_free_coherent(dev, sizeof(bytes), + data, dma_buf); +efuse_data_fail: + dma_free_coherent(dev, sizeof(struct xilinx_efuse), + efuse, dma_addr); + + return ret; +} - return 0; +static int zynqmp_nvmem_read(void *context, unsigned int offset, void *val, size_t bytes) +{ + struct device *dev = context; + int ret; + int pufflag = 0; + int idcode; + int version; + + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET) + pufflag = 1; + + switch (offset) { + /* Soc version offset is zero */ + case SOC_VERSION_OFFSET: + if (bytes != SOC_VER_SIZE) + return -EOPNOTSUPP; + + ret = zynqmp_pm_get_chipid((u32 *)&idcode, (u32 *)&version); + if (ret < 0) + return ret; + + dev_dbg(dev, "Read chipid val %x %x\n", idcode, version); + *(int *)val = version & SILICON_REVISION_MASK; + break; + /* Efuse offset starts from 0xc */ + case EFUSE_START_OFFSET ... EFUSE_END_OFFSET: + case EFUSE_PUF_START_OFFSET ... EFUSE_PUF_END_OFFSET: + ret = zynqmp_efuse_access(context, offset, val, + bytes, EFUSE_READ, pufflag); + break; + default: + *(u32 *)val = 0xDEADBEEF; + ret = 0; + break; + } + + return ret; } -static struct nvmem_config econfig = { - .name = "zynqmp-nvmem", - .owner = THIS_MODULE, - .word_size = 1, - .size = 1, - .read_only = true, -}; +static int zynqmp_nvmem_write(void *context, + unsigned int offset, void *val, size_t bytes) +{ + int pufflag = 0; + + if (offset < EFUSE_START_OFFSET || offset > EFUSE_PUF_END_OFFSET) + return -EOPNOTSUPP; + + if (offset >= EFUSE_PUF_START_OFFSET && offset <= EFUSE_PUF_END_OFFSET) + pufflag = 1; + + return zynqmp_efuse_access(context, offset, + val, bytes, EFUSE_WRITE, pufflag); +} static const struct of_device_id zynqmp_nvmem_match[] = { { .compatible = "xlnx,zynqmp-nvmem-fw", }, @@ -50,20 +206,18 @@ MODULE_DEVICE_TABLE(of, zynqmp_nvmem_match); static int zynqmp_nvmem_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; - struct zynqmp_nvmem_data *priv; - - priv = devm_kzalloc(dev, sizeof(struct zynqmp_nvmem_data), GFP_KERNEL); - if (!priv) - return -ENOMEM; + struct nvmem_config econfig = {}; - priv->dev = dev; + econfig.name = "zynqmp-nvmem"; + econfig.owner = THIS_MODULE; + econfig.word_size = 1; + econfig.size = ZYNQMP_NVMEM_SIZE; econfig.dev = dev; + econfig.priv = dev; econfig.reg_read = zynqmp_nvmem_read; - econfig.priv = priv; - - priv->nvmem = devm_nvmem_register(dev, &econfig); + econfig.reg_write = zynqmp_nvmem_write; - return PTR_ERR_OR_ZERO(priv->nvmem); + return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &econfig)); } static struct platform_driver zynqmp_nvmem_driver = {