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[8.43.85.97]) by mx.google.com with ESMTPS id w21-20020a05622a135500b00417ba4f4e18si815480qtk.311.2023.10.13.01.07.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 01:07:24 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=G6FgwysY; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D163E385B515 for ; Fri, 13 Oct 2023 08:07:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id B72A53858C3A for ; Fri, 13 Oct 2023 08:06:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org B72A53858C3A Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697184410; x=1728720410; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=fMnbGkU8kRA9hdmAh9VVQe5I6WswDFnoaJgBqexRqX0=; b=G6FgwysYX8gbd8a0FNCvXXpnXHW0/fAr4TRSdIXO6XqPiWHA/L1MGWnJ E6dd07wWRHnskoXlrh5mwi3yt3onFTVn/ah91Bctqo5n4x+KWqiF0UKAI HBTW/FFVG8B6BQWyvVbLkgQx8R3ABnrVzUYoMEyRNexpTHwD/yikslkJl M012B36CP3uBCOj5zcxP32LNzCsZWm2DGURxUq/X3vSg0VK2GJ45/9IL/ La25SzCegjR3mPofl1sb01cTmK1RkHzw/24T3BhwI6myNnsNZT2cllMlY 4QBXpEOKt+IThAZesZc3AWJaOi6ySY+yiy4AmHIU3QE2gMq4BTPNL2ckB w==; X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="375476799" X-IronPort-AV: E=Sophos;i="6.03,221,1694761200"; d="scan'208";a="375476799" Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 13 Oct 2023 01:06:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="754621899" X-IronPort-AV: E=Sophos;i="6.03,221,1694761200"; d="scan'208";a="754621899" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga002.jf.intel.com with ESMTP; 13 Oct 2023 01:06:45 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 9BC0410056F5; Fri, 13 Oct 2023 16:06:44 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Add test for FP iceil auto vectorization Date: Fri, 13 Oct 2023 16:06:43 +0800 Message-Id: <20231013080643.1813480-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779626875469966827 X-GMAIL-MSGID: 1779626875469966827 From: Pan Li The below FP API are supported already by sharing the same standard name, as well as the machine mode. int iceil (float); This patch would like to add the test cases for ensuring the correctness. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-iceil-run-0.c: New test. * gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- .../riscv/rvv/autovec/unop/math-iceil-0.c | 19 ++++++ .../riscv/rvv/autovec/unop/math-iceil-run-0.c | 63 +++++++++++++++++++ .../riscv/rvv/autovec/vls/math-iceil-0.c | 30 +++++++++ 3 files changed, 112 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-run-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c new file mode 100644 index 00000000000..2d4a1d163d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-0.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float_int___builtin_iceilf: +** frrm\s+[atx][0-9]+ +** ... +** fsrmi\s+3 +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*ma +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+ +** ... +** fsrm\s+[atx][0-9]+ +** ret +*/ +TEST_UNARY_CALL_CVT (float, int, __builtin_iceilf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-run-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-run-0.c new file mode 100644 index 00000000000..714173a7f8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-iceil-run-0.c @@ -0,0 +1,63 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +int out[ARRAY_SIZE]; +int ref[ARRAY_SIZE]; + +TEST_UNARY_CALL_CVT (float, int, __builtin_iceilf) +TEST_ASSERT (int) + +TEST_INIT_CVT (float, 1.2, int, __builtin_iceilf (1.2), 1) +TEST_INIT_CVT (float, -1.2, int, __builtin_iceilf (-1.2), 2) +TEST_INIT_CVT (float, 0.5, int, __builtin_iceilf (0.5), 3) +TEST_INIT_CVT (float, -0.5, int, __builtin_iceilf (-0.5), 4) +TEST_INIT_CVT (float, 0.1, int, __builtin_iceilf (0.1), 5) +TEST_INIT_CVT (float, -0.1, int, __builtin_iceilf (-0.1), 6) +TEST_INIT_CVT (float, 3.0, int, __builtin_iceilf (3.0), 7) +TEST_INIT_CVT (float, -3.0, int, __builtin_iceilf (-3.0), 8) +TEST_INIT_CVT (float, 8388607.5, int, __builtin_iceilf (8388607.5), 9) +TEST_INIT_CVT (float, 8388609.0, int, __builtin_iceilf (8388609.0), 10) +TEST_INIT_CVT (float, -8388607.5, int, __builtin_iceilf (-8388607.5), 11) +TEST_INIT_CVT (float, -8388609.0, int, __builtin_iceilf (-8388609.0), 12) +TEST_INIT_CVT (float, 0.0, int, __builtin_iceilf (-0.0), 13) +TEST_INIT_CVT (float, -0.0, int, __builtin_iceilf (-0.0), 14) +TEST_INIT_CVT (float, 2147483520.0, int, __builtin_iceilf (2147483520.0), 15) +TEST_INIT_CVT (float, 2147483648.0, int, 0x7fffffff, 16) +TEST_INIT_CVT (float, -2147483648.0, int, __builtin_iceilf (-2147483648.0), 17) +TEST_INIT_CVT (float, -2147483904.0, int, 0x80000000, 18) +TEST_INIT_CVT (float, __builtin_inf (), int, __builtin_iceilf (__builtin_inff ()), 19) +TEST_INIT_CVT (float, -__builtin_inf (), int, __builtin_iceilf (-__builtin_inff ()), 20) +TEST_INIT_CVT (float, __builtin_nanf (""), int, 0x7fffffff, 21) + +int +main () +{ + RUN_TEST_CVT (float, int, 1, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 2, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 3, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 4, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 5, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 6, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 7, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 8, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 9, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 10, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 11, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 12, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 13, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 14, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 15, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 16, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 17, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 18, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 19, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 20, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + RUN_TEST_CVT (float, int, 21, __builtin_iceilf, in, out, ref, ARRAY_SIZE); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c new file mode 100644 index 00000000000..f8877a1d564 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-iceil-0.c @@ -0,0 +1,30 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V_CVT (iceilf, 1, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 2, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 4, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 8, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 16, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 32, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 64, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 128, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 256, float, int, __builtin_iceilf) +DEF_OP_V_CVT (iceilf, 512, float, int, __builtin_iceilf) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+} 9 } } */