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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [RESEND PATCH V9 1/7] x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion. 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Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- arch/x86/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 66bfabae8814..a2e163acf623 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1054,8 +1054,9 @@ config SCHED_MC config SCHED_MC_PRIO bool "CPU core priorities scheduler support" - depends on SCHED_MC && CPU_SUP_INTEL - select X86_INTEL_PSTATE + depends on SCHED_MC + select X86_INTEL_PSTATE if CPU_SUP_INTEL + select X86_AMD_PSTATE if CPU_SUP_AMD && ACPI select CPU_FREQ default y help From patchwork Fri Oct 13 03:31:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 152286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1642063vqb; Thu, 12 Oct 2023 20:33:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHGIBYw6v7Q6ogcXsOayb6dqLFc6lX5M/Z/H4uS3pxXCUqtxzM5aCVgLw3PFyDZ1qrpRRol X-Received: by 2002:a17:90a:1:b0:27d:1f88:3cd with SMTP id 1-20020a17090a000100b0027d1f8803cdmr3702580pja.4.1697168035559; Thu, 12 Oct 2023 20:33:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697168035; cv=pass; d=google.com; s=arc-20160816; b=e1biwDvVQ3prtn9tcv+RMxr/BDK9hTNX6CuvOk+X+vSxNXJc46PwOm7y/DdPskqODV be5JIpI4DWw9dD6jR5QHrUo76N8l+LJMsz2FTq3vDdNhQlgViRBZ2TRXL4v+S9bvtRj8 LvPT6Oc3kL2Kzswr/OadyWq5HPpLRyb/gO+zQmtP3DR3KfiTzWLtJq/KW20n3heoK11l g0xGc8uVwU7ZDd2QFyLTAqDxtjhXPtp/Hfe7/6UF5iE+Xj1cxRwFQSYr2dP+7aCQqoJK NNR4p1vlHfXl64M8ivyve9klzMEQkRYyPNQRY21z7loTr0QHTo6xMt8z9IMBteScFIce SJrQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AlF2WKiSUPyODRJ7ueMUccEPh7maCKY1Dj6+XRqyp7A=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=sji7d7+vh0s27Oe84l99fJy17JbUvs7Vy60BLBV+KZMTi4wy3X3WYX7e/2hpi27WaS DlS1DZos8qYld/K9SVnWmxoN7OVq8uCMwY4VA1rrrkV4+v/RBwz9rBdomSK9YsnJdV5t gXDJDPcqxWICzGYc8lOmOQDB4sw9eaWFV9R32OaqexubBOMzCIWYSEfIl3IgQNSYPNbi oNqRfrydbq5PWDXaiUuZmdfDfZgfkz7cw2C852Kqfv0kXMVdMrVluCMf5kZ0wBPOCWfE qj31/HOBBoWNSU1LM1jXzZjPYXKnHlGPzLFWPtEGIxOjuJGtESxPfNTjKE04rECpv8EF GujA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=TABSuQf4; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [RESEND PATCH V9 2/7] acpi: cppc: Add get the highest performance cppc control Date: Fri, 13 Oct 2023 11:31:13 +0800 Message-ID: <20231013033118.3759311-3-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013033118.3759311-1-li.meng@amd.com> References: <20231013033118.3759311-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|DM4PR12MB5937:EE_ X-MS-Office365-Filtering-Correlation-Id: bc4f7448-d263-435f-eb7c-08dbcb9cf92b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: aC+v3PdFnsJg513BsNyDyiR+fzv1FVxs+iDjlJn0hRSrDm7vEuUk1hqUmkmdtC/X7rvHC9zQQMMMS4zPSyChlaP53JFJ7nNZ6xBFNOOEhutzigjScU/v/oCVs2AzsMwk0BDPeJrldFzdAZx5hYfhpFzjtAcObWrzPYXy5clXPhBAru0F9cYrlgfCY0iEpDm4+RdYsh2XIb/R9DwIWSBcXfWB+Ads978aTSMDotCuqnZ8Ioa+IEV6PInPfBiFgdWPc7dZ5GhDJuPG4QcgmoktpOnwnKOXAIavkIOvZlV/YACd7s/ezVEY4Ttvd93yvWa/oH7pvN/+sMMay8NzgDWdg8fNvjQ4cuM4JqRDbrSg1phSyEgioIr/KZy9gWlk0kWelRROATTdPFovttkLbcUvg/z+oYC+GQJ893UGBluRonxwUkjqEoSPeVKQ3RXuy/+f5t6ar61R/trvbj2wq+TZ5QvY7dHa0r9ckVE5g9wcZpUuyR1i64q1AdUwvP8ACVGgbYN+gAeccxZxAStP9MtGN0Cf8oe8W9ViWV9GojMuT899xMtDyLIwAqDqbdy4Kegd1rU7wkV7ceTT7g2ysi6Y0gyOXDqzbiimSj++aUF5eEPFfWQw8gwceUf520aU14w0FD4eRqlfvgn+fls0qR26wo+HbE/NUiwlLr/EJ9dyDa7kD78gtOCsLRQJSJIB+7j1hkUPjdqzgiKrGHDemT+m4fMngosBXZSHExBmtrn0QlzBomAbVrJk0Q5ObqZcSN+uqpEadgKfiN26ImPUreWM9z18yyGIUfb+bjn/5dlH558= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(396003)(376002)(136003)(230922051799003)(82310400011)(1800799009)(64100799003)(186009)(451199024)(46966006)(40470700004)(36840700001)(86362001)(82740400003)(36756003)(40460700003)(40480700001)(478600001)(2906002)(41300700001)(4326008)(966005)(7696005)(6666004)(7416002)(8676002)(8936002)(5660300002)(2616005)(426003)(1076003)(336012)(47076005)(70206006)(110136005)(70586007)(316002)(6636002)(16526019)(54906003)(26005)(36860700001)(356005)(81166007)(15583001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 03:32:05.7392 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc4f7448-d263-435f-eb7c-08dbcb9cf92b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5937 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 20:32:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779609670153179399 X-GMAIL-MSGID: 1779609670153179399 Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values. Please refer to the ACPI_Spec for details on continuous performance control of CPPC. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Acked-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#highest-performance --- drivers/acpi/cppc_acpi.c | 13 +++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 18 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7ff269a78c20..ad388a0e8484 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_highest_perf - Get the highest performance register value. + * @cpunum: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_highest_perf); + /** * cppc_get_epp_perf - Get the epp register value. * @cpunum: CPU from which to get epp preference value. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6126c977ece0..c0b69ffe7bdb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { #ifdef CONFIG_ACPI_CPPC_LIB extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); +extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); @@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { return -ENOTSUPP; } +static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) { return -ENOTSUPP; From patchwork Fri Oct 13 03:31:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 152290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1642169vqb; Thu, 12 Oct 2023 20:34:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF1zzOwceKbel5ONxHe/lCBAI6wjve0xtzU/Ywm/2q2Hoqx8gHTsXUtPb7JZ8J3l2t1xiHv X-Received: by 2002:a17:902:e80a:b0:1c4:1e65:1e5e with SMTP id u10-20020a170902e80a00b001c41e651e5emr28885964plg.0.1697168059317; Thu, 12 Oct 2023 20:34:19 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697168059; cv=pass; d=google.com; s=arc-20160816; b=zaLD3JQAp+zmSvP73aYIUIIY2eUlvMg7byQ/oEgu0I6Tmyede1OLz4hhu1N2b+OMe6 vPmo6d/d2MXdo6umacV+vOadH6vjjFJLM7EWGBJ9/lW++2Tzuvp/92IoxX1BwTj1WmMD jNOWiGjVvuN/Q9c9z4ruPQWZkIlqwhOk71qUo4hrQALs22YKlpK5NRxSuk5YbBH6cbVb 4cIcRV8RcQ5mB0sNwsOvcHuK7Cb1+QjeLl19XzRkCDRXCauk8JmIVO6H4FIGOLPGDpPf 0Xk2KEWh0NPnWLIUKCw1bzgQwwjuk928/OIRnhvIaO0LZ2lRdwvEszOJAXuJ/WTr8x01 lquA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N6sl1hWJ/Ba/x5EvJmAWdUD/rhbznGTYZmFl2wYOADI=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=kMizUOXB5iAVXjUwFY0lMYai2Q46buVSItSXkxXBgDAJSzPQ785Pjd4nrbrZBKOg9/ cSUfyKbre7f0zLtRXtDe1cLBPcYxMGUM2+XNvH5eL7vW7AhjWzxucNga0XoZ9y0Xq+k/ ptkFl1z4W+1oAjlXPjFY50PMuYt5E9F+SLXif2kxLOq/NkatVQrxJoEjN/AW5txawIJ+ WxRORvKGkWs5iuuP1l+iVIRK4EO/Vf5GBV5jcCVqyOwggXgGxFttTfnwBphpcNXNo7OC sbyFFl9ES4iJz7pwx2syZifQMogYNBYsDSMemc+LznhlMTDsZa3SyRShe596wkK5RbEs Qxvg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Tn7OM818; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [RESEND PATCH V9 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting. 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We call it amd-pstate preferrred core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by amd-pstate when the system boots. Add a variable hw_prefcore in cpudata structure. It will check if the processor and power firmware support preferred core feature. Add one new early parameter `disable` to allow user to disable the preferred core. Only when hardware supports preferred core and user set `enabled` in early parameter, amd pstate driver supports preferred core featue. Tested-by: Oleksandr Natalenko Reviewed-by: Huang Rui Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 155 +++++++++++++++++++++++++++++++---- include/linux/amd-pstate.h | 4 + 2 files changed, 143 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..6aae383990f1 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,8 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 +#define AMD_PSTATE_MAX_CPPC_PERF 255 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -64,6 +67,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +static bool amd_pstate_prefcore = true; /* * AMD Energy Preference Performance (EPP) @@ -290,23 +294,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +320,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +676,93 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/* + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + u64 cppc_highest_perf; + + ret = cppc_get_highest_perf(cpu, &cppc_highest_perf); + WRITE_ONCE(*highest_perf, cppc_highest_perf); + } + + return (ret); +} + +static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +{ + int ret, prio; + u32 highest_perf; + static u32 max_highest_perf = 0, min_highest_perf = U32_MAX; + + ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf); + if (ret) + return; + + cpudata->hw_prefcore = true; + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf == AMD_PSTATE_MAX_CPPC_PERF) { + pr_debug("AMD CPPC preferred core is unsupported!\n"); + cpudata->hw_prefcore = false; + return; + } + + if (!amd_pstate_prefcore) + return; + + /* The maximum value of highest perf is 255 */ + prio = (int)(highest_perf & 0xff); + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to + * update them at any time after it has been called. + */ + sched_set_itmt_core_prio(prio, cpudata->cpu); + + if (max_highest_perf <= min_highest_perf) { + if (highest_perf > max_highest_perf) + max_highest_perf = highest_perf; + + if (highest_perf < min_highest_perf) + min_highest_perf = highest_perf; + + if (max_highest_perf > min_highest_perf) { + /* + * This code can be run during CPU online under the + * CPU hotplug locks, so sched_set_itmt_support() + * cannot be called from here. Queue up a work item + * to invoke it. + */ + schedule_work(&sched_prefcore_work); + } + } +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +784,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -845,6 +934,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, + char *buf) +{ + bool hw_prefcore; + struct amd_cpudata *cpudata = policy->driver_data; + + hw_prefcore = READ_ONCE(cpudata->hw_prefcore); + + return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported"); +} + static ssize_t show_energy_performance_available_preferences( struct cpufreq_policy *policy, char *buf) { @@ -1037,18 +1137,27 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", amd_pstate_prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, NULL, }; @@ -1056,6 +1165,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, NULL, @@ -1063,6 +1173,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1114,6 +1225,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1527,7 +1640,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..87e140e9e6db 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -52,6 +52,9 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @hw_prefcore: check whether HW supports preferred core featue. + * Only when hw_prefcore and early prefcore param are true, + * AMD P-State driver supports preferred core featue. * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value @@ -81,6 +84,7 @@ struct amd_cpudata { u64 freq; bool boost_supported; + bool hw_prefcore; /* EPP feature related attributes*/ s16 epp_policy; From patchwork Fri Oct 13 03:31:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 152284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1641870vqb; Thu, 12 Oct 2023 20:33:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFRnBITUbqKqmWoF5lJYMVymvuvdxMaFcBhd6pd6wNL+cIetkUF95O0PVqKM1Ezel7FY4TH X-Received: by 2002:a17:902:d512:b0:1bf:349f:b85c with SMTP id b18-20020a170902d51200b001bf349fb85cmr28603121plg.1.1697168002189; Thu, 12 Oct 2023 20:33:22 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697168002; cv=pass; d=google.com; s=arc-20160816; b=TxVdn78JWdnOzaq6I1CEB9DiHuv2Bky4+f2kbrUaXOdZMUwr2ewW1TXmmjJVBLu1Zu l2wXcro6hl6PC9M51Sa17bhhgr43WbHzM1AfkZcXg1RlNglZHDbV1lshcw7o08F/YUDl u+4+KD3EAt772RBg2W7n8HqsgYbSpda1dQXYdKve+RLB14NM5bORDMfUaCA9cTKQ8Py7 JeGWRk5H2Tg+JeHcVAU6734gnrUnKOIIR58GIwXZ+V03s1DhDdyPeLV6d6GfVVdd21eS Oy6Gm8AxYjgYrb7J7MMm3S4zB2p5lQ9GjlRaXr+982Sab9ruUvZzkcpDtVYcYqlj2cim OEFg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iEG57ub2uyja18iSbeWFZGvSQXhoZh8gCxORPlmvouA=; fh=hGvksXpWJomenCq+IRP0QZoot/B1Zo6LHbgOlSKBIRE=; b=BaHwNabJf5+QFFK4GqCS1t58BfEV+jMQy2egfF8JV2G1245xDyzgAWnAsPB6s+0YfO gLNZTaCkvaX+Raq8HtY7vKYm6EwLvNUYMRm0sW0A8XkfkhowJ7GN5MZ35aDYOh1kfu9G kke1vyHP1aan3HVmZLRfaykkxJahnUmYAnnK8yk5B1IhwPiv55Si0mjAEo9OnwUNvc9o rz0vafQifWEdpdGnjs07nL0Qu6PWPQsfp5BvTAPaYIpQ0Y0RpW/EEUJxQc7NgjI0/LnR KWmQdBBcPLFCQOWQ09xUlbolzJlF6TyOLMwhXBqtpRKxcHPPEB83jKfTL1z4r5Du2+H0 6FNQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=aLKA2DOv; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from morse.vger.email (morse.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [RESEND PATCH V9 4/7] cpufreq: Add a notification message that the highest perf has changed Date: Fri, 13 Oct 2023 11:31:15 +0800 Message-ID: <20231013033118.3759311-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013033118.3759311-1-li.meng@amd.com> References: <20231013033118.3759311-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042A7:EE_|MN0PR12MB5739:EE_ X-MS-Office365-Filtering-Correlation-Id: cc68bdfa-33ff-4735-6dbb-08dbcb9cff74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: eTr2drDvk+J48en6baqm5XhVLIHIxB2BL8vBlBLVX7G4/fR8sFteZh4i2F8ol6FgUzLYTN8jKjRs9RSMlKWM50BOilIbydPCev8Dz6VNVIN7MVb+LbxJye1T/kNBymBU41YjoASRatkYj1NViqCkZ7A0qz7D6WfvDNM+ueJXMPlKhoZcQnu54o4gdFGFE2523qWOzHjTwQ86doLwTD7+WhQtoNsBYfDjun7nZ5Yf8AKZAlcGa1yttQdnZxK/eNecpaXZACIwyuzminP6MCaRt+TyK3Sqnm7Bv3Jwgnt0NG4/WRKvC7tcdSrg4chtiKiAK515IjwOlQzDrkULmPcZtyaVCPb6rQ/j8ANUFHgtKetZebRQZQ+cUbRGS1Ih9CqomfVq/p4nXdMLgOed4yqtJiGhI/7aiM6QxmB+IsGhv3fJMc0BGO/pOlkxEO9xElKtBYFq1KWjzlVAO7dwAYdbzCiptrBcMzVtj+eYTj8egZw9im1QsEPynDHsQz3wqBzz1f+8lxH+yJ4+n5YsdQkeTzlcccu6jP4hRxPQaKwgyszBdiGDzTkRE8tm/1qvGQ+7y8meldiWnXfcTohQ0O9dHpWSyuA1cYrCiImC23Wfsf3zJz6dBWB3khggsNq6DeihpYHVIeYR13XnwJxUrRQUzKMxQ0H/r9USZQnddxHYH8YNkyHytq9p2U4+WQw7fYQJU50mTn93mQZ+5q6XuHMJeuUNNA7tr6tf+XWR5K0LPNtQsLzg/pH4AHyQx52mIk4Rv8iLBJBymwDrREsN9/7I1dqqJukbdPlD72Kc1gV3Pzw= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(230922051799003)(82310400011)(64100799003)(1800799009)(186009)(451199024)(46966006)(40470700004)(36840700001)(40480700001)(2616005)(2906002)(70586007)(26005)(16526019)(356005)(47076005)(426003)(336012)(82740400003)(83380400001)(81166007)(4326008)(8936002)(8676002)(36860700001)(5660300002)(110136005)(70206006)(7416002)(6636002)(6666004)(7696005)(316002)(1076003)(478600001)(966005)(54906003)(40460700003)(15650500001)(41300700001)(36756003)(86362001)(226483002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 03:32:16.2651 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc68bdfa-33ff-4735-6dbb-08dbcb9cff74 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042A7.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5739 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Thu, 12 Oct 2023 20:33:17 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779609635007361183 X-GMAIL-MSGID: 1779609635007361183 ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#processor-device-notification-values --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 4bc15634d49c..e66b040b0c61 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2717,6 +2717,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 1c5ca92a0555..f62257b2a42f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -235,6 +235,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -263,6 +264,7 @@ static inline bool cpufreq_supports_freq_invariance(void) return false; } static inline void disable_cpufreq(void) { } +static inline void cpufreq_update_highest_perf(unsigned int cpu) { } #endif #ifdef CONFIG_CPU_FREQ_STAT @@ -380,6 +382,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Fri Oct 13 03:31:16 2023 Content-Type: text/plain; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [RESEND PATCH V9 5/7] cpufreq: amd-pstate: Update amd-pstate preferred core ranking dynamically Date: Fri, 13 Oct 2023 11:31:16 +0800 Message-ID: <20231013033118.3759311-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013033118.3759311-1-li.meng@amd.com> References: <20231013033118.3759311-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AB:EE_|SJ2PR12MB8876:EE_ X-MS-Office365-Filtering-Correlation-Id: 6b60f3d3-bcbd-4af5-bf3f-08dbcb9d0279 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6fER7IEqWc56zu08Odc3TN/KEC1XTMvLQ6FTBOUEEtTGSszW+r7x00tbEaaOxzwt6ZGAd67G43RFM2lIwmw+dKY/BoNJ6ss3Dvsvcc1NbAM6eRpokOlDah+D97Rm1Nz357Bvf1uHbhr1mea9x/2xsLmtpfIVKOZMexBS/9t7CZxF7q5uRpOiyY/gsf5aD4+uMVA3pl0WHqSw4UqtlvrDEei0lNDc5wkX8rOBRZ03I9AzBdOZQxI/2GqdJTqZEzBSJ1s7YJaSjIgDQUnvjg0OcLS19HaodKcKXKIiss9gyegY/oVmzFz8Wdhyym6rw/PQfEFLNaoL5iiI/KIvcP8Eu48gFSRArgbWg/C2noys4SFr229d14eIcm6e8+ZDqP3wBBLh67nOSQVEg8BGB7wK5Bt1Mj3YtQP4jbKuICFCpMyVx7zLSxcAeF1YHv+IvnhC9KTr48bwBoO19GRKU/f0fGdhqkPVnqmKEHaKVJtGAx4cKl0kM6pfsUySfG93xB3yQctaVwe5UFdckKH5/7ZRETErNaFQ75Grg9X7mGlAD6CkrUgEFN30nuTB+psy9nAsA58zQVHkNDR4AcA3oWfyY3Tx1nyZSL8yJX9y27AA7FwPX/6iF14MU3Yl1gZvtFb89wFEZbdI2vkl+8D57YFaEcd7Z+NCIAqxXZ0GeU4Z8lOb+HmHYCbzr1Lx+4Z36Ivbo116w2sgz9M4naJF+pNFNB6LvoDv/uTgDTPGJkXEaDNVM2aNwEOuHQqVCj0jBpiWlPVMikU9Dm5cnO71HfgO/w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(396003)(346002)(136003)(39860400002)(376002)(230922051799003)(186009)(1800799009)(82310400011)(64100799003)(451199024)(36840700001)(46966006)(40470700004)(7696005)(8936002)(8676002)(478600001)(5660300002)(41300700001)(26005)(336012)(1076003)(426003)(16526019)(2616005)(4326008)(70586007)(6636002)(316002)(54906003)(70206006)(110136005)(15650500001)(40460700003)(47076005)(36860700001)(66899024)(83380400001)(82740400003)(2906002)(40480700001)(81166007)(356005)(7416002)(36756003)(86362001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 03:32:21.3331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6b60f3d3-bcbd-4af5-bf3f-08dbcb9d0279 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8876 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 20:32:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779609672419219566 X-GMAIL-MSGID: 1779609672419219566 Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 49 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 6 +++++ 2 files changed, 55 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6aae383990f1..3b054e3acba1 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -313,6 +313,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -334,6 +335,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -763,6 +765,37 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) } } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + int ret; + + if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore)) + return; + + ret = amd_pstate_get_highest_perf(cpu, &cur_high); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + prev_high = READ_ONCE(cpudata->prefcore_ranking); + + if (prev_high != cur_high) { + int prio; + + WRITE_ONCE(cpudata->prefcore_ranking, cur_high); + + /* The maximum value of highest perf is 255 */ + prio = (int)(cur_high & 0xff); + sched_set_itmt_core_prio(prio, cpu); + } + + cpufreq_cpu_put(policy); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -934,6 +967,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->prefcore_ranking); + + return sysfs_emit(buf, "%u\n", perf); +} + static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, char *buf) { @@ -1147,6 +1191,7 @@ cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); @@ -1157,6 +1202,7 @@ static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, NULL, }; @@ -1165,6 +1211,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, @@ -1505,6 +1552,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1519,6 +1567,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 87e140e9e6db..426822612373 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -39,11 +39,16 @@ struct amd_aperf_mperf { * @cppc_req_cached: cached performance request hints * @highest_perf: the maximum performance an individual processor may reach, * assuming ideal conditions + * For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the fixed value as the highest_perf. * @nominal_perf: the maximum sustained performance level of the processor, * assuming ideal operating conditions * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power * savings are achieved * @lowest_perf: the absolute lowest performance level of the processor + * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher + * priority. * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf @@ -73,6 +78,7 @@ struct amd_cpudata { u32 nominal_perf; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [RESEND PATCH V9 6/7] Documentation: amd-pstate: introduce amd-pstate preferred core Date: Fri, 13 Oct 2023 11:31:17 +0800 Message-ID: <20231013033118.3759311-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013033118.3759311-1-li.meng@amd.com> References: <20231013033118.3759311-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000042AA:EE_|IA1PR12MB6211:EE_ X-MS-Office365-Filtering-Correlation-Id: 22dd36ee-65e2-4c52-4ac5-08dbcb9d054d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ZvwHaaVnvP8lSk2R4DjRTCKV/BXH0i2/CXzF4wJX5yjsbdZKYN+ysYdUBolnpys8qGnPKo+iCaEEoGV0wVj4zOveBB43SEjA+rDn4M8iNZd5we+FWjtOT5LPkviKMdDB8mbGMmANRs8p6ihNCF7OzaiETo8fJnaT6OKukpBAsE23nnYa+LqIFt6eIBcnr3CB3+a9DP/7lKWeqEpoAClWX0z9mH7S2Y4wOIihFYvwrDp/0X2JFpn0s0/K6uRC5iOonCb3xZgg0BFgoP4UWsU21jSfp7eMo5ndvzhGNOPfUsocci/vUJiQWF0Ri5Z0I6xLbgIwxnCcQAsBHnbjF1XiepDh9Vx804NCru24StnGqvYxt1xY2kPA0ZdmDHxR2gJ5dyAoQF1yRsTJ3t4PWDwNOXKSNhF+XgNbqv3ItK9Wh5l0GV1YIwRjzM/OmPVUKR3vjId7MoKbTngI2K2iFw/Q2Xg+zSDMbAmP3LbnB0eoTYq/k0/7rkxl+ppPua2l+9AYH0CME8HcTM0NOUVzR2Q5yA+TD94EwSzdu7u/jAw0Alm5poVp9WMaL7/qR1NdSgchg6DeiTm8wWDBdnKmo9lioGjsKmjAXYT0ctSU9LXJu3Rd76f7FQLQ+iu3jAATqFwfTDbSC7ZoUll2vFD9aCMGmzpwmdhx2kT2gEviKY15IC/+jd44+t8m3UbWu12LoZan9LNtVhgv2KbZ/yIAl08iIQMiIXJqv2mRwR6YTx/Bgz6olVnxx+Yx591SoXltPMV0mxnjcY4gxaywjUbQIBlWRQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(376002)(346002)(136003)(396003)(230922051799003)(64100799003)(451199024)(186009)(82310400011)(1800799009)(36840700001)(46966006)(40470700004)(83380400001)(7416002)(36860700001)(2906002)(40460700003)(47076005)(36756003)(86362001)(40480700001)(82740400003)(81166007)(356005)(6636002)(70586007)(110136005)(54906003)(41300700001)(1076003)(2616005)(26005)(16526019)(6666004)(316002)(70206006)(7696005)(478600001)(5660300002)(336012)(426003)(4326008)(8936002)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Oct 2023 03:32:26.0750 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 22dd36ee-65e2-4c52-4ac5-08dbcb9d054d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000042AA.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6211 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 20:33:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779609672890576736 X-GMAIL-MSGID: 1779609672890576736 Introduce amd-pstate preferred core. check preferred core state set by the kernel parameter: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Tested-by: Oleksandr Natalenko Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 59 ++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..0b832ff529db 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -300,8 +300,8 @@ platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -AMD Pstate Driver Operation Modes -================================= +``amd-pstate`` Driver Operation Modes +====================================== ``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, non-autonomous (passive) mode and guided autonomous (guided) mode. @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +``amd-pstate`` Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``amd-pstate`` preferred core enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the ``amd-pstate`` driver. The ``amd-pstate`` +driver will also determine whether or not ``amd-pstate`` preferred core is +supported by the platform. + +``amd-pstate`` driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When ``amd-pstate`` +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +``amd-pstate`` Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``amd-pstate`` peferred core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``amd-pstate`` preferred core. + +``amd_prefcore=disable`` + +For systems that support ``amd-pstate`` preferred core, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,19 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the ``amd-pstate`` preferred core. + + "disabled" + Disable the ``amd-pstate`` preferred core + + + This attribute is read-only to check the state of preferred core set + by the kernel parameter. + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Fri Oct 13 03:31:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 152289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1642090vqb; Thu, 12 Oct 2023 20:33:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHTICzV3Z4jR0EsTd7CidtQEKXh2svHUnX2R3v+xGzzVUrXY9PivoGAGu/oH8rbAkdqT9Qj X-Received: by 2002:a17:90a:4d88:b0:263:730b:f568 with SMTP id m8-20020a17090a4d8800b00263730bf568mr23903929pjh.3.1697168039257; Thu, 12 Oct 2023 20:33:59 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697168039; cv=pass; d=google.com; s=arc-20160816; b=BOqxzBNQkotpXHnStl/PL6EDhg/LolZlrNZ1EB39c+Pir4Xfnr65i3skhf7u/jXZmv SEHhNozeVn0Ha8GNdbOXN2+kBkEJHJ6Qs7I08osWosTINlClvw0NNnMdVJqNAAQkPGKu NQh3g+BRER/hfUCT2NYAr++MdTli/od+B5kKSSIWzDkjhBji+FWMi3FUxdEx3JeH7LZP lr6KWd/ZEb1Pzo7qJKEuqCwRLAltOKO6ksB7liIGjPUu4kcUab9ycpH9xelea0v8vhOQ 3qYhZqtz5fwF+Ow63H4Q8RlCMkjBGNcz0w3BMLOAnY0l0k5lAKTGMktclnGH6OjxRknh cPXQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3BATVT8xDKQmxK5ddKWQeikq5vTddHGyEfuh2meRohc=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=RT/SAe6fTbvof/djXS6E+gTShVvnS2eDkhIYrYscBlzWPEkASeMEcx/4gTB2PVLCFV 3hDYc+0hEGuWgY5gOrY/9YsCxwkhqIhKIZu3oEC+BY3KxZ1y+KDGjHOOOF8HrWvpCKEQ aQtd3KTUy1l8Ft/5X7lGiwi8uEQfCzcMUiI7WEUd7+JIQf99CWcqS5h/bMftIMtIy6yY bPpyG8LhmPEC5MJvT0/0cWNjuickr39xGHmlDKEvG8WvjLH10Dr9Q2DXYHFy6g+KF3+R Nsb/GoIBaPvic9K8vNTHPwhPqfjC0x33Ti+dBK3ek3PsJ7jqsczpkDpe+BeVYT4xp64O CRcQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=SWppC7lT; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Default enabled on platforms supporting amd-pstate preferred core. Disable amd-pstate preferred core with "amd_prefcore=disable" added to the kernel command line. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Tested-by: Oleksandr Natalenko --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 0a1731a0f0ef..e35b795aa8aa 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + disable + Disable amd-pstate preferred core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,