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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id f32-20020a05622a1a2000b004199bf94c56si554857qtb.411.2023.10.12.19.22.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 19:22:56 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=P00d9J93; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 46E243856944 for ; Fri, 13 Oct 2023 02:22:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id 53E1A3858C5E for ; Fri, 13 Oct 2023 02:22:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 53E1A3858C5E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697163749; x=1728699749; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=4TEvze9GyYvAJJ9OL9tnhuYtQEFnk+N4Bq+viy9rbOs=; b=P00d9J93l/OHKUE6b8Bm/D+w9PCA/XLsARkE8WyNhO5KzLlk/IS+AJMN WtBEhTXlcuWohdRjkWqi5anxB8Z686kCQ28Y7JqjTfOtzfij4zVTR4cSy hVYPKVHjIewOaQ5F/XZAWQ5l4wPSw7LLauO5XJqsob/O3w3RyIVRQmM8N 0Q6diIaquFZBqjkxjp6tk3WlzsW0nhGI4fGBsfH7TB4Kdy/80G2uOzrth hQl+vn2F2j1W3MZZ85QgVbtru1VsC7ueQDdsB+FeRn///54LptByMXomp E+OWA85Bb6XWCnF/SbKpydP0yDoOBLt2K2RsItpEmqLSshFfEA1N124ac g==; X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="365344919" X-IronPort-AV: E=Sophos;i="6.03,219,1694761200"; d="scan'208";a="365344919" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Oct 2023 19:22:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10861"; a="845243820" X-IronPort-AV: E=Sophos;i="6.03,219,1694761200"; d="scan'208";a="845243820" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by FMSMGA003.fm.intel.com with ESMTP; 12 Oct 2023 19:22:26 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id C225A1005663; Fri, 13 Oct 2023 10:22:25 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Leverage stdint-gcc.h for RVV test cases Date: Fri, 13 Oct 2023 10:22:24 +0800 Message-Id: <20231013022224.3837020-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779605203604036973 X-GMAIL-MSGID: 1779605203604036973 From: Pan Li Leverage stdint-gcc.h for the int64_t types instead of typedef. Or we may have conflict with stdint-gcc.h in somewhere else. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c: Include stdint-gcc.h for int types. * gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c: Ditto. * gcc.target/riscv/rvv/autovec/unop/test-math.h: Remove int64_t typedef. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c | 1 + .../gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c | 1 + gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h | 2 -- 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c index 2d90d232ba1..4bf125f8cc8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-0.c @@ -2,6 +2,7 @@ /* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ /* { dg-final { check-function-bodies "**" "" } } */ +#include #include "test-math.h" /* diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c index 6b69f5568e9..409175a8dff 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c @@ -1,6 +1,7 @@ /* { dg-do run { target { riscv_v && rv64 } } } */ /* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ +#include #include "test-math.h" #define ARRAY_SIZE 128 diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h index 3867bc50a14..a1c9d55bd48 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/test-math.h @@ -68,8 +68,6 @@ #define FRM_RMM 4 #define FRM_DYN 7 -typedef long long int64_t; - static inline void set_rm (unsigned rm) {