From patchwork Mon Nov 7 07:00:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 16266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1884049wru; Sun, 6 Nov 2022 23:09:50 -0800 (PST) X-Google-Smtp-Source: AMsMyM6pha6POuxH4ndi/J7rb6LWqRmkzLmXMbnof3kDgOOY7A5E/xP69xMLa5rgqN9/LHCfie9m X-Received: by 2002:a17:90a:dc10:b0:213:90f3:27c9 with SMTP id i16-20020a17090adc1000b0021390f327c9mr50011195pjv.240.1667804990678; Sun, 06 Nov 2022 23:09:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667804990; cv=none; d=google.com; s=arc-20160816; b=BF1l3EzZtYasD9lXw6Ea6t9yPq/wc4JTABKM+oGvKRm2I53TsN55zRo42C+HjCSdV0 OJe1qQBnFrk/E+ENasnYDS6J0C+m7Vhc3WfZ/7XC6PRbEETWwESnr8ZpxA7V+vaLEmPE wP28ffLiRI6znh+yvlNBMqnQssXWnwOrTjW2Fv6ErEtN7tXNj3L6+KvU0ieQr4cPcYz/ DfOBzcRUe9F0ZlcUFlrekLQgy9TF7XVMNHlFwDF9XT9RP94fABZ0/ec6GWRfd2R8kWhs uHemCxgAAwWbpq0/h8/ja0eoQu3J2B1nNsu+nNyS/3yAhzJQMnvlt9fS1cr7o7PAyr6R mZ0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=N/AKRvo7yxdUrf8yNI8oDO4NZkY80ljqByskoTAYKuM=; b=xN8fU0Y88NoLnUMFd+Tg3/gNdzGvvFsL7cBfu2UR8hd506c+govaX3DwnZVTK5xmDf sfReaFixA+5+BQuw8wY+y/wxr5CnrfMqGqi9ALKS6GcsqEJA6I/E3tTyFFEK24QmTFw8 96lNOkQ5k+N6DwfbWWrLj4efr5H6SZnWGa39UsKp7/YwrtMHwgzEaSdRq25MohyGPKsK GncsJ2HecDj6geMjx9qAhYwPAn2SVnqE1Wj/Ra0qKwVd0o1LPhAlCMvR0Zv1xih2gND9 OCiBsZkXxzQILImwKQi+T9LSzgzRwFbl+eRFVKIOT8J42xJH+wJmp6Y27JtrEI6qNz3G uUVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ehhb5q22; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id a3-20020a170902ecc300b0017bcea4e6b6si10889382plh.234.2022.11.06.23.09.37; Sun, 06 Nov 2022 23:09:50 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ehhb5q22; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231272AbiKGHAo (ORCPT + 99 others); Mon, 7 Nov 2022 02:00:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231149AbiKGHAh (ORCPT ); Mon, 7 Nov 2022 02:00:37 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 74D7711C2E; Sun, 6 Nov 2022 23:00:35 -0800 (PST) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2A770GC1030650; Mon, 7 Nov 2022 01:00:16 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1667804416; bh=N/AKRvo7yxdUrf8yNI8oDO4NZkY80ljqByskoTAYKuM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ehhb5q22erh9E/+qDo2X68Z9uP/QORY1ee3+mF74mZKm9BwzZFaTDrxRcFnQTC9OG jWgYMGl0+uFNNYXe8TBrJ9Uny2qqKukLLLAgUvfg1bFY1RfHZDo6sLms4yw/A/ibeK IMCRi2KdRNeTghqKmr7SLWNav+/smR3zwJHm9kLw= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2A770G4m082557 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 7 Nov 2022 01:00:16 -0600 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6; Mon, 7 Nov 2022 01:00:16 -0600 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.6 via Frontend Transport; Mon, 7 Nov 2022 01:00:16 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A770F8K047555; Mon, 7 Nov 2022 01:00:15 -0600 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v8 1/2] arm64: dts: ti: k3-j721e-main: Add dts nodes for EHRPWMs Date: Mon, 7 Nov 2022 12:30:08 +0530 Message-ID: <20221107070009.11500-2-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221107070009.11500-1-r-ravikumar@ti.com> References: <20221107070009.11500-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748820285708570997?= X-GMAIL-MSGID: =?utf-8?q?1748820285708570997?= From: Vijay Pothukuchi Add dts nodes for 6 EHRPWM instances on SoC. Disable EHRPWM nodes in the dtsi files and only enable the ones that are actually pinned out on a given board. Signed-off-by: Vijay Pothukuchi Signed-off-by: Rahul T R --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 68 ++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 5c4a0e28cde5..bc3146e24816 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -66,7 +66,73 @@ usb_serdes_mux: mux-controller@4000 { #mux-control-cells = <1>; mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */ - }; + }; + + ehrpwm_tbclk: clock-controller@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + }; + }; + + main_ehrpwm0: pwm@3000000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3000000 0x00 0x100>; + power-domains = <&k3_pds 83 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 0>, <&k3_clks 83 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm1: pwm@3010000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3010000 0x00 0x100>; + power-domains = <&k3_pds 84 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 1>, <&k3_clks 84 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm2: pwm@3020000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3020000 0x00 0x100>; + power-domains = <&k3_pds 85 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 2>, <&k3_clks 85 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm3: pwm@3030000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3030000 0x00 0x100>; + power-domains = <&k3_pds 86 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 3>, <&k3_clks 86 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm4: pwm@3040000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3040000 0x00 0x100>; + power-domains = <&k3_pds 87 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 4>, <&k3_clks 87 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; + }; + + main_ehrpwm5: pwm@3050000 { + compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; + #pwm-cells = <3>; + reg = <0x00 0x3050000 0x00 0x100>; + power-domains = <&k3_pds 88 TI_SCI_PD_EXCLUSIVE>; + clocks = <&ehrpwm_tbclk 5>, <&k3_clks 88 0>; + clock-names = "tbclk", "fck"; + status = "disabled"; }; gic500: interrupt-controller@1800000 { From patchwork Mon Nov 7 07:00:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul T R X-Patchwork-Id: 16267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1884143wru; Sun, 6 Nov 2022 23:10:03 -0800 (PST) X-Google-Smtp-Source: AMsMyM7r+USq1TZqnjLX9RlKohQj/LfqJjsPu89Nn3T3y8mZHs3gGLsxLRFBU0fv+/sju/ZhINnw X-Received: by 2002:a63:ec15:0:b0:46e:e211:5435 with SMTP id j21-20020a63ec15000000b0046ee2115435mr41406932pgh.526.1667805003366; Sun, 06 Nov 2022 23:10:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667805003; cv=none; d=google.com; s=arc-20160816; b=N57iVwCNcTyY5k+CoqjJ9BFH/W9zHBeKcT7nM25MOMYzzfyO/vINVzDA49kWOzUWMg /TYVPbzv8oTApM5zetiEh7eWW3lIUMHNpXNVQIQTVEsurI59L/P6N0tngfpQq/IONSdN SRR4WlyjoQD2hnrEqisElZO4oUhP6uvUCHrx9JmFXN04fRz8POgXlHzXelKN18/DkRp5 WmbwwEuRnS3BIphcp0+kvRyluz0FxJ1E/JIHN7OZEjuYdEXz7+LvnzjDNvV7i1O8Obai FVv8NFHMJ0z1lygzmne9tGAF/0cG6WY9HSA5D9eMtGUbPYOLWh59O63FjLqvJjijj6Ak hcvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tAAab/KAtcVE7PGD4xw17lbMGtEahjjN8h1D5UjXh0Y=; b=t0eU2j9cVM7snz+pbtbxmJovkHVS/VvgLbML2MTMTF9VK5v47i+L0UzH6DRuEbM3NX C4E4GZWY/TXySAC4G+aQaCMU0mzIehSOItIYQ94MtFH10N8Rj4KAvbO7eK6LvhiqKHFo Ugm7vzE9N0VOJuDcstGJOQxKNO3ydNLajiblbsRXYAdR29wzOmFJlZSGWah+au8jTcPA CvMNPp48iuTFiZ5UaKEigtylYtaTGjzJfQ1x+va6OrvTclYEIIDWmoiHvBRBpxxbNAwq rwWUwRtpPXuO4iCtrY4WNSSgG8+GofqG3APbADzDX9L2dHdRj6RJGWq4YhVN4ZjRXD52 5XvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=DpGqJBBf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from out1.vger.email (out1.vger.email. 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Mon, 7 Nov 2022 01:00:18 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2A770HiD047636; Mon, 7 Nov 2022 01:00:18 -0600 From: Rahul T R To: CC: , , , , , , , , Subject: [PATCH v8 2/2] arm64: dts: ti: k3-j721e-sk: Add pinmux for RPi Header Date: Mon, 7 Nov 2022 12:30:09 +0530 Message-ID: <20221107070009.11500-3-r-ravikumar@ti.com> X-Mailer: git-send-email 2.38.0 In-Reply-To: <20221107070009.11500-1-r-ravikumar@ti.com> References: <20221107070009.11500-1-r-ravikumar@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Spam-Status: No, score=-4.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748820299602988941?= X-GMAIL-MSGID: =?utf-8?q?1748820299602988941?= Add pinmux required to bring out i2c5 and gpios on 40 pin RPi header on sk board Signed-off-by: Sinthu Raja Signed-off-by: Rahul T R --- Notes: Only GPIO and I2C muxing is enabled, as per the comments and discussion in v4 https://lore.kernel.org/all/20220620144322.x54zitvhjreiy3ey@uda0490373/ arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 59 ++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 78aa4aa4de57..4640d280c85c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -400,6 +400,47 @@ ekey_reset_pins_default: ekey-reset-pns-pins-default { J721E_IOPAD(0x124, PIN_INPUT, 7) /* (Y24) PRG0_PRU1_GPO9.GPIO0_72 */ >; }; + + main_i2c5_pins_default: main-i2c5-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x150, PIN_INPUT_PULLUP, 2) /* (Y26) PRG0_MDIO0_MDIO.I2C5_SCL */ + J721E_IOPAD(0x154, PIN_INPUT_PULLUP, 2) /* (AA27) PRG0_MDIO0_MDC.I2C5_SDA */ + >; + }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x01C, PIN_INPUT, 7) /* (AD22) PRG1_PRU0_GPO6.GPIO0_7 */ + J721E_IOPAD(0x120, PIN_INPUT, 7) /* (AA28) PRG0_PRU1_GPO8.GPIO0_71 */ + J721E_IOPAD(0x14C, PIN_INPUT, 7) /* (AA29) PRG0_PRU1_GPO19.GPIO0_82 */ + J721E_IOPAD(0x02C, PIN_INPUT, 7) /* (AD21) PRG1_PRU0_GPO10.GPIO0_11 */ + J721E_IOPAD(0x198, PIN_INPUT, 7) /* (V25) RGMII6_TD1.GPIO0_101 */ + J721E_IOPAD(0x1B0, PIN_INPUT, 7) /* (W24) RGMII6_RD1.GPIO0_107 */ + J721E_IOPAD(0x1A0, PIN_INPUT, 7) /* (W29) RGMII6_TXC.GPIO0_103 */ + J721E_IOPAD(0x008, PIN_INPUT, 7) /* (AG22) PRG1_PRU0_GPO1.GPIO0_2 */ + J721E_IOPAD(0x1D0, PIN_INPUT, 7) /* (AA3) SPI0_D1.GPIO0_115 */ + J721E_IOPAD(0x11C, PIN_INPUT, 7) /* (AA24) PRG0_PRU1_GPO7.GPIO0_70 */ + J721E_IOPAD(0x148, PIN_INPUT, 7) /* (AA26) PRG0_PRU1_GPO18.GPIO0_81 */ + J721E_IOPAD(0x004, PIN_INPUT, 7) /* (AC23) PRG1_PRU0_GPO0.GPIO0_1 */ + J721E_IOPAD(0x014, PIN_INPUT, 7) /* (AH23) PRG1_PRU0_GPO4.GPIO0_5 */ + J721E_IOPAD(0x020, PIN_INPUT, 7) /* (AE20) PRG1_PRU0_GPO7.GPIO0_8 */ + J721E_IOPAD(0x19C, PIN_INPUT, 7) /* (W27) RGMII6_TD0.GPIO0_102 */ + J721E_IOPAD(0x1B4, PIN_INPUT, 7) /* (W25) RGMII6_RD0.GPIO0_108 */ + J721E_IOPAD(0x188, PIN_INPUT, 7) /* (Y28) RGMII6_TX_CTL.GPIO0_97 */ + J721E_IOPAD(0x00C, PIN_INPUT, 7) /* (AF22) PRG1_PRU0_GPO2.GPIO0_3 */ + J721E_IOPAD(0x010, PIN_INPUT, 7) /* (AJ23) PRG1_PRU0_GPO3.GPIO0_4 */ + J721E_IOPAD(0x178, PIN_INPUT, 7) /* (U27) RGMII5_RD3.GPIO0_93 */ + J721E_IOPAD(0x17C, PIN_INPUT, 7) /* (U24) RGMII5_RD2.GPIO0_94 */ + J721E_IOPAD(0x190, PIN_INPUT, 7) /* (W23) RGMII6_TD3.GPIO0_99 */ + J721E_IOPAD(0x18C, PIN_INPUT, 7) /* (V23) RGMII6_RX_CTL.GPIO0_98 */ + >; + }; + + rpi_header_gpio1_pins_default: rpi-header-gpio1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x234, PIN_INPUT, 7) /* (U3) EXT_REFCLK1.GPIO1_12 */ + >; + }; }; &wkup_pmx0 { @@ -600,6 +641,24 @@ i2c@1 { }; }; +&main_i2c5 { + /* Brought out on RPi Header */ + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; +}; + +&main_gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; +}; + +&main_gpio1 { + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio1_pins_default>; +}; + &main_gpio2 { status = "disabled"; };