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[78.62.135.63]) by smtp.gmail.com with ESMTPSA id br34-20020a056512402200b005068e7a2e7dsm2557470lfb.77.2023.10.12.09.21.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 09:21:07 -0700 (PDT) From: Siarhei Volkau To: Thomas Bogendoerfer , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, Siarhei Volkau Cc: Paul Cercueil Subject: [PATCH] MIPS: Take in account load hazards for HI/LO restoring Date: Thu, 12 Oct 2023 19:20:27 +0300 Message-ID: <20231012162027.3411684-1-lis8215@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 12 Oct 2023 09:21:28 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779567367258928023 X-GMAIL-MSGID: 1779567367258928023 MIPS CPUs usually have 1 to 4 cycles load hazards, thus doing load and right after move to HI/LO will usually stall the pipeline for significant amount of time. Let's take it into account and separate loads and mthi/lo in instruction sequence. The patch uses t6 and t7 registers as temporaries in addition to t8. The patch tries to deal with SmartMIPS, but I know little about and haven't tested it. Signed-off-by: Siarhei Volkau --- arch/mips/include/asm/stackframe.h | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a8705aef47e1..3821d91b00fd 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -308,17 +308,11 @@ jal octeon_mult_restore #endif #ifdef CONFIG_CPU_HAS_SMARTMIPS - LONG_L $24, PT_ACX(sp) - mtlhx $24 - LONG_L $24, PT_HI(sp) - mtlhx $24 - LONG_L $24, PT_LO(sp) - mtlhx $24 -#elif !defined(CONFIG_CPU_MIPSR6) + LONG_L $14, PT_ACX(sp) +#endif +#if defined(CONFIG_CPU_HAS_SMARTMIPS) || !defined(CONFIG_CPU_MIPSR6) LONG_L $24, PT_LO(sp) - mtlo $24 - LONG_L $24, PT_HI(sp) - mthi $24 + LONG_L $15, PT_HI(sp) #endif #ifdef CONFIG_32BIT cfi_ld $8, PT_R8, \docfi @@ -327,6 +321,14 @@ cfi_ld $10, PT_R10, \docfi cfi_ld $11, PT_R11, \docfi cfi_ld $12, PT_R12, \docfi +#ifdef CONFIG_CPU_HAS_SMARTMIPS + mtlhx $14 + mtlhx $15 + mtlhx $24 +#elif !defined(CONFIG_CPU_MIPSR6) + mtlo $24 + mthi $15 +#endif cfi_ld $13, PT_R13, \docfi cfi_ld $14, PT_R14, \docfi cfi_ld $15, PT_R15, \docfi