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[2620:137:e000::1:20]) by mx.google.com with ESMTP id e19-20020a170902ed9300b0017535568d5dsi8708112plj.256.2022.11.06.21.33.48; Sun, 06 Nov 2022 21:34:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sholland.org header.s=fm1 header.b=ZWOT2BWp; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=dxDhSj3j; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sholland.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230350AbiKGFcx (ORCPT + 99 others); Mon, 7 Nov 2022 00:32:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51832 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230309AbiKGFcv (ORCPT ); Mon, 7 Nov 2022 00:32:51 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CB3FFADD; Sun, 6 Nov 2022 21:32:50 -0800 (PST) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.nyi.internal (Postfix) with ESMTP id C5E6E5C00A0; Mon, 7 Nov 2022 00:32:49 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Mon, 07 Nov 2022 00:32:49 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1667799169; x=1667885569; bh=XC XLV1Fn2JMkCGp5d8/IdzhEV6t432NGJWbrn/bcneo=; b=ZWOT2BWpAOKgtXDisF 8P+Da+UnWG7+rg6Ktziof8zNYah8+HxgL1e+R6Bs1WmfxR7XSs+BJAFgx3QsE1jn 065r2pbTCQZYvmd5B2t2sShojDA8fs2c3zoalWJdlUMkmyN06j2Y6mbwuhK5G/++ 8vOUboUNIDwXTF1ZlA+dQ8nuaQZPxZboU8w99NDf+pNmH0sDG6G4C1dIAmfuU2mF Nu8/PYllz8ZTu1HXaGb1BsPab1Unj90PVKJKKh3W485b6dgyCQemfQ5wZ2ss0hzF 9w4zwPhlEUE3+U07DsZsh6CqfAX3+3UyMMcDBAMfbYPQWQrhNnerLZutKWiKrHxY vxwA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1667799169; x=1667885569; bh=XCXLV1Fn2JMkC Gp5d8/IdzhEV6t432NGJWbrn/bcneo=; b=dxDhSj3jTNQTQ2dirHiOqXjHOeoUa XZoQ8QtOLmtWw47eC3g1tVoaCTTsiryeaa41Y0qyNQhYNyKHQKRsvhH6Vda04yl8 6HhaO6gQYI1YLXh1NJy4a3FkdWc7SJNOTyBFhPqc4VACDCHj5K/PVdd6LWpigN2I ESQh6LCwcs9PCCoraK7mglZPjJpKCV/76W+Hlt4Pabka1x+m77dltrksS/aqHbFD C0qX0gWlLOCg2/FXJr+Uu4NcV3Oxiucfqlhv7VabLp8BD6OAVndlW9i8gOhV1ybg 0e+9zAndJ4DC0KsQcIiNIZYlct5nQDyQP/x+6SBIns7lr/jETR3E5LK+g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrvdejgdekgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpefghfevhffgheejhefgkeehueffgeehffejgeehueduueeffffhhfeu iefhueffhfenucffohhmrghinhepuggvvhhitggvthhrvggvrdhorhhgnecuvehluhhsth gvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomhepshgrmhhuvghlsehshhho lhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 7 Nov 2022 00:32:48 -0500 (EST) From: Samuel Holland To: Pavel Machek , linux-leds@vger.kernel.org, Chen-Yu Tsai , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland , Maxime Ripard , Rob Herring Subject: [PATCH v6 1/5] dt-bindings: leds: Add Allwinner A100 LED controller Date: Sun, 6 Nov 2022 23:32:42 -0600 Message-Id: <20221107053247.1180-2-samuel@sholland.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221107053247.1180-1-samuel@sholland.org> References: <20221107053247.1180-1-samuel@sholland.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748814261461839749?= X-GMAIL-MSGID: =?utf-8?q?1748814261461839749?= The Allwinner A100, R329, and D1 SoCs contain an LED controller designed to drive a series of RGB LED pixels. It supports PIO and DMA transfers, and has configurable timing and pixel format. All three implementations appear to be identical, so use the oldest as the fallback compatible. Acked-by: Maxime Ripard Reviewed-by: Rob Herring Signed-off-by: Samuel Holland --- (no changes since v5) Changes in v5: - A100 contains the original implementation, so use that as the base compatible string, and rename the binding to match - Add "unevaluatedProperties: false" to the child multi-led binding Changes in v4: - Use "default" instead of "maxItems" for timing properties Changes in v3: - Removed quotes from enumeration values - Added vendor prefix to timing/format properties - Renamed "format" property to "pixel-format" for clarity - Dropped "vled-supply" as it is unrelated to the controller hardware Changes in v2: - Fixed typo leading to duplicate t1h-ns property - Removed "items" layer in definition of dmas/dma-names - Replaced uint32 type reference with maxItems in timing properties .../leds/allwinner,sun50i-a100-ledc.yaml | 139 ++++++++++++++++++ 1 file changed, 139 insertions(+) create mode 100644 Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml diff --git a/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml new file mode 100644 index 000000000000..fc8ecf6f91e6 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/allwinner,sun50i-a100-ledc.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/allwinner,sun50i-a100-ledc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner A100 LED Controller Bindings + +maintainers: + - Samuel Holland + +description: + The LED controller found in Allwinner sunxi SoCs uses a one-wire serial + interface to drive up to 1024 RGB LEDs. + +properties: + compatible: + oneOf: + - const: allwinner,sun50i-a100-ledc + - items: + - enum: + - allwinner,sun20i-d1-ledc + - allwinner,sun50i-r329-ledc + - const: allwinner,sun50i-a100-ledc + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Bus clock + - description: Module clock + + clock-names: + items: + - const: bus + - const: mod + + resets: + maxItems: 1 + + dmas: + maxItems: 1 + description: TX DMA channel + + dma-names: + const: tx + + allwinner,pixel-format: + description: Pixel format (subpixel transmission order), default is "grb" + enum: + - bgr + - brg + - gbr + - grb + - rbg + - rgb + + allwinner,t0h-ns: + default: 336 + description: Length of high pulse when transmitting a "0" bit + + allwinner,t0l-ns: + default: 840 + description: Length of low pulse when transmitting a "0" bit + + allwinner,t1h-ns: + default: 882 + description: Length of high pulse when transmitting a "1" bit + + allwinner,t1l-ns: + default: 294 + description: Length of low pulse when transmitting a "1" bit + + allwinner,treset-ns: + default: 300000 + description: Minimum delay between transmission frames + +patternProperties: + "^multi-led@[0-9a-f]+$": + type: object + $ref: leds-class-multicolor.yaml# + unevaluatedProperties: false + properties: + reg: + minimum: 0 + maximum: 1023 + description: Index of the LED in the series (must be contiguous) + + required: + - reg + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include + #include + + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-a100-ledc"; + reg = <0x2008000 0x400>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu 12>, <&ccu 34>; + clock-names = "bus", "mod"; + resets = <&ccu 12>; + dmas = <&dma 42>; + dma-names = "tx"; + #address-cells = <1>; + #size-cells = <0>; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_INDICATOR; + }; + }; + +... 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id v69-20020a638948000000b00434d8692854si8732942pgd.541.2022.11.06.21.34.48; Sun, 06 Nov 2022 21:35:01 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sholland.org header.s=fm1 header.b=mT8YtReJ; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=GBP9yFvX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sholland.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230464AbiKGFdB (ORCPT + 99 others); Mon, 7 Nov 2022 00:33:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230342AbiKGFcx (ORCPT ); Mon, 7 Nov 2022 00:32:53 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C2FBDED9; Sun, 6 Nov 2022 21:32:51 -0800 (PST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id C75835C009A; Mon, 7 Nov 2022 00:32:50 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Mon, 07 Nov 2022 00:32:50 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm1; t=1667799170; x= 1667885570; bh=RL9ANq1RleS8NLm3MosMiWmbO3sk2Nh2RvN+mH4yZ6k=; b=m T8YtReJWoxf5sahWXBeFfRMuuorSx75lQFw09ke5wbRuUekMigOBc71ya9pKuhHT vNP+plMGqkbQtU0t2FopqHrJ3haOUqvQ9YBaw1ZfIAUYtSe3jF5WRe7yi7o/zhWS 3LwC3O/NOjY4LknlDulrMgKhlKyRQjNLZ278Vrpx0I7wf6nESYlDnhMoiKgIyz8t dpdrbCZk46E6xBWb1LFJMNoz8gqz1GDKt7GwM4KkpcZ17TdmzpAEZwbhBP/4h71K P7G9YOKZXgjw2o6eTDxNyGqENZcUkjOwgIJ38Y1qejqLRvqJpBZfwg1peuUfzOLD TIw0kU/V3GJUJzdZvqKEw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm3; t=1667799170; x= 1667885570; bh=RL9ANq1RleS8NLm3MosMiWmbO3sk2Nh2RvN+mH4yZ6k=; b=G BP9yFvXBxbPSj14n3Mn3cTluAXgwSvZ0X4vJUs0cukmNOjd4vjhznZvAL7nuOmGp rsN24SgPUu73eVuAnBKJbG7N2D9LnLGg+t+roQ2GBjLVZQOUYfeRWDG2lcwFLSBg 7iArsyPEimrI7SdvtH40UxqXhn+L93Ug7RQw0MAgoU8RNGh3NZjcqr6M39BodurG RuVM1Nh1yOkXBQIAnLSDAk6AOLJubfk8foEOpQbucapuqhyvhGv6m/RqrajCtJA0 1Jf8owi66gbqYIc/dod7dF2KAO5VJDJdd/0vXbGASGxxAJdWuqC9h8dRRzrSDIwS LWQ7Ne1T83pwcYblGHxCw== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrvdejgdekgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfgggtgfesthekredtredtjeenucfhrhhomhepufgrmhhu vghlucfjohhllhgrnhguuceoshgrmhhuvghlsehshhholhhlrghnugdrohhrgheqnecugg ftrfgrthhtvghrnhepfeeuveeufeefleehlefhleeglefggfeikeffveetfeevjeeuieet uefgfeeiheelnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrh homhepshgrmhhuvghlsehshhholhhlrghnugdrohhrgh X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 7 Nov 2022 00:32:50 -0500 (EST) From: Samuel Holland To: Pavel Machek , linux-leds@vger.kernel.org, Chen-Yu Tsai , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v6 2/5] leds: sun50i-a100: New driver for the A100 LED controller Date: Sun, 6 Nov 2022 23:32:43 -0600 Message-Id: <20221107053247.1180-3-samuel@sholland.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221107053247.1180-1-samuel@sholland.org> References: <20221107053247.1180-1-samuel@sholland.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748814320622292026?= X-GMAIL-MSGID: =?utf-8?q?1748814320622292026?= Some Allwinner sunxi SoCs, starting with the A100, contain an LED controller designed to drive RGB LED pixels. Add a driver for it using the multicolor LED framework, and with LEDs defined in the device tree. Signed-off-by: Samuel Holland Acked-by: Jernej Skrabec --- (no changes since v5) Changes in v5: - Rename the driver R329 -> A100, since that is the actual original implementation Changes in v4: - Depend on LEDS_CLASS_MULTICOLOR Changes in v3: - Added vendor prefix to timing/format properties - Renamed "format" property to "pixel-format" for clarity - Dropped "vled-supply" as it is unrelated to the controller hardware - Changed "writesl" to "iowrite32_rep" so the driver builds on hppa Changes in v2: - Renamed from sunxi-ledc to sun50i-r329-ledc - Added missing "static" to functions/globals as reported by 0day bot drivers/leds/Kconfig | 9 + drivers/leds/Makefile | 1 + drivers/leds/leds-sun50i-a100.c | 554 ++++++++++++++++++++++++++++++++ 3 files changed, 564 insertions(+) create mode 100644 drivers/leds/leds-sun50i-a100.c diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig index 499d0f215a8b..4f4c515ed7d7 100644 --- a/drivers/leds/Kconfig +++ b/drivers/leds/Kconfig @@ -281,6 +281,15 @@ config LEDS_COBALT_RAQ help This option enables support for the Cobalt Raq series LEDs. +config LEDS_SUN50I_A100 + tristate "LED support for Allwinner A100 RGB LED controller" + depends on LEDS_CLASS_MULTICOLOR && OF + depends on ARCH_SUNXI || COMPILE_TEST + help + This option enables support for the RGB LED controller found + in some Allwinner sunxi SoCs, includeing A100, R329, and D1. + It uses a one-wire interface to control up to 1024 LEDs. + config LEDS_SUNFIRE tristate "LED support for SunFire servers." depends on LEDS_CLASS diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile index 4fd2f92cd198..a6ee3f5cf7be 100644 --- a/drivers/leds/Makefile +++ b/drivers/leds/Makefile @@ -76,6 +76,7 @@ obj-$(CONFIG_LEDS_PWM) += leds-pwm.o obj-$(CONFIG_LEDS_REGULATOR) += leds-regulator.o obj-$(CONFIG_LEDS_S3C24XX) += leds-s3c24xx.o obj-$(CONFIG_LEDS_SC27XX_BLTC) += leds-sc27xx-bltc.o +obj-$(CONFIG_LEDS_SUN50I_A100) += leds-sun50i-a100.o obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o obj-$(CONFIG_LEDS_SYSCON) += leds-syscon.o obj-$(CONFIG_LEDS_TCA6507) += leds-tca6507.o diff --git a/drivers/leds/leds-sun50i-a100.c b/drivers/leds/leds-sun50i-a100.c new file mode 100644 index 000000000000..238626288547 --- /dev/null +++ b/drivers/leds/leds-sun50i-a100.c @@ -0,0 +1,554 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (c) 2021-2022 Samuel Holland +// +// Partly based on drivers/leds/leds-turris-omnia.c, which is: +// Copyright (c) 2020 by Marek Behún +// + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LEDC_CTRL_REG 0x0000 +#define LEDC_CTRL_REG_DATA_LENGTH (0x1fff << 16) +#define LEDC_CTRL_REG_RGB_MODE (0x7 << 6) +#define LEDC_CTRL_REG_LEDC_EN BIT(0) +#define LEDC_T01_TIMING_CTRL_REG 0x0004 +#define LEDC_T01_TIMING_CTRL_REG_T1H (0x3f << 21) +#define LEDC_T01_TIMING_CTRL_REG_T1L (0x1f << 16) +#define LEDC_T01_TIMING_CTRL_REG_T0H (0x1f << 6) +#define LEDC_T01_TIMING_CTRL_REG_T0L (0x3f << 0) +#define LEDC_RESET_TIMING_CTRL_REG 0x000c +#define LEDC_RESET_TIMING_CTRL_REG_LED_NUM (0x3ff << 0) +#define LEDC_DATA_REG 0x0014 +#define LEDC_DMA_CTRL_REG 0x0018 +#define LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL (0x1f << 0) +#define LEDC_INT_CTRL_REG 0x001c +#define LEDC_INT_CTRL_REG_GLOBAL_INT_EN BIT(5) +#define LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN BIT(1) +#define LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN BIT(0) +#define LEDC_INT_STS_REG 0x0020 +#define LEDC_INT_STS_REG_FIFO_CPUREQ_INT BIT(1) +#define LEDC_INT_STS_REG_TRANS_FINISH_INT BIT(0) + +#define LEDC_FIFO_DEPTH 32 +#define LEDC_MAX_LEDS 1024 + +#define LEDS_TO_BYTES(n) ((n) * sizeof(u32)) + +struct sun50i_a100_ledc_led { + struct led_classdev_mc mc_cdev; + struct mc_subled subled_info[3]; +}; + +#define to_ledc_led(mc) container_of(mc, struct sun50i_a100_ledc_led, mc_cdev) + +struct sun50i_a100_ledc_timing { + u32 t0h_ns; + u32 t0l_ns; + u32 t1h_ns; + u32 t1l_ns; + u32 treset_ns; +}; + +struct sun50i_a100_ledc { + struct device *dev; + void __iomem *base; + struct clk *bus_clk; + struct clk *mod_clk; + struct reset_control *reset; + + u32 *buffer; + struct dma_chan *dma_chan; + dma_addr_t dma_handle; + int pio_length; + int pio_offset; + + spinlock_t lock; + int next_length; + bool xfer_active; + + u32 format; + struct sun50i_a100_ledc_timing timing; + + int num_leds; + struct sun50i_a100_ledc_led leds[]; +}; + +static int sun50i_a100_ledc_dma_xfer(struct sun50i_a100_ledc *priv, int length) +{ + struct dma_async_tx_descriptor *desc; + dma_cookie_t cookie; + + desc = dmaengine_prep_slave_single(priv->dma_chan, priv->dma_handle, + LEDS_TO_BYTES(length), + DMA_MEM_TO_DEV, 0); + if (!desc) + return -ENOMEM; + + cookie = dmaengine_submit(desc); + if (dma_submit_error(cookie)) + return -EIO; + + dma_async_issue_pending(priv->dma_chan); + + return 0; +} + +static void sun50i_a100_ledc_pio_xfer(struct sun50i_a100_ledc *priv, int length) +{ + u32 burst, offset, val; + + if (length) { + /* New transfer (FIFO is empty). */ + offset = 0; + burst = min(length, LEDC_FIFO_DEPTH); + } else { + /* Existing transfer (FIFO is half-full). */ + length = priv->pio_length; + offset = priv->pio_offset; + burst = min(length, LEDC_FIFO_DEPTH / 2); + } + + iowrite32_rep(priv->base + LEDC_DATA_REG, priv->buffer + offset, burst); + + if (burst < length) { + priv->pio_length = length - burst; + priv->pio_offset = offset + burst; + + if (!offset) { + val = readl(priv->base + LEDC_INT_CTRL_REG); + val |= LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; + writel(val, priv->base + LEDC_INT_CTRL_REG); + } + } else { + /* Disable the request IRQ once all data is written. */ + val = readl(priv->base + LEDC_INT_CTRL_REG); + val &= ~LEDC_INT_CTRL_REG_FIFO_CPUREQ_INT_EN; + writel(val, priv->base + LEDC_INT_CTRL_REG); + } +} + +static void sun50i_a100_ledc_start_xfer(struct sun50i_a100_ledc *priv, + int length) +{ + u32 val; + + dev_dbg(priv->dev, "Updating %d LEDs\n", length); + + val = readl(priv->base + LEDC_CTRL_REG); + val &= ~LEDC_CTRL_REG_DATA_LENGTH; + val |= length << 16 | LEDC_CTRL_REG_LEDC_EN; + writel(val, priv->base + LEDC_CTRL_REG); + + if (length > LEDC_FIFO_DEPTH) { + int ret = sun50i_a100_ledc_dma_xfer(priv, length); + + if (!ret) + return; + + dev_warn(priv->dev, "Failed to set up DMA: %d\n", ret); + } + + sun50i_a100_ledc_pio_xfer(priv, length); +} + +static irqreturn_t sun50i_a100_ledc_irq(int irq, void *dev_id) +{ + struct sun50i_a100_ledc *priv = dev_id; + u32 val; + + val = readl(priv->base + LEDC_INT_STS_REG); + + if (val & LEDC_INT_STS_REG_TRANS_FINISH_INT) { + int next_length; + + /* Start the next transfer if needed. */ + spin_lock(&priv->lock); + next_length = priv->next_length; + if (next_length) + priv->next_length = 0; + else + priv->xfer_active = false; + spin_unlock(&priv->lock); + + if (next_length) + sun50i_a100_ledc_start_xfer(priv, next_length); + } else if (val & LEDC_INT_STS_REG_FIFO_CPUREQ_INT) { + /* Continue the current transfer. */ + sun50i_a100_ledc_pio_xfer(priv, 0); + } + + writel(val, priv->base + LEDC_INT_STS_REG); + + return IRQ_HANDLED; +} + +static void sun50i_a100_ledc_brightness_set(struct led_classdev *cdev, + enum led_brightness brightness) +{ + struct sun50i_a100_ledc *priv = dev_get_drvdata(cdev->dev->parent); + struct led_classdev_mc *mc_cdev = lcdev_to_mccdev(cdev); + struct sun50i_a100_ledc_led *led = to_ledc_led(mc_cdev); + int addr = led - priv->leds; + unsigned long flags; + bool xfer_active; + int next_length; + + led_mc_calc_color_components(mc_cdev, brightness); + + priv->buffer[addr] = led->subled_info[0].brightness << 16 | + led->subled_info[1].brightness << 8 | + led->subled_info[2].brightness; + + dev_dbg(priv->dev, "LED %d -> #%06x\n", addr, priv->buffer[addr]); + + spin_lock_irqsave(&priv->lock, flags); + next_length = max(priv->next_length, addr + 1); + xfer_active = priv->xfer_active; + if (xfer_active) + priv->next_length = next_length; + else + priv->xfer_active = true; + spin_unlock_irqrestore(&priv->lock, flags); + + if (!xfer_active) + sun50i_a100_ledc_start_xfer(priv, next_length); +} + +static const char *const sun50i_a100_ledc_formats[] = { + "rgb", + "rbg", + "grb", + "gbr", + "brg", + "bgr", +}; + +static int sun50i_a100_ledc_parse_format(const struct device_node *np, + struct sun50i_a100_ledc *priv) +{ + const char *format = "grb"; + u32 i; + + of_property_read_string(np, "allwinner,pixel-format", &format); + + for (i = 0; i < ARRAY_SIZE(sun50i_a100_ledc_formats); ++i) { + if (!strcmp(format, sun50i_a100_ledc_formats[i])) { + priv->format = i; + return 0; + } + } + + dev_err(priv->dev, "Bad pixel format '%s'\n", format); + + return -EINVAL; +} + +static void sun50i_a100_ledc_set_format(struct sun50i_a100_ledc *priv) +{ + u32 val; + + val = readl(priv->base + LEDC_CTRL_REG); + val &= ~LEDC_CTRL_REG_RGB_MODE; + val |= priv->format << 6; + writel(val, priv->base + LEDC_CTRL_REG); +} + +static const struct sun50i_a100_ledc_timing sun50i_a100_ledc_default_timing = { + .t0h_ns = 336, + .t0l_ns = 840, + .t1h_ns = 882, + .t1l_ns = 294, + .treset_ns = 300000, +}; + +static int sun50i_a100_ledc_parse_timing(const struct device_node *np, + struct sun50i_a100_ledc *priv) +{ + struct sun50i_a100_ledc_timing *timing = &priv->timing; + + *timing = sun50i_a100_ledc_default_timing; + + of_property_read_u32(np, "allwinner,t0h-ns", &timing->t0h_ns); + of_property_read_u32(np, "allwinner,t0l-ns", &timing->t0l_ns); + of_property_read_u32(np, "allwinner,t1h-ns", &timing->t1h_ns); + of_property_read_u32(np, "allwinner,t1l-ns", &timing->t1l_ns); + of_property_read_u32(np, "allwinner,treset-ns", &timing->treset_ns); + + return 0; +} + +static void sun50i_a100_ledc_set_timing(struct sun50i_a100_ledc *priv) +{ + const struct sun50i_a100_ledc_timing *timing = &priv->timing; + unsigned long mod_freq = clk_get_rate(priv->mod_clk); + u32 cycle_ns = NSEC_PER_SEC / mod_freq; + u32 val; + + val = (timing->t1h_ns / cycle_ns) << 21 | + (timing->t1l_ns / cycle_ns) << 16 | + (timing->t0h_ns / cycle_ns) << 6 | + (timing->t0l_ns / cycle_ns); + writel(val, priv->base + LEDC_T01_TIMING_CTRL_REG); + + val = (timing->treset_ns / cycle_ns) << 16 | + (priv->num_leds - 1); + writel(val, priv->base + LEDC_RESET_TIMING_CTRL_REG); +} + +static int sun50i_a100_ledc_resume(struct device *dev) +{ + struct sun50i_a100_ledc *priv = dev_get_drvdata(dev); + u32 val; + int ret; + + ret = reset_control_deassert(priv->reset); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->bus_clk); + if (ret) + goto err_assert_reset; + + ret = clk_prepare_enable(priv->mod_clk); + if (ret) + goto err_disable_bus_clk; + + sun50i_a100_ledc_set_format(priv); + sun50i_a100_ledc_set_timing(priv); + + /* The trigger level must be at least the burst length. */ + val = readl(priv->base + LEDC_DMA_CTRL_REG); + val &= ~LEDC_DMA_CTRL_REG_FIFO_TRIG_LEVEL; + val |= LEDC_FIFO_DEPTH / 2; + writel(val, priv->base + LEDC_DMA_CTRL_REG); + + val = LEDC_INT_CTRL_REG_GLOBAL_INT_EN | + LEDC_INT_CTRL_REG_TRANS_FINISH_INT_EN; + writel(val, priv->base + LEDC_INT_CTRL_REG); + + return 0; + +err_disable_bus_clk: + clk_disable_unprepare(priv->bus_clk); +err_assert_reset: + reset_control_assert(priv->reset); + + return ret; +} + +static int sun50i_a100_ledc_suspend(struct device *dev) +{ + struct sun50i_a100_ledc *priv = dev_get_drvdata(dev); + + clk_disable_unprepare(priv->mod_clk); + clk_disable_unprepare(priv->bus_clk); + reset_control_assert(priv->reset); + + return 0; +} + +static void sun50i_a100_ledc_dma_cleanup(void *data) +{ + struct sun50i_a100_ledc *priv = data; + struct device *dma_dev = dmaengine_get_dma_device(priv->dma_chan); + + if (priv->buffer) + dma_free_wc(dma_dev, LEDS_TO_BYTES(priv->num_leds), + priv->buffer, priv->dma_handle); + dma_release_channel(priv->dma_chan); +} + +static int sun50i_a100_ledc_probe(struct platform_device *pdev) +{ + const struct device_node *np = pdev->dev.of_node; + struct dma_slave_config dma_cfg = {}; + struct led_init_data init_data = {}; + struct device *dev = &pdev->dev; + struct device_node *child; + struct sun50i_a100_ledc *priv; + struct resource *mem; + int count, irq, ret; + + count = of_get_available_child_count(np); + if (!count) + return -ENODEV; + if (count > LEDC_MAX_LEDS) { + dev_err(dev, "Too many LEDs! (max is %d)\n", LEDC_MAX_LEDS); + return -EINVAL; + } + + priv = devm_kzalloc(dev, struct_size(priv, leds, count), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->num_leds = count; + spin_lock_init(&priv->lock); + dev_set_drvdata(dev, priv); + + ret = sun50i_a100_ledc_parse_format(np, priv); + if (ret) + return ret; + + ret = sun50i_a100_ledc_parse_timing(np, priv); + if (ret) + return ret; + + priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + priv->bus_clk = devm_clk_get(dev, "bus"); + if (IS_ERR(priv->bus_clk)) + return PTR_ERR(priv->bus_clk); + + priv->mod_clk = devm_clk_get(dev, "mod"); + if (IS_ERR(priv->mod_clk)) + return PTR_ERR(priv->mod_clk); + + priv->reset = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(priv->reset)) + return PTR_ERR(priv->reset); + + priv->dma_chan = dma_request_chan(dev, "tx"); + if (IS_ERR(priv->dma_chan)) + return PTR_ERR(priv->dma_chan); + + ret = devm_add_action_or_reset(dev, sun50i_a100_ledc_dma_cleanup, priv); + if (ret) + return ret; + + dma_cfg.dst_addr = mem->start + LEDC_DATA_REG; + dma_cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; + dma_cfg.dst_maxburst = LEDC_FIFO_DEPTH / 2; + ret = dmaengine_slave_config(priv->dma_chan, &dma_cfg); + if (ret) + return ret; + + priv->buffer = dma_alloc_wc(dmaengine_get_dma_device(priv->dma_chan), + LEDS_TO_BYTES(priv->num_leds), + &priv->dma_handle, GFP_KERNEL); + if (!priv->buffer) + return -ENOMEM; + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + ret = devm_request_irq(dev, irq, sun50i_a100_ledc_irq, + 0, dev_name(dev), priv); + if (ret) + return ret; + + ret = sun50i_a100_ledc_resume(dev); + if (ret) + return ret; + + for_each_available_child_of_node(np, child) { + struct sun50i_a100_ledc_led *led; + struct led_classdev *cdev; + u32 addr, color; + + ret = of_property_read_u32(child, "reg", &addr); + if (ret || addr >= count) { + dev_err(dev, "LED 'reg' values must be from 0 to %d\n", + priv->num_leds - 1); + ret = -EINVAL; + goto err_put_child; + } + + ret = of_property_read_u32(child, "color", &color); + if (ret || color != LED_COLOR_ID_RGB) { + dev_err(dev, "LED 'color' must be LED_COLOR_ID_RGB\n"); + ret = -EINVAL; + goto err_put_child; + } + + led = &priv->leds[addr]; + + led->subled_info[0].color_index = LED_COLOR_ID_RED; + led->subled_info[0].channel = 0; + led->subled_info[1].color_index = LED_COLOR_ID_GREEN; + led->subled_info[1].channel = 1; + led->subled_info[2].color_index = LED_COLOR_ID_BLUE; + led->subled_info[2].channel = 2; + + led->mc_cdev.num_colors = ARRAY_SIZE(led->subled_info); + led->mc_cdev.subled_info = led->subled_info; + + cdev = &led->mc_cdev.led_cdev; + cdev->max_brightness = U8_MAX; + cdev->brightness_set = sun50i_a100_ledc_brightness_set; + + init_data.fwnode = of_fwnode_handle(child); + + ret = devm_led_classdev_multicolor_register_ext(dev, + &led->mc_cdev, + &init_data); + if (ret) { + dev_err(dev, "Failed to register LED %u: %d\n", + addr, ret); + goto err_put_child; + } + } + + dev_info(dev, "Registered %d LEDs\n", priv->num_leds); + + return 0; + +err_put_child: + of_node_put(child); + sun50i_a100_ledc_suspend(&pdev->dev); + + return ret; +} + +static int sun50i_a100_ledc_remove(struct platform_device *pdev) +{ + sun50i_a100_ledc_suspend(&pdev->dev); + + return 0; +} + +static void sun50i_a100_ledc_shutdown(struct platform_device *pdev) +{ + sun50i_a100_ledc_suspend(&pdev->dev); +} + +static const struct of_device_id sun50i_a100_ledc_of_match[] = { + { .compatible = "allwinner,sun50i-a100-ledc" }, + {} +}; +MODULE_DEVICE_TABLE(of, sun50i_a100_ledc_of_match); + +static SIMPLE_DEV_PM_OPS(sun50i_a100_ledc_pm, + sun50i_a100_ledc_suspend, sun50i_a100_ledc_resume); + +static struct platform_driver sun50i_a100_ledc_driver = { + .probe = sun50i_a100_ledc_probe, + .remove = sun50i_a100_ledc_remove, + .shutdown = sun50i_a100_ledc_shutdown, + .driver = { + .name = "sun50i-a100-ledc", + .of_match_table = sun50i_a100_ledc_of_match, + .pm = pm_ptr(&sun50i_a100_ledc_pm), + }, +}; +module_platform_driver(sun50i_a100_ledc_driver); + +MODULE_AUTHOR("Samuel Holland "); +MODULE_DESCRIPTION("Allwinner A100 LED controller driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Nov 7 05:32:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 16238 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1849621wru; Sun, 6 Nov 2022 21:34:21 -0800 (PST) X-Google-Smtp-Source: AMsMyM4RB1j1vv+JRKhp24ZcWcugynCY8jbdxg6csD2M98CC4HLTB1fpMX1xPQKV7eAlFgbHa/e0 X-Received: by 2002:a63:34c8:0:b0:46e:f67c:c117 with SMTP id b191-20020a6334c8000000b0046ef67cc117mr41690286pga.401.1667799261158; Sun, 06 Nov 2022 21:34:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667799261; cv=none; d=google.com; s=arc-20160816; b=CSFZ2TpXJ4xTSwNeRTrVvPkrGztt+Q7iH7KotbdhjzqZDZ5JgyWAeXF/3q1I/oojhe 6KecWjx1y2e39JzYyKfPHhxT2Do/PD58apZmiFrjH0ZU7smE6OsCXRzLVRBx1ezoCA4i BM+snfh4ZXP87epBqch0lENN76IGWBzHH5//65HpNwcrrS5MoaK63y0gs0MFVaDcmp6g t+1E4wXhxiCeB3D9qN+1KIwvpRMWd52rgJf+FAbN0zakysWQhSkt9mOXg7fo9NMx8U4w j86bJpyDGgb6pIGH8hGWRXNlpZOORC/j0cNSPUEYF+U0vupBa1r9+ojEF3NHnHuUWxRg A16w== ARC-Message-Signature: i=1; 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Add it to the devicetree. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v5) Changes in v5: - New patch for v5 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi index 97e3e6907acd..2c90683145f2 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi @@ -273,6 +273,20 @@ i2c3: i2c@5002c00 { #size-cells = <0>; }; + ledc: led-controller@5018000 { + compatible = "allwinner,sun50i-a100-ledc"; + reg = <0x5018000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + ths: thermal-sensor@5070400 { compatible = "allwinner,sun50i-a100-ths"; reg = <0x05070400 0x100>; From patchwork Mon Nov 7 05:32:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 16240 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1850115wru; Sun, 6 Nov 2022 21:36:12 -0800 (PST) X-Google-Smtp-Source: AMsMyM717vxSpnamtIxFYdqFyD98J+JJBY+6O3zqGE2NMaj2SJE0YcbM162w+9AjyACI4YK6HQ14 X-Received: by 2002:a17:902:6a86:b0:176:a6bc:54c0 with SMTP id n6-20020a1709026a8600b00176a6bc54c0mr50161120plk.87.1667799372567; Sun, 06 Nov 2022 21:36:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667799372; cv=none; d=google.com; s=arc-20160816; b=U3pO7LZjPCdPsfDIXu1Q2nTEQigdibc0/dQuyygOVMZ+qQ2LxoCGnsaPu8aOygTzhd psjFIuRJL0RwUbl86kcNNuR6740m5ASID++33tzgTlen5e52+5fy9QGwPNSMETPRDqUQ 9qbEtAThDEEtWnFT41Mj/to7ZwygZ/Oz+BU/RAMkn0gC/sifT2ZyhT5JzKA/uATJ9RGF GWF9xldZ/gwplmHqPmnvnDq223bwzWXEQDorKjdy1KHgCF6LJbVoYWX/gGnVLQ0p1K1Z PWms/e+7D5JT4qIlyKC/9nsLIlsclawJtmhLWiduSbifOpwLeaPqVDBPxjOwypHxrJsv 2jLQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=rb54mEX2euKxbMAz3voJkO60XtjBIRlH8c9USq+WGWw=; b=0hd6dd7sBt7KRZoEVVp+k5rfOgA12rsj8TusAt7XznGChSvwkE0QsRzxitfwnjjTUV Uy/cPZrfc+8FauLyrnzIKc0wHD4tRzwuBsNvWTXr1sseRlPWvxLkhBmsixLyZjwfdYBB TuPixKUJ5x9s6+5To9BUepC/Hqric6Lp5BR5bAbr5BBulon/onyiLokpQDs0gcoTPBwI c//R7Ff26xjcicW+Tm/DRC5Ll/kpax3btYp3RTzuOo0M7y0K4TsRXkrVJ5lleD0/FC9f rt50BOguH7/o+UVcVOyDOY2WdXqSHUjyPTEbJi9U3xpbb5Szh28ev6wstutcUdT80C3+ K1Vw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sholland.org header.s=fm1 header.b=czBhdnVn; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b="kJ/ily+q"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sholland.org Received: from out1.vger.email (out1.vger.email. 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Add its devicetree node, as well as the pinmux used by the reference board design. Signed-off-by: Samuel Holland Reviewed-by: Jernej Skrabec --- (no changes since v5) Changes in v5: - New patch for v5 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 21 ++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi index 9a9b3e0fe79d..53b0cb64906f 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi @@ -115,6 +115,12 @@ lcd_rgb666_pins: lcd-rgb666-pins { function = "lcd0"; }; + /omit-if-no-ref/ + ledc_pc0_pin: ledc-pc0-pin { + pins = "PC0"; + function = "ledc"; + }; + /omit-if-no-ref/ mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; @@ -178,6 +184,21 @@ ccu: clock-controller@2001000 { #reset-cells = <1>; }; + ledc: led-controller@2008000 { + compatible = "allwinner,sun20i-d1-ledc", + "allwinner,sun50i-a100-ledc"; + reg = <0x2008000 0x400>; + interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_LEDC>, <&ccu CLK_LEDC>; + clock-names = "bus", "mod"; + resets = <&ccu RST_BUS_LEDC>; + dmas = <&dma 42>; + dma-names = "tx"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + lradc: keys@2009800 { compatible = "allwinner,sun20i-d1-lradc", "allwinner,sun50i-r329-lradc"; From patchwork Mon Nov 7 05:32:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Samuel Holland X-Patchwork-Id: 16241 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1850139wru; Sun, 6 Nov 2022 21:36:14 -0800 (PST) X-Google-Smtp-Source: AMsMyM6JWdeqGgnIvvAHCnE0rWd9f8Wtfe2O2b9ScIh4VACppWU7lEJTE02zsDwgU2MeE8kINu1z X-Received: by 2002:a17:903:41cc:b0:186:b756:a5f0 with SMTP id u12-20020a17090341cc00b00186b756a5f0mr49228063ple.132.1667799374646; Sun, 06 Nov 2022 21:36:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667799374; cv=none; d=google.com; s=arc-20160816; b=pn7j+54aKug6R75GSMaz7EYj2m2deYLnrXYxqwz57Plam+a7mNa2TDoNcscJc1lvks b3pn3BomGLWuQ4DRAFTBTU1jSrJhnji3WU4brmrawhpRyvkfCVPmdxqt7I0y+v77jMYm 318Rutalt+Tnq75k+eko09jUFIXawwjyLnNfDLg9I8tuQwJ4cVMSjRvQhCFwpHEQt3T3 k2bEN4Bxk0mbILb802WTnX6lEt5dtIMjI7a+ysiVqvbCEmNk52LEv9l7ubWdgccW5Wdv ld2BZV2DmT4Ux+6KRbeWdT8i6JonAXHz4Op+/F3EFcpH/yDh4ojMVO78QmHHBSlo5AdM elSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=1R1DZWFpevQOPZqRZc5KNPqt9efV8bhbezth/9NJtpE=; b=SAX4UiAzYGbQ+ireLMkOsgeWR3PO0BLReoWRtKaqMMP6C7ElLSiYmCU/qrKR0hUsAP Ir/Q44fLimcCmauY4VKE2M525e6dpGT81BXTaT0zDtX/NOljSHG/jRAHPrMNXnLSPorw i8seavkhxtlWVCVn+eoK6++h1vk6Ow+hgd6X4foaykhpJAUjJGF6Uo4xVWaYDA8YARir 3P30Nbnr/TC4dDvBspdIMdcREA2j0XbMWeqgHsInZ8jPF3QFtpfxo6KbEKAWWWamjsNW 7xPBji6lz2AbN5VE+Hi1n/L9EuYZZwHPfOpD89COCUplRiEgAnH88IKiHvdhS+HtDqj8 AcTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sholland.org header.s=fm1 header.b=Gg+w8T8k; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=rdSZ54j0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sholland.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id oo16-20020a17090b1c9000b00200bbb9027asi15888797pjb.77.2022.11.06.21.36.01; Sun, 06 Nov 2022 21:36:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@sholland.org header.s=fm1 header.b=Gg+w8T8k; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=rdSZ54j0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sholland.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230460AbiKGFdJ (ORCPT + 99 others); Mon, 7 Nov 2022 00:33:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230373AbiKGFc4 (ORCPT ); Mon, 7 Nov 2022 00:32:56 -0500 Received: from out3-smtp.messagingengine.com (out3-smtp.messagingengine.com [66.111.4.27]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 69E3E11C3A; Sun, 6 Nov 2022 21:32:54 -0800 (PST) Received: from compute1.internal (compute1.nyi.internal [10.202.2.41]) by mailout.nyi.internal (Postfix) with ESMTP id C0C7B5C009C; Mon, 7 Nov 2022 00:32:53 -0500 (EST) Received: from mailfrontend1 ([10.202.2.162]) by compute1.internal (MEProxy); Mon, 07 Nov 2022 00:32:53 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sholland.org; h= cc:cc:content-transfer-encoding:date:date:from:from:in-reply-to :in-reply-to:message-id:mime-version:references:reply-to:sender :subject:subject:to:to; s=fm1; t=1667799173; x=1667885573; bh=1R 1DZWFpevQOPZqRZc5KNPqt9efV8bhbezth/9NJtpE=; b=Gg+w8T8k542hNjDfF+ Y4Qam2g8iLx0wbeCR7AvL3JyAwDPhRo8yifrbgPx5OoN7qdeNEA52OdrSyt9exzh W4je62AQhNBiSxwvJYa3clzYqgkV5wu/OqRZKA+kHW7XbhnReavPCv/usrrHp/Nv be2WMq1fL36YaWte0wtoCC8srPWOYUXdgKzXcOdyatG7xyEjt5EaGKOy8a45nLzD FsSkikp9z1jD6fuxk5Awgy/suGvO4dce3h3J7tifdFaQJ7VQ1hRSgL5B/UYFiuP7 Xd31l8zHD58qDNkqx296Sby1ZQArlWDH8mvziZc9FhemxO1UVHhtQNBPQAN3Z79J zHWw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding:date:date :feedback-id:feedback-id:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to:x-me-proxy:x-me-proxy:x-me-sender:x-me-sender :x-sasl-enc; s=fm3; t=1667799173; x=1667885573; bh=1R1DZWFpevQOP ZqRZc5KNPqt9efV8bhbezth/9NJtpE=; b=rdSZ54j03yQXR0iGz2I46xGiiN/ik +cfFAJfVs63SKGunbM2NN6CagaPr9UQfhszcSjsGLeH+6bULAQEiSwXFHtNcF0f+ nnHhhTh/58bAFThEbZm54STILR/rLIh7FItj+RerUp3XQyuL0ucY3TwPRfy9J8XD rgWrFG8D4iiSdZqLVCrdJMbs4a8kbaJ0+lU6cA29P2Wr+9iWB+P1yRNlrwr44y0e mYrplczkCHrdc+2nBp7dB3qtn+nLsi/H//Wv1oLjdVIlwf2AFVX6HQO/UCggKSqb 50h+XNUcgYTxB6Qb60ch98Bnm4JfxhsRmvgtT7LP5Ebel9cG+xPPk3D2Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvgedrvdejgdekgecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenuc fjughrpefhvfevufffkffojghfggfgsedtkeertdertddtnecuhfhrohhmpefurghmuhgv lhcujfholhhlrghnugcuoehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhgqeenucggtf frrghtthgvrhhnpedukeetueduhedtleetvefguddvvdejhfefudelgfduveeggeehgfdu feeitdevteenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhroh hmpehsrghmuhgvlhesshhhohhllhgrnhgurdhorhhg X-ME-Proxy: Feedback-ID: i0ad843c9:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Mon, 7 Nov 2022 00:32:53 -0500 (EST) From: Samuel Holland To: Pavel Machek , linux-leds@vger.kernel.org, Chen-Yu Tsai , Jernej Skrabec Cc: devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Samuel Holland Subject: [PATCH v6 5/5] riscv: dts: allwinner: d1: Add RGB LEDs to boards Date: Sun, 6 Nov 2022 23:32:46 -0600 Message-Id: <20221107053247.1180-6-samuel@sholland.org> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221107053247.1180-1-samuel@sholland.org> References: <20221107053247.1180-1-samuel@sholland.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748814396947605415?= X-GMAIL-MSGID: =?utf-8?q?1748814396947605415?= Some D1-based boards feature an onboard RGB LED. Enable them. Signed-off-by: Samuel Holland Acked-by: Jernej Skrabec --- (no changes since v5) Changes in v5: - New patch for v5 .../boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts | 12 ++++++++++++ arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts | 13 +++++++++++++ 2 files changed, 25 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts index ca36a5d75a7f..02d13e987e02 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-lichee-rv-dock.dts @@ -25,6 +25,18 @@ &ehci1 { status = "okay"; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &lradc { status = "okay"; diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts index df865ee15fcf..099075462998 100644 --- a/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts +++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-nezha.dts @@ -5,6 +5,7 @@ #include #include +#include #include "sun20i-d1.dtsi" #include "sun20i-d1-common-regulators.dtsi" @@ -90,6 +91,18 @@ pcf8574a: gpio@38 { }; }; +&ledc { + pinctrl-0 = <&ledc_pc0_pin>; + pinctrl-names = "default"; + status = "okay"; + + multi-led@0 { + reg = <0x0>; + color = ; + function = LED_FUNCTION_STATUS; + }; +}; + &lradc { status = "okay";