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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id z14-20020a17090a66ce00b002791d2ce94asi1989285pjl.81.2023.10.12.02.57.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:57:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eVltjlch; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id CA7E58218E50; Thu, 12 Oct 2023 02:57:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235586AbjJLJ5s (ORCPT + 19 others); Thu, 12 Oct 2023 05:57:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229757AbjJLJ5q (ORCPT ); Thu, 12 Oct 2023 05:57:46 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06C38C0 for ; Thu, 12 Oct 2023 02:57:44 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B2AD06607346; Thu, 12 Oct 2023 10:57:42 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104663; bh=rJh9dq2zg8Xp2mCThXqt5EFMAevJSGKGnsZ1ZKAX+pQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eVltjlchZ7V33dLGRpRPA+P+A/oWfDcoJyl7sJIlONTqojqblnHSO9dYgIMuusYkY Cm5ZbQqmiQXyqobohmVZk9Rf+QkWAalbA8JMlAJsWkcaVTsudgPq4vJJI/TcHVCX2F 4fBrTt5YcFTe6nIC/6a+Wra/YS3p8nFaTNBPZdvT0UWZ1KXdi9R6nEvPdk2FjkWtG8 KnD9O6XE/h2JYF2Qx2+OEpp5hW1JZ6Flpt+jeAwuUVN69uVoIGyZKcOEbIcbmYnJ/Q ZD80DMAE5JNI2LgbTfUI3YLHEbv+eShP9gzFwrvrFdD2pleYBfOIfwFJ5xaXY/EltO nbmSCyRxYa0nA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, "Jason-JH.Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 01/16] drm/mediatek: gamma: Adjust mtk_drm_gamma_set_common parameters Date: Thu, 12 Oct 2023 11:57:21 +0200 Message-ID: <20231012095736.100784-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:57:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543231322813621 X-GMAIL-MSGID: 1779543231322813621 From: "Jason-JH.Lin" Adjust the parameters in mtk_drm_gamma_set_common() - add (struct device *dev) to get lut_diff from gamma's driver data - remove (bool lut_diff) and use false as default value in the function Signed-off-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 2 +- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 +- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 18 ++++++++++++------ 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index ce2da1ccec6f..662c5d03ee43 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -61,7 +61,7 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) struct mtk_disp_aal *aal = dev_get_drvdata(dev); if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(aal->regs, state, false); + mtk_gamma_set_common(NULL, aal->regs, state); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 2254038519e1..75045932353e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -54,7 +54,7 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff); +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index e9242249884b..68e2565b88a5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -54,14 +54,24 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } -void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool lut_diff) +void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { + struct mtk_disp_gamma *gamma; unsigned int i, reg; struct drm_color_lut *lut; void __iomem *lut_base; + bool lut_diff; u32 word; u32 diff[3] = {0}; + /* If we're called from AAL, dev is NULL */ + gamma = dev ? dev_get_drvdata(dev) : NULL; + + if (gamma && gamma->data) + lut_diff = gamma->data->lut_diff; + else + lut_diff = false; + if (state->gamma_lut) { reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; @@ -91,12 +101,8 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state, bool void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - bool lut_diff = false; - - if (gamma->data) - lut_diff = gamma->data->lut_diff; - mtk_gamma_set_common(gamma->regs, state, lut_diff); + mtk_gamma_set_common(dev, gamma->regs, state); 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 02/16] drm/mediatek: gamma: Reduce indentation in mtk_gamma_set_common() Date: Thu, 12 Oct 2023 11:57:22 +0200 Message-ID: <20231012095736.100784-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543258356077876 X-GMAIL-MSGID: 1779543258356077876 Invert the check for state->gamma_lut and move it at the beginning of the function to reduce indentation: this prepares the code for keeping readability on later additions. This commit brings no functional changes. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 45 ++++++++++++----------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 68e2565b88a5..63840e25416b 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -64,6 +64,10 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt u32 word; u32 diff[3] = {0}; + /* If there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; @@ -72,29 +76,26 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt else lut_diff = false; - if (state->gamma_lut) { - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); - lut_base = regs + DISP_GAMMA_LUT; - lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { - - if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); - } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); - - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); - } - writel(word, (lut_base + i * 4)); + reg = readl(regs + DISP_GAMMA_CFG); + reg = reg | GAMMA_LUT_EN; + writel(reg, regs + DISP_GAMMA_CFG); + lut_base = regs + DISP_GAMMA_LUT; + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < MTK_LUT_SIZE; i++) { + if (!lut_diff || (i % 2 == 0)) { + word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + + ((lut[i].blue >> 6) & LUT_10BIT_MASK); + } else { + diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); + diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); + diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + + word = ((diff[0] & LUT_10BIT_MASK) << 20) + + ((diff[1] & LUT_10BIT_MASK) << 10) + + (diff[2] & LUT_10BIT_MASK); } + writel(word, (lut_base + i * 4)); } } From patchwork Thu Oct 12 09:57:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151881 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104690vqb; Thu, 12 Oct 2023 02:58:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFWeG2Upwae7nvKcyEo9VlRESuiTwfcEvK5SNqHlWmK6C6ONJCf7x1cf8ciH2AIXJ2Xyefd X-Received: by 2002:a05:6a00:39a8:b0:692:ad93:e852 with SMTP id fi40-20020a056a0039a800b00692ad93e852mr25582392pfb.2.1697104688873; Thu, 12 Oct 2023 02:58:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104688; cv=none; d=google.com; s=arc-20160816; b=hzotygd7KFdiC0fnp9LpJEQcU9c3fLkA04HQuWEuYZEJJc1C249G2LlEtq3BDowMpU 4ddKFbNHMmQkYK7TRzn2Ar5yZyO+T/QMmQtZzG+Y2Okx9aGvIf00ioBtnadp3J/VgD6a xlQe6auuKPtcWwmC+2DrkRlswVzfIVeILmGmJjcGQWGMXzy7L0FXCXFMU3o+kJuC5pNB tFsm8X51I2YU4UF9uwNcmHdYcxPQSXbF4i7EL6V0kdJpdrkL0rfmBlaFTB+t02V5OjA8 e85q6HElGc/0LCWmJIzzTDPdExkzjncWX8wnqQEW1eGgDJN6h1+rcBRNhml0bBlWHGO/ XuGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=H1SMhH+VWzARkwD9fU4lWLCZrMbQ35gt1sOrQXUNPcM=; fh=KhamMcu+afW+JcycbJwsIN7GCvQjQBx356VRODtXooA=; b=JvdD7zYJsUnA5TUWUlCIvTSxt2WmDB0mbLblpEe/umd7+H4k6lFThpJpt5ijjGvTTm egI8UQ8s77LCjdWoFVf4VtIM2dyxfcs5lR1uRXRq+pj6E+IaOIdobk2uIYhYSwe6IGxp zRK5etHVWitkQYHEndgjv3Nxp7RFh4iie1fIZG8SGczKE017vtUhy6er6VVe24EaMJCu p+StmjeMnUcE2LR/moUTbAgFv3sZnuV2v8HG1tAyF/Qke4+aX1y55gFShy8sf27oyFzM EOn7B5op04+VgGRQEiOw3kIgrJwkRMkVd1xfk/Feu1W2FSlBvifJXvfsp/Aw3r473/Q7 NYKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=FqIQwytI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 03/16] drm/mediatek: gamma: Support SoC specific LUT size Date: Thu, 12 Oct 2023 11:57:23 +0200 Message-ID: <20231012095736.100784-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543246263385687 X-GMAIL-MSGID: 1779543246263385687 Newer SoCs support a bigger Gamma LUT table: wire up a callback to retrieve the correct LUT size for each different Gamma IP. Co-developed-by: Jason-JH.Lin Signed-off-by: Jason-JH.Lin [Angelo: Rewritten commit message/description + porting] Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 17 +++++++++++++++- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 2 ++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 22 ++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 8 ++++++-- drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 1 - drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++ drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 9 +++++++++ 7 files changed, 54 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 662c5d03ee43..dc26ddce0c6e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -19,7 +19,7 @@ #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_OUTPUT_SIZE 0x04d8 - +#define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { bool has_gamma; @@ -56,6 +56,21 @@ void mtk_aal_config(struct device *dev, unsigned int w, mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } +/** + * mtk_aal_gamma_get_lut_size() - Get gamma LUT size for AAL + * @dev: Pointer to struct device + * + * Return: 0 if gamma control not supported in AAL or gamma LUT size + */ +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_aal *aal = dev_get_drvdata(dev); + + if (aal->data && aal->data->has_gamma) + return DISP_AAL_LUT_SIZE; + return 0; +} + void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index 75045932353e..ca377265e5eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -17,6 +17,7 @@ void mtk_aal_clk_disable(struct device *dev); void mtk_aal_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_aal_gamma_get_lut_size(struct device *dev); void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_aal_start(struct device *dev); void mtk_aal_stop(struct device *dev); @@ -53,6 +54,7 @@ void mtk_gamma_clk_disable(struct device *dev); void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); +unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 63840e25416b..bb237523d4b7 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -28,6 +28,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_size; }; /* @@ -54,6 +55,15 @@ void mtk_gamma_clk_disable(struct device *dev) clk_disable_unprepare(gamma->clk); } +unsigned int mtk_gamma_get_lut_size(struct device *dev) +{ + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + + if (gamma && gamma->data) + return gamma->data->lut_size; + return 0; +} + void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma; @@ -61,6 +71,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; + u16 lut_size; u32 word; u32 diff[3] = {0}; @@ -71,17 +82,20 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt /* If we're called from AAL, dev is NULL */ gamma = dev ? dev_get_drvdata(dev) : NULL; - if (gamma && gamma->data) + if (gamma && gamma->data) { lut_diff = gamma->data->lut_diff; - else + lut_size = gamma->data->lut_size; + } else { lut_diff = false; + lut_size = 512; + } reg = readl(regs + DISP_GAMMA_CFG); reg = reg | GAMMA_LUT_EN; writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < MTK_LUT_SIZE; i++) { + for (i = 0; i < lut_size; i++) { if (!lut_diff || (i % 2 == 0)) { word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + @@ -192,10 +206,12 @@ static void mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_diff = true, + .lut_size = 512, }; static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 45d05b6b7071..18da16e5626b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -943,8 +943,12 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev, mtk_crtc->ddp_comp[i] = comp; if (comp->funcs) { - if (comp->funcs->gamma_set) - gamma_lut_size = MTK_LUT_SIZE; + if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) { + unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp); + + if (lut_sz) + gamma_lut_size = lut_sz; + } if (comp->funcs->ctm_set) has_ctm = true; diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h index 3e9046993d09..b2e50292e57d 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h @@ -10,7 +10,6 @@ #include "mtk_drm_ddp_comp.h" #include "mtk_drm_plane.h" -#define MTK_LUT_SIZE 512 #define MTK_MAX_BPC 10 #define MTK_MIN_BPC 3 diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c index 5d392ce96a14..51f802be8440 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c @@ -263,6 +263,7 @@ static void mtk_ufoe_start(struct device *dev) static const struct mtk_ddp_comp_funcs ddp_aal = { .clk_enable = mtk_aal_clk_enable, .clk_disable = mtk_aal_clk_disable, + .gamma_get_lut_size = mtk_aal_gamma_get_lut_size, .gamma_set = mtk_aal_gamma_set, .config = mtk_aal_config, .start = mtk_aal_start, @@ -314,6 +315,7 @@ static const struct mtk_ddp_comp_funcs ddp_dsi = { static const struct mtk_ddp_comp_funcs ddp_gamma = { .clk_enable = mtk_gamma_clk_enable, .clk_disable = mtk_gamma_clk_disable, + .gamma_get_lut_size = mtk_gamma_get_lut_size, .gamma_set = mtk_gamma_set, .config = mtk_gamma_config, .start = mtk_gamma_start, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h index febcaeef16a1..c1355960e195 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h @@ -67,6 +67,7 @@ struct mtk_ddp_comp_funcs { void (*layer_config)(struct device *dev, unsigned int idx, struct mtk_plane_state *state, struct cmdq_pkt *cmdq_pkt); + unsigned int (*gamma_get_lut_size)(struct device *dev); void (*gamma_set)(struct device *dev, struct drm_crtc_state *state); void (*bgclr_in_on)(struct device *dev); @@ -186,6 +187,14 @@ static inline void mtk_ddp_comp_layer_config(struct mtk_ddp_comp *comp, comp->funcs->layer_config(comp->dev, idx, state, cmdq_pkt); } +static inline unsigned int mtk_ddp_gamma_get_lut_size(struct mtk_ddp_comp *comp) +{ + if (comp->funcs && comp->funcs->gamma_get_lut_size) + return comp->funcs->gamma_get_lut_size(comp->dev); + + return 0; +} + static inline void mtk_ddp_gamma_set(struct mtk_ddp_comp *comp, struct drm_crtc_state *state) { From patchwork Thu Oct 12 09:57:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151883 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104819vqb; Thu, 12 Oct 2023 02:58:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxV1BpuSZvvzK6GR9JENRtDTMggzeF5MO82GKbyERjMPB3OwdU6DY2p231AESQ+7bIzst+ X-Received: by 2002:a05:6830:3109:b0:6b9:db20:4d25 with SMTP id b9-20020a056830310900b006b9db204d25mr34214116ots.1.1697104704810; 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 04/16] drm/mediatek: gamma: Improve and simplify HW LUT calculation Date: Thu, 12 Oct 2023 11:57:24 +0200 Message-ID: <20231012095736.100784-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:22 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543262790815269 X-GMAIL-MSGID: 1779543262790815269 Use drm_color_lut_extract() to avoid open-coding the bits reduction calculations for each color channel and use a struct drm_color_lut to temporarily store the information instead of an array of u32. Also, slightly improve the precision of the HW LUT calculation in the LUT DIFF case by performing the subtractions on the 16-bits values and doing the 10 bits conversion later. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 32 ++++++++++++++--------- 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index bb237523d4b7..8506b9a0a811 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -23,8 +23,6 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_LUT 0x0700 -#define LUT_10BIT_MASK 0x03ff - struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; @@ -73,7 +71,6 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt bool lut_diff; u16 lut_size; u32 word; - u32 diff[3] = {0}; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -96,18 +93,29 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[i].red, 10); + hwlut.green = drm_color_lut_extract(lut[i].green, 10); + hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); + if (!lut_diff || (i % 2 == 0)) { - word = (((lut[i].red >> 6) & LUT_10BIT_MASK) << 20) + - (((lut[i].green >> 6) & LUT_10BIT_MASK) << 10) + - ((lut[i].blue >> 6) & LUT_10BIT_MASK); + word = hwlut.red << 20 + + hwlut.green << 10 + + hwlut.red; } else { - diff[0] = (lut[i].red >> 6) - (lut[i - 1].red >> 6); - diff[1] = (lut[i].green >> 6) - (lut[i - 1].green >> 6); - diff[2] = (lut[i].blue >> 6) - (lut[i - 1].blue >> 6); + diff.red = lut[i].red - lut[i - 1].red; + diff.red = drm_color_lut_extract(diff.red, 10); + + diff.green = lut[i].green - lut[i - 1].green; + diff.green = drm_color_lut_extract(diff.green, 10); + + diff.blue = lut[i].blue - lut[i - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, 10); - word = ((diff[0] & LUT_10BIT_MASK) << 20) + - ((diff[1] & LUT_10BIT_MASK) << 10) + - (diff[2] & LUT_10BIT_MASK); + word = diff.blue << 20 + + diff.green << 10 + + diff.red; } writel(word, (lut_base + i * 4)); } From patchwork Thu Oct 12 09:57:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151884 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104872vqb; Thu, 12 Oct 2023 02:58:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG3iVudbmJRSu84zuX9GpTZ6fiS2n2Oy6jO4usGe1jvVncvwSgBlp5VSuLZjjOJXJFpcagB X-Received: by 2002:a17:902:e80a:b0:1c4:1e65:1e5e with SMTP id u10-20020a170902e80a00b001c41e651e5emr26429380plg.0.1697104713389; Thu, 12 Oct 2023 02:58:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104713; cv=none; d=google.com; s=arc-20160816; b=PPw2X/+6hzsHVxTtdt5Dqo/qoqY+Bi5ceBuY69Qhq0uenBByauUfkx1N6v2gigguzj HTO6OMpHyePYtvrexM8vtpoFAKicKK3dc5J/tDQaYFg8R/jdoOXugUCmLqJtqTotouxg E+Hlh287Z71lJ9dnQRWIgi+SPrNZWP23i/2EJqyJKZtXCp4ZW+D5cFhdpnjwvIdwG219 xdaZh7bl5nhhKFiIQ3bT2bU+qpeAcf0B3k1mZ4Al9YrL6NCg1sAveFI+yESQcqL84LnL +yFwEs9YaoKxNBLjyJCEo/L464Fo4uQPaPLTQdv978YFrRiEHIFY1pzAR/GPotaskAPT G94g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VEAe/Lv2c2CBSNljT1Dh/BDQx27kgNBvj7a/gt32TaE=; fh=KhamMcu+afW+JcycbJwsIN7GCvQjQBx356VRODtXooA=; b=Vi/iNO8Qq5qYzoNqqDpvjQ+UJCs1OG89vC9kSvzhXRHRIA2tpc3v2rb2KyjV0O9PJN vNa+AQ4y2vtF20IVubrWXvWO6ESn+Sjjo+CKJlQ4hlOHpO1AkHlo4pcVlhENqr3bIfcY 1TYfljt0VdMEQL7503iSWZ9/fMgaO+cMqJEIsmVPrFDfxz0q/uWvGxiaJgzPjBaLS6p2 T7Dfx58StJ+ytZpCWZbh3kjZgj+9GKPiflxfO+nqT+JjQ31nT+JUQHCop6GAZfyiHAPr 0HYPcSE+px8nopUn2MCBFcdLSrmqnTOV+HMN3L2tjdphgQ+KBOSXa+UZl727zlT3k5FC z2zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eKp2dFfc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 05/16] drm/mediatek: gamma: Enable the Gamma LUT table only after programming Date: Thu, 12 Oct 2023 11:57:25 +0200 Message-ID: <20231012095736.100784-6-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:32 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543271811400697 X-GMAIL-MSGID: 1779543271811400697 Move the write to DISP_GAMMA_CFG to enable the Gamma LUT to after programming the actual table to avoid potential visual glitches during table modification. Note: GAMMA should get enabled in between vblanks, but this requires many efforts in order to make this happen, as that requires migrating all of the writes to make use of CMDQ instead of cpu writes and that's not trivial. For this reason, this patch only moves the LUT enable. The CMDQ rework will come at a later time. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 8506b9a0a811..d35eaf6dbc2d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -65,12 +65,12 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma; - unsigned int i, reg; + unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; bool lut_diff; u16 lut_size; - u32 word; + u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) @@ -87,9 +87,6 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt lut_size = 512; } - reg = readl(regs + DISP_GAMMA_CFG); - reg = reg | GAMMA_LUT_EN; - writel(reg, regs + DISP_GAMMA_CFG); lut_base = regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; for (i = 0; i < lut_size; i++) { @@ -119,6 +116,13 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt } writel(word, (lut_base + i * 4)); } + + cfg_val = readl(regs + DISP_GAMMA_CFG); + + /* Enable the gamma table */ + cfg_val |= GAMMA_LUT_EN; + + writel(cfg_val, regs + DISP_GAMMA_CFG); } void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) From patchwork Thu Oct 12 09:57:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151885 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104894vqb; Thu, 12 Oct 2023 02:58:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFvumSEONIT7kE3yguczPJXx5M0VA67XE/LZTjYb82R5DpNSviPcZ1Dx5NAcstsnoMqbtuI X-Received: by 2002:a17:902:e885:b0:1c0:bf60:ba82 with SMTP id w5-20020a170902e88500b001c0bf60ba82mr26730680plg.5.1697104716588; Thu, 12 Oct 2023 02:58:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104716; cv=none; d=google.com; s=arc-20160816; b=D+SDYFUxTN2jDFzqmfddx80MZnUascA1/NBUvwff7kl6Zkl5bM4msUv9pyk2d8+gce xERvaxwRoLlJbPCGF8+Nt26Eq8PIzmXa31qD+n2d78luTghA34liHW+Hzr1p6jI7UiKP DiugwjRZ+NevmOUeMEEj74jkhAT4i7dDAjeD0DtXniNKbF2vx9DWiuMbePM7Y4bEfeWy hDfnpM0eJbtxn+vLYCaT8vKO18otdXUwrLN659Nkxl4GLyw0Hs3mC78+YXb9jmHJcLXc RnbQ31qnBoyYJt2IotE/JT6ilEUaXmVF+Epr8yQ1eAbSsgbWlNiE03koMumWKHpz2Thz vkaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dKAov8pWlUyKpth2FpbcXa/Ca6ED23vE3e+YSPkUGis=; fh=bQWidIve/HFmt3CUWmgadT5Wp0aqqdoUxugz1+Q5vPs=; b=boJS8fv4CHCRfWGHBb5YqlcJbVOuTXDbxHicPtTFG73bFOSmyjHXBMgwAmYgtcdSa8 fPwb1hna9f1fMIgfHqpCgENk5P3nG6bo6olrKxcc3lOBwgcuHDhB8nB8vUdqquOLORSF fNboW3B7FN9Rva0KEUzK51U+i6qLtxfxsN+Zd/D7qTLx/2JP+Ou2YhRTi9xF0MB3XwA9 z7e+38s7Wdbel9PmxhxPbfjFv94ZMAYkJ/qsCbA1fFHAstFV2Y6xKEN8T2kXPrpz3CPI q3jZpFy7srEbRvD1j3PSYu0AqnbAL8z2VRl6zAQeQqwwgfjqW/TFn4WYeVP3KxEwMp4a 9n4g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=gYh9fZlT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from howler.vger.email (howler.vger.email. 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Lin" , Alexandre Mergnat Subject: [PATCH v11 06/16] drm/mediatek: gamma: Use bitfield macros Date: Thu, 12 Oct 2023 11:57:26 +0200 Message-ID: <20231012095736.100784-7-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:30 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543275467131447 X-GMAIL-MSGID: 1779543275467131447 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. While at it, also add a definition for LUT_BITS_DEFAULT. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 28 +++++++++++++++-------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index d35eaf6dbc2d..81c04518a5eb 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -3,6 +3,7 @@ * Copyright (c) 2021 MediaTek Inc. */ +#include #include #include #include @@ -21,8 +22,14 @@ #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 +#define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) +#define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) +#define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) +#define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) + struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; @@ -97,9 +104,9 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); if (!lut_diff || (i % 2 == 0)) { - word = hwlut.red << 20 + - hwlut.green << 10 + - hwlut.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); } else { diff.red = lut[i].red - lut[i - 1].red; diff.red = drm_color_lut_extract(diff.red, 10); @@ -110,9 +117,9 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt diff.blue = lut[i].blue - lut[i - 1].blue; diff.blue = drm_color_lut_extract(diff.blue, 10); - word = diff.blue << 20 + - diff.green << 10 + - diff.red; + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); } writel(word, (lut_base + i * 4)); } @@ -120,7 +127,7 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt cfg_val = readl(regs + DISP_GAMMA_CFG); /* Enable the gamma table */ - cfg_val |= GAMMA_LUT_EN; + cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); writel(cfg_val, regs + DISP_GAMMA_CFG); } @@ -137,9 +144,12 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); + u32 sz; + + sz = FIELD_PREP(DISP_GAMMA_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_GAMMA_SIZE_VSIZE, h); - mtk_ddp_write(cmdq_pkt, h << 16 | w, &gamma->cmdq_reg, gamma->regs, - DISP_GAMMA_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &gamma->cmdq_reg, gamma->regs, DISP_GAMMA_SIZE); if (gamma->data && gamma->data->has_dither) mtk_dither_set_common(gamma->regs, &gamma->cmdq_reg, bpc, DISP_GAMMA_CFG, GAMMA_DITHERING, cmdq_pkt); From patchwork Thu Oct 12 09:57:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151886 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104959vqb; 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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id h64-20020a638343000000b005891f64e423si1869691pge.781.2023.10.12.02.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:58:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=UMzZkGKN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 796948120441; Thu, 12 Oct 2023 02:58:37 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235656AbjJLJ6T (ORCPT + 19 others); Thu, 12 Oct 2023 05:58:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59898 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235605AbjJLJ5w (ORCPT ); Thu, 12 Oct 2023 05:57:52 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3CB5C0 for ; Thu, 12 Oct 2023 02:57:50 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id E958B6607351; Thu, 12 Oct 2023 10:57:48 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104669; bh=s51bMlmGO1xHv5GaAY9hJMRyrYqHvYtjxvhr5nY4WEI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UMzZkGKNx/Iusi03ckaJHrfpWbCP71+BrRJ5QZQY9niamh66UrO9JhI0zRcAGwNKi NvJ6pexjpSYgCe5PGfja65/kjs0kEz/WSeGBjrHU4QEQXw9y8Bzo7kPl2+0s60upI3 HiiUSTxaMIFBVwemhn5359brPxiJxB4F4xdoxYgz0UpsDwH6ghSzIdXi5CRyzR9Jl4 GUk0TJHaqfCWWKZ0bNOdE+qq1jySMICiG9PXZWaaE0r+5xZqB9qFuuSlzH3JGnM7Bl X+HomRwIfu1vGD5CyPN+2SVzlTAqY0Sn61si+vrFBivsQPHMByEaTdniPGxST6drZG lCV4Cm8OjFp6A== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, CK Hu Subject: [PATCH v11 07/16] drm/mediatek: aal: Use bitfield macros Date: Thu, 12 Oct 2023 11:57:27 +0200 Message-ID: <20231012095736.100784-8-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543285128267103 X-GMAIL-MSGID: 1779543285128267103 Make the code more robust and improve readability by using bitfield macros instead of open coding bit operations. Reviewed-by: CK Hu Reviewed-by: Nícolas F. R. A. Prado Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index dc26ddce0c6e..05f9be23fa47 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -18,6 +18,8 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) #define DISP_AAL_SIZE 0x0030 +#define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) +#define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 #define DISP_AAL_LUT_SIZE 512 @@ -51,9 +53,13 @@ void mtk_aal_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + u32 sz; - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); - mtk_ddp_write(cmdq_pkt, w << 16 | h, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); + sz = FIELD_PREP(DISP_AAL_SIZE_HSIZE, w); + sz |= FIELD_PREP(DISP_AAL_SIZE_VSIZE, h); + + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_SIZE); + mtk_ddp_write(cmdq_pkt, sz, &aal->cmdq_reg, aal->regs, DISP_AAL_OUTPUT_SIZE); } /** From patchwork Thu Oct 12 09:57:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151891 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105155vqb; Thu, 12 Oct 2023 02:59:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEI05Mi2ryTTvkqii5lne8KhgoS2Rtnxxx+1cjXdZM1hUoHPFGeM0UHBdSC136KXjFFsyGH X-Received: by 2002:a05:6a00:3985:b0:68f:c8b3:3077 with SMTP id fi5-20020a056a00398500b0068fc8b33077mr25411090pfb.1.1697104754602; Thu, 12 Oct 2023 02:59:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104754; cv=none; d=google.com; s=arc-20160816; b=a//0886Mc4jfA4N0EWX8uBJoaOiHuTfJ89eq6JGtqWLVPuBuzBtoYJQL2a0dI4FBXb 5JOmneRuOoNeVo3kZmrlIT2NgHoDS5T/xDQg4qoYXn/1xtMqvCHcvhNhz6pnwNTsxccE PSiz0RHViPO72V4FDCYKTSs+Mq1H0/HbKTSz9nCMfQXDEb7/tRYsz67Nfy0B4KsLMSs7 dpVJ+MSAQYQsiNAj/PAON4rMcmD6OzUi75r1NvB59VyuHXdFnmHDD2PUsweFWwBbBiLF DnvNlO0YuDBsgnIZL3OyeI42fEBAjhluF0YzSR+mkI3plkyo3dpaBNrwpJf903AaMhWI 5MHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=La1tCl2Df6I5M0VxE3Qfj0ERUNLAd5MIeKoGt3E7mno=; fh=/ex0owXp/r4cbV2B4nf4t7l5WFpbQiPvun1AWGbXjko=; b=iG7ujmzdiUEwOXVPCEge1GdDZfrf2R3SXwmdrItXcfLYrf7cBMjvxF6KK90GP0D3CE HbBlT4w3Pl6TjYZpRM0/lYg5Q6qVN8mItZWHNG9g0Jxo8AgHpkD3LGj5XNkuMkiZ+KZN XzDkvCjR4GpyX+szFH4RWVrotwDloK++G7OSb5YDtg2Fned7kszxhGaC0qaMF0JBrKYS x64gUPg8fwlLhI2nnDHNzGoavUKeIrid735bkXuYNDOUrS37rrqMfAMyPP547AYH0dgz 2kU4ldsbzKY7bkYGgDuJ4RF2nTgitWuNnn7LD2+dOFni6Lu+B4qnFXef5JTceREVHbzB Q0fw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=mDvO5LZU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id h71-20020a63834a000000b005859c8462f9si1992577pge.286.2023.10.12.02.59.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:59:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=mDvO5LZU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id EDEAE818BCB4; Thu, 12 Oct 2023 02:59:08 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235702AbjJLJ62 (ORCPT + 19 others); Thu, 12 Oct 2023 05:58:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59916 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235575AbjJLJ5x (ORCPT ); Thu, 12 Oct 2023 05:57:53 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A34A6CA for ; Thu, 12 Oct 2023 02:57:51 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id D3FCB6607356; Thu, 12 Oct 2023 10:57:49 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104670; bh=QCs4wI96fPs5unPYTZSQukv443uPSWfhQ3mtjInGcpk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mDvO5LZUBOAR4HnZNh5431O7PsLGsP1VfJSAYoETc54G2JtzJ8zMV6BYPX65WzXH0 zqaEWIhF7k32kjqlsDwjpnF702SSfcq7R4tyYC7PWmNkxQs8BIYcZtOhBFKV2c88FS eyhQaFMOS1FhOXtJAJIotxKUIIZ7IndYcm17JVcUH66JIPVJ657KVpBleiTg8LuN// dtiYGlTPsnDQmd01lDUNtPfJPxczyocxaYW7NXD2G99tJaCE5/0A3brAmYthcRTr0Z RJWvNgZDP7nCGXcRCuTbrLyye1/ElPBplfnXXhLnpe8w6Q9rdcRrg9aS+mY0gEvtau Uqdud4QWF666w== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com Subject: [PATCH v11 08/16] drm/mediatek: De-commonize disp_aal/disp_gamma gamma_set functions Date: Thu, 12 Oct 2023 11:57:28 +0200 Message-ID: <20231012095736.100784-9-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543314715053102 X-GMAIL-MSGID: 1779543314715053102 In preparation for adding a 12-bits gamma support for the DISP_GAMMA IP, remove the mtk_gamma_set_common() function and move the relevant bits in mtk_gamma_set() for DISP_GAMMA and mtk_aal_gamma_set() for DISP_AAL: since the latter has no more support for gamma manipulation (being moved to a different IP) in newer revisions, those functions are about to diverge and it makes no sense to keep a common one (with all the complications of passing common data and making exclusions for device driver data) for just a few bits. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Nícolas F. R. A. Prado Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 41 +++++++++++++++++++++-- drivers/gpu/drm/mediatek/mtk_disp_drv.h | 1 - drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 34 ++++--------------- 3 files changed, 46 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 05f9be23fa47..a618be9b3dba 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -17,10 +17,17 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) +#define DISP_AAL_CFG 0x0020 +#define AAL_GAMMA_LUT_EN BIT(1) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) #define DISP_AAL_SIZE_VSIZE GENMASK(12, 0) #define DISP_AAL_OUTPUT_SIZE 0x04d8 +#define DISP_AAL_GAMMA_LUT 0x0700 +#define DISP_AAL_GAMMA_LUT_R GENMASK(29, 20) +#define DISP_AAL_GAMMA_LUT_G GENMASK(19, 10) +#define DISP_AAL_GAMMA_LUT_B GENMASK(9, 0) +#define DISP_AAL_LUT_BITS 10 #define DISP_AAL_LUT_SIZE 512 struct mtk_disp_aal_data { @@ -80,9 +87,39 @@ unsigned int mtk_aal_gamma_get_lut_size(struct device *dev) void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_aal *aal = dev_get_drvdata(dev); + struct drm_color_lut *lut; + unsigned int i; + u32 cfg_val; + + /* If gamma is not supported in AAL, go out immediately */ + if (!(aal->data && aal->data->has_gamma)) + return; + + /* Also, if there's no gamma lut there's nothing to do here. */ + if (!state->gamma_lut) + return; + + lut = (struct drm_color_lut *)state->gamma_lut->data; + for (i = 0; i < DISP_AAL_LUT_SIZE; i++) { + struct drm_color_lut hwlut = { + .red = drm_color_lut_extract(lut[i].red, DISP_AAL_LUT_BITS), + .green = drm_color_lut_extract(lut[i].green, DISP_AAL_LUT_BITS), + .blue = drm_color_lut_extract(lut[i].blue, DISP_AAL_LUT_BITS) + }; + u32 word; + + word = FIELD_PREP(DISP_AAL_GAMMA_LUT_R, hwlut.red); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_G, hwlut.green); + word |= FIELD_PREP(DISP_AAL_GAMMA_LUT_B, hwlut.blue); + writel(word, aal->regs + DISP_AAL_GAMMA_LUT + i * 4); + } - if (aal->data && aal->data->has_gamma) - mtk_gamma_set_common(NULL, aal->regs, state); + cfg_val = readl(aal->regs + DISP_AAL_CFG); + + /* Enable the gamma table */ + cfg_val |= FIELD_PREP(AAL_GAMMA_LUT_EN, 1); + + writel(cfg_val, aal->regs + DISP_AAL_CFG); } void mtk_aal_start(struct device *dev) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h index ca377265e5eb..54d3712e2afd 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h @@ -56,7 +56,6 @@ void mtk_gamma_config(struct device *dev, unsigned int w, unsigned int bpc, struct cmdq_pkt *cmdq_pkt); unsigned int mtk_gamma_get_lut_size(struct device *dev); void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state); -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state); void mtk_gamma_start(struct device *dev); void mtk_gamma_stop(struct device *dev); diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 81c04518a5eb..0929f8830d6d 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -69,41 +69,28 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } -void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crtc_state *state) +void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { - struct mtk_disp_gamma *gamma; + struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - bool lut_diff; - u16 lut_size; u32 cfg_val, word; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; - /* If we're called from AAL, dev is NULL */ - gamma = dev ? dev_get_drvdata(dev) : NULL; - - if (gamma && gamma->data) { - lut_diff = gamma->data->lut_diff; - lut_size = gamma->data->lut_size; - } else { - lut_diff = false; - lut_size = 512; - } - - lut_base = regs + DISP_GAMMA_LUT; + lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < lut_size; i++) { + for (i = 0; i < gamma->data->lut_size; i++) { struct drm_color_lut diff, hwlut; hwlut.red = drm_color_lut_extract(lut[i].red, 10); hwlut.green = drm_color_lut_extract(lut[i].green, 10); hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); - if (!lut_diff || (i % 2 == 0)) { + if (!gamma->data->lut_diff || (i % 2 == 0)) { word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); @@ -124,19 +111,12 @@ void mtk_gamma_set_common(struct device *dev, void __iomem *regs, struct drm_crt writel(word, (lut_base + i * 4)); } - cfg_val = readl(regs + DISP_GAMMA_CFG); + cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); - writel(cfg_val, regs + DISP_GAMMA_CFG); -} - -void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) -{ - struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - - mtk_gamma_set_common(dev, gamma->regs, state); + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } void mtk_gamma_config(struct device *dev, unsigned int w, From patchwork Thu Oct 12 09:57:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151887 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104971vqb; Thu, 12 Oct 2023 02:58:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH1OQSWSG0k8AXYc1UK3E6xeyqH+RZfouJXVYSMnbvK5L/Sjr7CbagtoHVK3LWUlu6mehXB X-Received: by 2002:a05:6a20:4407:b0:133:6e3d:68cd with SMTP id ce7-20020a056a20440700b001336e3d68cdmr32386002pzb.3.1697104728376; Thu, 12 Oct 2023 02:58:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104728; cv=none; d=google.com; s=arc-20160816; b=yGhmb0vg9tXe5a2++pPYa+zOnOVG9aupFTq2SB3gt8hdxvpzi1a6MDOrO6XPYODxJt jJZjcqv/RhUNcdK36RycSSzz3kplcTvZekwA9PGfFSHHQANFBwW/kBnouOd+jofGr1ms aPAPY4fi7/dw15mNcl/S7eJ/J+slnACTGY6G460AdJwPs7n7LViNVW3Z0ss7LEXc//Qa LafAhWHS3ZQW64L9enYczzkwFjdNiiVM6xSsFqhCyAQZXpiMwBOWMK4TUN/a0Dmf1Fs/ Ahxfhdd4CDovYeJmkeRLcLV7DVsruHKTLsXBU6gHXhAiwdeoxb5XSMfsVAu+XL4z+UX8 TeoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FPqTkbtBXLVhMUV7hq+HoM3v6SzUyXuCev7aS1j/gEY=; fh=KhamMcu+afW+JcycbJwsIN7GCvQjQBx356VRODtXooA=; b=IspRYVq4h7Q2Jnw3FvNlMMrny+fPTygRdUIWuER9chUNSmESS1H+UK4ZlkN8KB5bAY gDC+WGuXn72NtIm5yiZDtzHFyV2CLaFEdil2UNKqI/HoPtHpZ6JH/oNPf9qrSRCDnoPx DpCRzc3Q0iLyF500NwMqSII66TKk01QXR6oXNOJdZzCUi2ATs5KP8ODOrF4kwwb8VpzC n1lt3A/DJ7LE8SlT1E/WbltvBw14hEHl67V/KB6LVK2QVZNzjYIPK2XhI54+sabSaxeu 1lMKTs9qkNQiNjRsJTKdp6VR101QyDG9oMaWGnwk9zofnYXHUf0qQxdcKqHXhCS6jXcz ILAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=E66JZ8dO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 09/16] drm/mediatek: gamma: Support multi-bank gamma LUT Date: Thu, 12 Oct 2023 11:57:29 +0200 Message-ID: <20231012095736.100784-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543287832225970 X-GMAIL-MSGID: 1779543287832225970 Newer Gamma IP have got multiple LUT banks: support specifying the size of the LUT banks and handle bank-switching before programming the LUT in mtk_gamma_set_common() in preparation for adding support for MT8195 and newer SoCs. Suggested-by: Jason-JH.Lin [Angelo: Refactored original commit] Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 70 ++++++++++++++--------- 1 file changed, 44 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 0929f8830d6d..911468984ad5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -24,6 +24,8 @@ #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) +#define DISP_GAMMA_BANK 0x0100 +#define DISP_GAMMA_BANK_BANK GENMASK(1, 0) #define DISP_GAMMA_LUT 0x0700 #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) @@ -33,6 +35,7 @@ struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; + u16 lut_bank_size; u16 lut_size; }; @@ -75,40 +78,53 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) unsigned int i; struct drm_color_lut *lut; void __iomem *lut_base; - u32 cfg_val, word; + u32 cfg_val, lbank_val, word; + int cur_bank, num_lut_banks; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; + num_lut_banks = gamma->data->lut_size / gamma->data->lut_bank_size; lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; - for (i = 0; i < gamma->data->lut_size; i++) { - struct drm_color_lut diff, hwlut; - - hwlut.red = drm_color_lut_extract(lut[i].red, 10); - hwlut.green = drm_color_lut_extract(lut[i].green, 10); - hwlut.blue = drm_color_lut_extract(lut[i].blue, 10); - - if (!gamma->data->lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); - } else { - diff.red = lut[i].red - lut[i - 1].red; - diff.red = drm_color_lut_extract(diff.red, 10); - - diff.green = lut[i].green - lut[i - 1].green; - diff.green = drm_color_lut_extract(diff.green, 10); - - diff.blue = lut[i].blue - lut[i - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, 10); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { + + /* Switch gamma bank and set data mode before writing LUT */ + if (num_lut_banks > 1) { + lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); + } + + for (i = 0; i < gamma->data->lut_bank_size; i++) { + int n = cur_bank * gamma->data->lut_bank_size + i; + struct drm_color_lut diff, hwlut; + + hwlut.red = drm_color_lut_extract(lut[n].red, 10); + hwlut.green = drm_color_lut_extract(lut[n].green, 10); + hwlut.blue = drm_color_lut_extract(lut[n].blue, 10); + + if (!gamma->data->lut_diff || (i % 2 == 0)) { + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } else { + diff.red = lut[n].red - lut[n - 1].red; + diff.red = drm_color_lut_extract(diff.red, 10); + + diff.green = lut[n].green - lut[n - 1].green; + diff.green = drm_color_lut_extract(diff.green, 10); + + diff.blue = lut[n].blue - lut[n - 1].blue; + diff.blue = drm_color_lut_extract(diff.blue, 10); + + word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } + writel(word, lut_base + i * 4); } - writel(word, (lut_base + i * 4)); } cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); @@ -208,10 +224,12 @@ static void mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, + .lut_bank_size = 512, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { + .lut_bank_size = 512, .lut_diff = true, .lut_size = 512, }; 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Lin" , Alexandre Mergnat Subject: [PATCH v11 10/16] drm/mediatek: gamma: Add support for 12-bit LUT Date: Thu, 12 Oct 2023 11:57:30 +0200 Message-ID: <20231012095736.100784-11-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543321657445809 X-GMAIL-MSGID: 1779543321657445809 New SoCs, like MT8195, not only may support bigger lookup tables, but have got a different register layout to support bigger precision: support specifying the number of `lut_bits` for each SoC and use it in mtk_gamma_set_common() to perform the right calculations and add support for 12-bit gamma lookup tables. While at it, also reorder the variables in mtk_gamma_set_common() and rename `lut_base` to `lut0_base` to improve readability. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 83 +++++++++++++++++------ 1 file changed, 64 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 911468984ad5..6305cd95e6d4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -26,17 +26,26 @@ #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) #define DISP_GAMMA_BANK 0x0100 #define DISP_GAMMA_BANK_BANK GENMASK(1, 0) +#define DISP_GAMMA_BANK_DATA_MODE BIT(2) #define DISP_GAMMA_LUT 0x0700 +#define DISP_GAMMA_LUT1 0x0b00 +/* For 10 bit LUT layout, R/G/B are in the same register */ #define DISP_GAMMA_LUT_10BIT_R GENMASK(29, 20) #define DISP_GAMMA_LUT_10BIT_G GENMASK(19, 10) #define DISP_GAMMA_LUT_10BIT_B GENMASK(9, 0) +/* For 12 bit LUT layout, R/G are in LUT, B is in LUT1 */ +#define DISP_GAMMA_LUT_12BIT_R GENMASK(11, 0) +#define DISP_GAMMA_LUT_12BIT_G GENMASK(23, 12) +#define DISP_GAMMA_LUT_12BIT_B GENMASK(11, 0) + struct mtk_disp_gamma_data { bool has_dither; bool lut_diff; u16 lut_bank_size; u16 lut_size; + u8 lut_bits; }; /* @@ -72,28 +81,48 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } +/* + * SoCs supporting 12-bits LUTs are using a new register layout that does + * always support (by HW) both 12-bits and 10-bits LUT but, on those, we + * ignore the support for 10-bits in this driver and always use 12-bits. + * + * Summarizing: + * - SoC HW support 9/10-bits LUT only + * - Old register layout + * - 10-bits LUT supported + * - 9-bits LUT not supported + * - SoC HW support both 10/12bits LUT + * - New register layout + * - 12-bits LUT supported + * - 10-its LUT not supported + */ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) { struct mtk_disp_gamma *gamma = dev_get_drvdata(dev); - unsigned int i; - struct drm_color_lut *lut; - void __iomem *lut_base; - u32 cfg_val, lbank_val, word; + void __iomem *lut0_base = gamma->regs + DISP_GAMMA_LUT; + void __iomem *lut1_base = gamma->regs + DISP_GAMMA_LUT1; + u32 cfg_val, data_mode, lbank_val, word[2]; + u8 lut_bits = gamma->data->lut_bits; int cur_bank, num_lut_banks; + struct drm_color_lut *lut; + unsigned int i; /* If there's no gamma lut there's nothing to do here. */ if (!state->gamma_lut) return; num_lut_banks = gamma->data->lut_size / gamma->data->lut_bank_size; - lut_base = gamma->regs + DISP_GAMMA_LUT; lut = (struct drm_color_lut *)state->gamma_lut->data; + /* Switch to 12 bits data mode if supported */ + data_mode = FIELD_PREP(DISP_GAMMA_BANK_DATA_MODE, !!(lut_bits == 12)); + for (cur_bank = 0; cur_bank < num_lut_banks; cur_bank++) { /* Switch gamma bank and set data mode before writing LUT */ if (num_lut_banks > 1) { lbank_val = FIELD_PREP(DISP_GAMMA_BANK_BANK, cur_bank); + lbank_val |= data_mode; writel(lbank_val, gamma->regs + DISP_GAMMA_BANK); } @@ -101,29 +130,43 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) int n = cur_bank * gamma->data->lut_bank_size + i; struct drm_color_lut diff, hwlut; - hwlut.red = drm_color_lut_extract(lut[n].red, 10); - hwlut.green = drm_color_lut_extract(lut[n].green, 10); - hwlut.blue = drm_color_lut_extract(lut[n].blue, 10); + hwlut.red = drm_color_lut_extract(lut[n].red, lut_bits); + hwlut.green = drm_color_lut_extract(lut[n].green, lut_bits); + hwlut.blue = drm_color_lut_extract(lut[n].blue, lut_bits); if (!gamma->data->lut_diff || (i % 2 == 0)) { - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + if (lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, hwlut.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, hwlut.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, hwlut.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, hwlut.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, hwlut.blue); + } } else { diff.red = lut[n].red - lut[n - 1].red; - diff.red = drm_color_lut_extract(diff.red, 10); + diff.red = drm_color_lut_extract(diff.red, lut_bits); diff.green = lut[n].green - lut[n - 1].green; - diff.green = drm_color_lut_extract(diff.green, 10); + diff.green = drm_color_lut_extract(diff.green, lut_bits); diff.blue = lut[n].blue - lut[n - 1].blue; - diff.blue = drm_color_lut_extract(diff.blue, 10); - - word = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); - word |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + diff.blue = drm_color_lut_extract(diff.blue, lut_bits); + + if (lut_bits == 12) { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_12BIT_G, diff.green); + word[1] = FIELD_PREP(DISP_GAMMA_LUT_12BIT_B, diff.blue); + } else { + word[0] = FIELD_PREP(DISP_GAMMA_LUT_10BIT_R, diff.red); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_G, diff.green); + word[0] |= FIELD_PREP(DISP_GAMMA_LUT_10BIT_B, diff.blue); + } } - writel(word, lut_base + i * 4); + writel(word[0], lut0_base + i * 4); + if (lut_bits == 12) + writel(word[1], lut1_base + i * 4); } } @@ -225,11 +268,13 @@ static void mtk_disp_gamma_remove(struct platform_device *pdev) static const struct mtk_disp_gamma_data mt8173_gamma_driver_data = { .has_dither = true, .lut_bank_size = 512, + .lut_bits = 10, .lut_size = 512, }; static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_bank_size = 512, + .lut_bits = 10, .lut_diff = true, .lut_size = 512, }; From patchwork Thu Oct 12 09:57:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151888 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1104997vqb; Thu, 12 Oct 2023 02:58:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkqZ0W6I3Gau+XL9twkB8dW+ihvP6uXPk69uGGbBwgq9pPU0VxHc8aPs/eVeCdE1xbjMex X-Received: by 2002:a17:902:f149:b0:1c9:d366:8ef5 with SMTP id d9-20020a170902f14900b001c9d3668ef5mr3530237plb.1.1697104731390; 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id x2-20020a170902fe8200b001c724f997ffsi1767147plm.131.2023.10.12.02.58.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:58:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=VaOuBimP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 62C0E821A140; Thu, 12 Oct 2023 02:58:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235674AbjJLJ6n (ORCPT + 19 others); Thu, 12 Oct 2023 05:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235618AbjJLJ54 (ORCPT ); Thu, 12 Oct 2023 05:57:56 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3F489D for ; Thu, 12 Oct 2023 02:57:54 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id BAAD96607346; Thu, 12 Oct 2023 10:57:52 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104673; bh=ThqabPr3bv/oVcU6bXeFf4cKumQAnz569b0Huyfi/jU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VaOuBimPm+qX4vFFVNcjeT9TJ0PEjrowb9R4N2duXjzKhh70KAKHfLZuXrPx239+h EpT3IJ3jH8Kp+vR1LQlwsCAz+ClpautF2O9iHgcZ/POJXM8Tem3ydCHASdYpyXJ8F6 OOLNIQuqn2tYdmHeI3AN8mLEA3+fCiqXQ6aE1xlCRI5JeGA5nzq/0D0HJ3SwGRpuX+ BwNd9XtF8EEpwGEMHHiSfxt2Wtcsg0f0nx+co55mDlVeNoE2wca3GyA7TD8MGqP7Mt bRy2fJds16k+bk+ebdxoRrHXvlxFKHLa9OaYNFsSX4eoRWBqmnlwtk4+7Am/PPJ6yV lpz0kR+oLwmsA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com Subject: [PATCH v11 11/16] drm/mediatek: gamma: Add support for MT8195 Date: Thu, 12 Oct 2023 11:57:31 +0200 Message-ID: <20231012095736.100784-12-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:58:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543291015456450 X-GMAIL-MSGID: 1779543291015456450 Now that this driver supports 12-bit LUTs, we can add support for the DISP_GAMMA found on the MT8195 SoC: add its driver data and compatible. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 6305cd95e6d4..bcc33aeca885 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -279,11 +279,20 @@ static const struct mtk_disp_gamma_data mt8183_gamma_driver_data = { .lut_size = 512, }; +static const struct mtk_disp_gamma_data mt8195_gamma_driver_data = { + .lut_bank_size = 256, + .lut_bits = 12, + .lut_diff = true, + .lut_size = 1024, +}; + static const struct of_device_id mtk_disp_gamma_driver_dt_match[] = { { .compatible = "mediatek,mt8173-disp-gamma", .data = &mt8173_gamma_driver_data}, { .compatible = "mediatek,mt8183-disp-gamma", .data = &mt8183_gamma_driver_data}, + { .compatible = "mediatek,mt8195-disp-gamma", + .data = &mt8195_gamma_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, mtk_disp_gamma_driver_dt_match); From patchwork Thu Oct 12 09:57:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151889 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105100vqb; Thu, 12 Oct 2023 02:59:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGv+voRRrCUg2xeCac4WfBIg86ohBtgWD9tumFx4rJNYiQL2XtD9qEwvwFy+qhsyKri1Kh5 X-Received: by 2002:a17:902:da87:b0:1c6:2902:24f9 with SMTP id j7-20020a170902da8700b001c6290224f9mr26867571plx.1.1697104746652; Thu, 12 Oct 2023 02:59:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104746; cv=none; d=google.com; s=arc-20160816; b=MrUqskn7VPzhwUd+6wlKONOcoVMcmIi9Oa3qRd96eQti3XnIDvAKquEXtI+CD/OFCV 3iDOFQ3C4NDZmsnidtDu6BP31Xn1zU3wcNnOmClEJpNKBfUMoXseyJP9WrcIGdKZNHqT kTc1xMII5KcRM9cGzZCVY/0YXLtAlgXYXQORtf3eYB8JHvZ9PCl4ymkJQ8oxBR5Z9L1p m8i8763OYZoM+qn6ylQX/NklIwvcIFSTTRLjhAfFOMp6WHcovcyBlHEHDlcka/6Kr2eH RH7d4TPgI8/DQWIw33HuvXr3qtr170Q5+gIXAQUFYk+AirMPfJsZRdLkyYY16CdglZVS xlzw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FJzKBxqQPBO/X/mfBXuQpi3PlOrt6qw31uT/6YMQtWM=; fh=KhamMcu+afW+JcycbJwsIN7GCvQjQBx356VRODtXooA=; b=C0JOC9xkKk27omEf+slMCR+1bKB/r3GlEi5odyL94ejKXF+S8eAUvni8T/7sdX8EJc UFWsC3u8WvfnIC5101nUP7zhOtcx3Lo3i4PUF3u4Pi/vHSa6J0IpVQrdn7iWXoLBc5WS QhufT3Wsaf2sJIuDyE1S7vrLsrOFXyVRICKwa/be5u9yROfEKs90yEyk9dA29L3XyCiw moE9eITvcakhRg8ztVbkIhLQPHNmQdGrWcZph0+REP/k0577n+XN5M23lVwVKQgdR6Pk WrYem1oIOGB5tzQpFxApfSOx0V6WtV9eE+Js75WFk4HGblBqdehFxcVMtFwSTX46/Udq gm6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=G+R5v+WP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from snail.vger.email (snail.vger.email. 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 12/16] drm/mediatek: gamma: Make sure relay mode is disabled Date: Thu, 12 Oct 2023 11:57:32 +0200 Message-ID: <20231012095736.100784-13-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543307096575068 X-GMAIL-MSGID: 1779543307096575068 Disable relay mode at the end of LUT programming to make sure that the processed image goes through in both DISP_GAMMA and DISP_AAL for gamma setting. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 4 ++++ drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index a618be9b3dba..15f91cea9f20 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -18,6 +18,7 @@ #define DISP_AAL_EN 0x0000 #define AAL_EN BIT(0) #define DISP_AAL_CFG 0x0020 +#define AAL_RELAY_MODE BIT(0) #define AAL_GAMMA_LUT_EN BIT(1) #define DISP_AAL_SIZE 0x0030 #define DISP_AAL_SIZE_HSIZE GENMASK(28, 16) @@ -119,6 +120,9 @@ void mtk_aal_gamma_set(struct device *dev, struct drm_crtc_state *state) /* Enable the gamma table */ cfg_val |= FIELD_PREP(AAL_GAMMA_LUT_EN, 1); + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~AAL_RELAY_MODE; + writel(cfg_val, aal->regs + DISP_AAL_CFG); } diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index bcc33aeca885..6746033615db 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -19,6 +19,7 @@ #define DISP_GAMMA_EN 0x0000 #define GAMMA_EN BIT(0) #define DISP_GAMMA_CFG 0x0020 +#define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) #define DISP_GAMMA_SIZE 0x0030 @@ -175,6 +176,9 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); + /* Disable RELAY mode to pass the processed image */ + cfg_val &= ~GAMMA_RELAY_MODE; + writel(cfg_val, gamma->regs + DISP_GAMMA_CFG); } From patchwork Thu Oct 12 09:57:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151890 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105157vqb; Thu, 12 Oct 2023 02:59:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFleWRd6FX6JmRiIyzL0adcH4xrqrIl3XdTzu2C+9oxrHSek95rvalNsIzX6sP93N6weBVm X-Received: by 2002:a05:6830:490e:b0:6c4:7516:f2cf with SMTP id eq14-20020a056830490e00b006c47516f2cfmr29108590otb.2.1697104754863; Thu, 12 Oct 2023 02:59:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104754; cv=none; d=google.com; s=arc-20160816; b=NiccECw1VJtVRXv9D9BFnrHEwl3U05I+oJ9RCoVNQKgM6hP/iqBXCUM3xFSiXsnNNd 5gpSrBTB1fr/5hYCj6lsZKEDrngXSTtXuq6PXWQspwHqg0rh6zR3YPt2rViFHvRtTGZY MDtK8nnJU73pFzu8bbYQTiD8So2Z6yLdW8LWo1KBOKUJaHvTbh+qLPlKB5VPUA+agyD4 2n1zAtW7LM959sLF+Zy8hWp8DBdkrMLQ94JwyAkQBF7iEIhsXy5YcGvcof9V7WvLCkLx oWAJtNzX7I+Qk34++FOSbgxks1C472HtKv3viM0GFvp6f5Bf/1eze2s3dR0aYDZlROyc YRoQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+I4c4zk1/ul2wYlG4nRZDeBLTa3NI6Ka5pPpYUr5+MU=; fh=KhamMcu+afW+JcycbJwsIN7GCvQjQBx356VRODtXooA=; b=sssMpsliKrF/zB/Pf6bxzPWyIAjCJN6OSbQtROEHmjsdM+zUOhWHuxFXZKhGx1gsAb Scs/y2D8B3gNQutqBcCtUv1kFxawbO5zkkEr5G/7fEw27iKcpJ4f52g3b+FBUHkun3t9 Ji3ISFnttviDJ6GgB6+toWmDx7EXBFE4H24eaIoQgw63WaVlwq/8N/1c3FXsx7UBNGP9 30nvlkbBmM/qAL4S5Sm4c6lGQMVzn7Qd8H8D1GevJG/gLo7hNHZvxSTe+HTzNbSnKO83 fGfPiZvbZF81pZvREgtQR2ljYgiGF8dfi+0ozoTM9qnIaSN5cru6dXy0nbpOkU5KYkv4 fvwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=eZKU5RSO; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from agentk.vger.email (agentk.vger.email. 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Lin" , Alexandre Mergnat , CK Hu Subject: [PATCH v11 13/16] drm/mediatek: gamma: Program gamma LUT type for descending or rising Date: Thu, 12 Oct 2023 11:57:33 +0200 Message-ID: <20231012095736.100784-14-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543315279420287 X-GMAIL-MSGID: 1779543315279420287 All of the SoCs that don't have dithering control in the gamma IP have got a GAMMA_LUT_TYPE bit that tells to the IP if the LUT is "descending" (bit set) or "rising" (bit cleared): make sure to set it correctly after programming the LUT. Reviewed-by: Jason-JH.Lin Reviewed-by: Alexandre Mergnat Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 6746033615db..0f116c0e51b5 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -22,6 +22,7 @@ #define GAMMA_RELAY_MODE BIT(0) #define GAMMA_LUT_EN BIT(1) #define GAMMA_DITHERING BIT(2) +#define GAMMA_LUT_TYPE BIT(2) #define DISP_GAMMA_SIZE 0x0030 #define DISP_GAMMA_SIZE_HSIZE GENMASK(28, 16) #define DISP_GAMMA_SIZE_VSIZE GENMASK(12, 0) @@ -82,6 +83,17 @@ unsigned int mtk_gamma_get_lut_size(struct device *dev) return 0; } +static bool mtk_gamma_lut_is_descending(struct drm_color_lut *lut, u32 lut_size) +{ + u64 first, last; + int last_entry = lut_size - 1; + + first = lut[0].red + lut[0].green + lut[0].blue; + last = lut[last_entry].red + lut[last_entry].green + lut[last_entry].blue; + + return !!(first > last); +} + /* * SoCs supporting 12-bits LUTs are using a new register layout that does * always support (by HW) both 12-bits and 10-bits LUT but, on those, we @@ -173,6 +185,14 @@ void mtk_gamma_set(struct device *dev, struct drm_crtc_state *state) cfg_val = readl(gamma->regs + DISP_GAMMA_CFG); + if (!gamma->data->has_dither) { + /* Descending or Rising LUT */ + if (mtk_gamma_lut_is_descending(lut, gamma->data->lut_size - 1)) + cfg_val |= FIELD_PREP(GAMMA_LUT_TYPE, 1); + else + cfg_val &= ~GAMMA_LUT_TYPE; + } + /* Enable the gamma table */ cfg_val |= FIELD_PREP(GAMMA_LUT_EN, 1); From patchwork Thu Oct 12 09:57:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151892 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105158vqb; Thu, 12 Oct 2023 02:59:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERK+jgAD8jkWBPNNkjAi0mBxupJJwDSxPQiJcnrWBAtlsMvQSLOKrRt5Zo//drMPoT5rCq X-Received: by 2002:a05:6830:3109:b0:6b9:db20:4d25 with SMTP id b9-20020a056830310900b006b9db204d25mr34216414ots.1.1697104754856; Thu, 12 Oct 2023 02:59:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104754; cv=none; d=google.com; s=arc-20160816; b=GSMizXv0wImrCRZKgPYQIZUMo+JSp2DP0pwLx5Xna/ius/5Gya9ULbF2JMn7wsXP3O HIn/2eM41dsqriz0GezyX6AEmB35I9/+uHwamtWcgb7fPCwnzKFjvAuirw5b/Xw8/Zzh Z72uixamN4uFkeXSCeA/WMCTr3d/LRudRQVvuZnMK96E1jQvD2hw7dQHXkKUlDEfbVL7 Izoxlvu/pJ9QoCt14coknJr4Bucw6vXnXfb4vb2DzUwOjdZCK5rqe90Z0Ske3BQexvaM as9TMvpILTOituC4veloAM9TYfRPM+r2xtvjgc61uSUU0LzBo5rq7nL4jAOZzPrs3Clz b/kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iCKuFwpY+ES1vmPepetvdi1pEhNshl/kLUS9j06eJFM=; fh=z5BwPHW+0WCeeOOYOk/t92kvrD91AUIcSucCefH7Wbk=; b=JR0Nk+MPW1AxTQS6j/HoEkPgUYl62ScEAuki/f6E7GGrYmEcJTzeZT1cMDmZYdISnG 0dSm2vSn5KF/bCQvX93LDBEmqsWCJanXhZrvY2ondz9oqBl187kIbNHuQ2g98AvmzgUQ TBG3dHuDFQqXu3KYQw++s3JYnFfoTOjDt9LzhO75AepdCD2mveVBvI6eIKl0Dmxp+UZL DZ3lJ0qpX8bULugTNS7yN7xlY/TjdQZp0Y/1/1xhA+3SG2qlkQbfRc2mpCD5FYUYE5IX PJas/Jal1Fo4sW2+rsz8o4YkubEOQM7THhEzHkqutPiWc38nSLBQzH2aI76mn2rsVvhB tLKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=KsNcUiyY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id y18-20020a056a001c9200b0067ff1a1ccbcsi13644523pfw.63.2023.10.12.02.59.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:59:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=KsNcUiyY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id AC73B83B8190; Thu, 12 Oct 2023 02:59:09 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1346972AbjJLJ65 (ORCPT + 19 others); Thu, 12 Oct 2023 05:58:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59972 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235635AbjJLJ6F (ORCPT ); Thu, 12 Oct 2023 05:58:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3487E8 for ; Thu, 12 Oct 2023 02:57:57 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B45C7660735F; Thu, 12 Oct 2023 10:57:55 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104676; bh=P77/YJTDYSmaGaK0qEws105RIsjmcoEYcEi31r4tRak=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KsNcUiyYcr5XDShO3jtR6lFvlbnttI8Bj9IT5wRcAVxxNmfrK1oSd5yYjKUcYc/M3 yoLfBUpSg2XIxz/PIgAFSLOCVf1/becsUAVE6cKNnlz16brkuRgMGGIw8quEFV9uUY ZUouCH6PbMiOfUVXo0+xdoLWaKb5PeoDBPvJQ/r5HnaQSYdTuOGZp5H9AYoo6mG9Rx OdsjXQAAutSbNy8jZiMSdIW9Hu2dEY9+XGjJaWyG91pwiag6C/rGlXD0c/DPjgvDpz BoJYCsTymG7C9a/xSyUD06ZBmomCwr6yEdu9urIwBnTEF3v4DYdKHtfsqf6lW6C41Q j4BvyIfh8FAcA== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, CK Hu Subject: [PATCH v11 14/16] drm/mediatek: aal: Add kerneldoc for struct mtk_disp_aal Date: Thu, 12 Oct 2023 11:57:34 +0200 Message-ID: <20231012095736.100784-15-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543315640550477 X-GMAIL-MSGID: 1779543315640550477 The kerneldoc for struct mtk_disp_aal is missing: write one and document this structure. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 15f91cea9f20..7b3e1c275056 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -35,6 +35,13 @@ struct mtk_disp_aal_data { bool has_gamma; }; + /** + * struct mtk_disp_aal - Display Adaptive Ambient Light driver structure + * @clk: clock for DISP_AAL controller + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform specific data for DISP_AAL + */ struct mtk_disp_aal { struct clk *clk; void __iomem *regs; From patchwork Thu Oct 12 09:57:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151895 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105250vqb; Thu, 12 Oct 2023 02:59:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEbuo2T+2xsypCpTiTYfJbI1Of2EsUtWknv/OiHIDtlRJzqw3ovZzCdL6pytvmLKFIH9p8h X-Received: by 2002:a05:6e02:9a:b0:357:4682:d128 with SMTP id bc26-20020a056e02009a00b003574682d128mr5141429ilb.1.1697104771023; Thu, 12 Oct 2023 02:59:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104770; cv=none; d=google.com; s=arc-20160816; b=JZiTflcmtYcddzVMZ80Zt4wjYWdhz1kl/eyGPumW/NkwfE+p/AEhaB3t2V5iCp+6Pl qCz85lxiltfUeh1Uzqrq/dmvt0RMX14BeL0D+3Aycbb4/Qsl1W20f6Blj0y1YCmrZY6F jOVs/Mgmg1rAdxLo4V8rjjIKcfhHniJRQTpm9UB/qnJfUpFkHUsHHwQGtV3f9SQC19Ck u1oDh0WUQKMU9sK283jqGkOHNEta2DYfjejozbkPmUbf2SE2gZgGV2G44zr8CKNF+g7B r5nB9RPqQmtc7HBb/3SdBlNgIoxyckDIHdBjUy5LLK1KZ1s2Fyf6mlQdl+fNxBqVeOPS 0Ibw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tC1lj0m2VhvjV4gf68aGW3sa41PB5VL+AjcUK/nICj4=; fh=z5BwPHW+0WCeeOOYOk/t92kvrD91AUIcSucCefH7Wbk=; b=Cr6tMqmUHvYKBKW4u7N808MwUNouV0RWAUyTRT9wXlbQZcbPrJM4zCp0WCOIMMX1uV kWKLqyIHlIToojc26fwIe1izkWBbovTg/iw85CX/QJrRTrXzVLjIcmbGbprW17CGVMLx nbYICE4UNINvIMFc4WhEMzQJ3NfzCuTV4j8PRU2Pt3thd/mZdIN74F31e0jKXMLgri4+ abBXH00uAP6Jib0SKaVXYbpNL0DX7sFar+Jv3J8nv70bapI0CaPHRrYRKrclIJCfAOhC AhaPm5hmn2GF/+f+djA7oONv1Xt8pvpc87g7S3LGB6vl5p55ORN3kKKp2X5wRoJ3l2wn 9aYA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="LDRmH/+X"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id v135-20020a63618d000000b005784d9e065dsi1880861pgb.25.2023.10.12.02.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:59:30 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b="LDRmH/+X"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 601E481904D6; Thu, 12 Oct 2023 02:59:24 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343619AbjJLJ7H (ORCPT + 19 others); Thu, 12 Oct 2023 05:59:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235669AbjJLJ6F (ORCPT ); Thu, 12 Oct 2023 05:58:05 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FB59ED for ; Thu, 12 Oct 2023 02:57:58 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id A76036607353; Thu, 12 Oct 2023 10:57:56 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104677; bh=F86yWw2q9jRPtZJ/+Z1yLORSlOTQBx0C3WCmrGPVXMo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LDRmH/+XLLQ8NVYfRr/Kni7gONMnyJ9bi/N3lXRnNeDQlmehZoP++yqJIQTXKy/Wo CX7K+DXcbNviXcrRYIF1QktlhT/IbCXaX42ZCy4gTL/imQIPsEDDdeqldWMAD+Kg7M g7pO3XQ0DxbxfKrmLSaDqYZBassxSP5ZKuuiDPxUJVQ0izlvC53rLqmp2/j6AnXeah xyIfcMKbkgUKQqoJCB2Sfv9hZ6+Ocg0a51fDfO1FJXRxKcCyp8XqmmRc4MHHToRAMk oeLt9m0A0sX+5jn8+2NKHwp5VMEFbQobvCkQHQGFTdNCggiTbjGjza/mP4YfcLWeh3 vbQ49hOTaQLFw== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, CK Hu Subject: [PATCH v11 15/16] drm/mediatek: gamma: Add kerneldoc for struct mtk_disp_gamma Date: Thu, 12 Oct 2023 11:57:35 +0200 Message-ID: <20231012095736.100784-16-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:24 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543332242674895 X-GMAIL-MSGID: 1779543332242674895 The mtk_disp_gamma structure was completely undocumented: add some kerneldoc documentation to it. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_gamma.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c index 0f116c0e51b5..52c752bc5f41 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_gamma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_gamma.c @@ -50,8 +50,12 @@ struct mtk_disp_gamma_data { u8 lut_bits; }; -/* - * struct mtk_disp_gamma - DISP_GAMMA driver structure +/** + * struct mtk_disp_gamma - Display Gamma driver structure + * @clk: clock for DISP_GAMMA block + * @regs: MMIO registers base + * @cmdq_reg: CMDQ Client register + * @data: platform data for DISP_GAMMA */ struct mtk_disp_gamma { struct clk *clk; From patchwork Thu Oct 12 09:57:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 151893 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp1105191vqb; Thu, 12 Oct 2023 02:59:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE4kULhfwUgiBbOYyk4cEHHx5TScd5Qmg0BkLO+3gdxX7uBzMcsczI/ABeflHMQvdf1Q230 X-Received: by 2002:a05:6a00:3985:b0:68f:c8b3:3077 with SMTP id fi5-20020a056a00398500b0068fc8b33077mr25411205pfb.1.1697104759664; Thu, 12 Oct 2023 02:59:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697104759; cv=none; d=google.com; s=arc-20160816; b=GPE0ILfyTEYIFWfPsO2GZfbpMc7Ll0CDqNea5oYfK4C1GZpRhycIb58b1Ex/iY9R8N Qu9dvl1IpzKmCrQ9KMWA5GAbK5JXPSMs2fOsjhAvcVuG5qehDUqFY0g1cZnm5IiV7JC6 GfyrT+8LlVyTTzbLZDXMO4frT6ku+DYagLJTpF2/ph11QbDnPq/0w5WeGpPJfeHVfSiX PlpiVHF6l7LAaA1a/OR2dOA+l1ha2Hx1XdWG9Bu8FCQFRdoky5MuhC2X3juPcrdainvy mq8hDLyauoWnp4b3gjCueGzHenmLRccYpx0rOsum6sWnq2EqTzvmN3uVOpABIEqIlkWC UQ7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8fOE0s2BG+dmz4IVJKd7oC1YWT04fOmf0YyPieb6z3o=; fh=z5BwPHW+0WCeeOOYOk/t92kvrD91AUIcSucCefH7Wbk=; b=UMHRU5fMrq4RRWFm2YvNkgMG7rR8AEfA7mTkF5+QGfCDvd3xRtnZOty9ILygAfKmJh ldUsAeN+hgHExTbeqWpI0NJmQXx9FDP+Y65ptIWMnsOkNiYpKrFQfSXU/nRj5kxFjU4e yNENHafX703mvLUluF/c5UJz5GDFI+eXYlRafRiIdA/x7dRTkAwk82le7NMaWEwvY9sl ndwjFaNcDOR2K5z9cmsi/aqxpMjbsgocvVA4K6liXv3l/rBhlziYdmO0zOiaSb/JGHmb d3kfvPSSjQdpbG4S/Nup/PUqHjcL9JOrS8tM0+euZizhFFUeFFcVGhNpx7jeOAm5NMA6 hsYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SKGyDy9o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id d2-20020a63d702000000b00578d0d070f7si915441pgg.659.2023.10.12.02.59.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Oct 2023 02:59:19 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=SKGyDy9o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 2C9FE8256C99; Thu, 12 Oct 2023 02:59:15 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235636AbjJLJ7D (ORCPT + 19 others); Thu, 12 Oct 2023 05:59:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235680AbjJLJ6L (ORCPT ); Thu, 12 Oct 2023 05:58:11 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7F066FC for ; Thu, 12 Oct 2023 02:57:59 -0700 (PDT) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 984976607362; Thu, 12 Oct 2023 10:57:57 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1697104678; bh=yTuzr7kwQWHUl8HtZXARUiw4vwCiedeVUiWy+PyIDto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SKGyDy9ocMehP5Q106HwzwZAExymO3OnWVdnh8WmarSyzztnnoin1zD/e8IBFqTy5 8TNsvNWL6ADTgCxAd6Kcg9uk0urAqKIQWctJb5iTm8PI/eYlShc3Ga22CMU+g6J+5p aS+8kXeHZg95Bcf5mYMgnUDeYNWIwVm87hm3y3XqQ04sKWvdkSDCEI+2WhPbeGaqet GvGJE2K3oB1jiwBWddeCb3lhscvtcHCp3orcnnEKPKLn0LsS2nrADLeToB0W7F1eGJ dOY8IF2vS4Q7OpKgTGA19vV3coVFVE3tV01AJau9CZ4vRCUb60j2rpEiMfxu+u6m5V rAfGReDSOxKFg== From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, wenst@chromium.org, kernel@collabora.com, ehristev@collabora.com, nfraprado@collabora.com, CK Hu Subject: [PATCH v11 16/16] drm/mediatek: aal: Compress of_device_id entries and add sentinel Date: Thu, 12 Oct 2023 11:57:36 +0200 Message-ID: <20231012095736.100784-17-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> References: <20231012095736.100784-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 12 Oct 2023 02:59:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779543320194412185 X-GMAIL-MSGID: 1779543320194412185 Compress the entry for mediatek,mt8173-disp-aal, as it fits in one line, and fix the style; while at it, also add the usual sentinel comment to the last entry. This commit brings no functional changes. Reviewed-by: CK Hu Signed-off-by: AngeloGioacchino Del Regno --- drivers/gpu/drm/mediatek/mtk_disp_aal.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_aal.c b/drivers/gpu/drm/mediatek/mtk_disp_aal.c index 7b3e1c275056..677e7d378e7a 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_aal.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_aal.c @@ -209,10 +209,9 @@ static const struct mtk_disp_aal_data mt8173_aal_driver_data = { }; static const struct of_device_id mtk_disp_aal_driver_dt_match[] = { - { .compatible = "mediatek,mt8173-disp-aal", - .data = &mt8173_aal_driver_data}, - { .compatible = "mediatek,mt8183-disp-aal"}, - {}, + { .compatible = "mediatek,mt8173-disp-aal", .data = &mt8173_aal_driver_data }, + { .compatible = "mediatek,mt8183-disp-aal" }, + { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, mtk_disp_aal_driver_dt_match);