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[2620:137:e000::1:20]) by mx.google.com with ESMTP id f8-20020a056a0022c800b00557eeba9fa4si9358409pfj.91.2022.11.06.18.35.54; Sun, 06 Nov 2022 18:36:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230222AbiKGCeR (ORCPT + 99 others); Sun, 6 Nov 2022 21:34:17 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53566 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbiKGCeQ (ORCPT ); Sun, 6 Nov 2022 21:34:16 -0500 Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 076CA2BDC; Sun, 6 Nov 2022 18:34:13 -0800 (PST) Received: from loongson.cn (unknown [10.20.42.77]) by gateway (Coremail) with SMTP id _____8Dxu9ihbmhjfO0EAA--.16207S3; Mon, 07 Nov 2022 10:34:09 +0800 (CST) Received: from loongson-PC.loongson.cn (unknown [10.20.42.77]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxr+Ccbmhj2D0OAA--.40061S2; Mon, 07 Nov 2022 10:34:09 +0800 (CST) From: Liu Peibao To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui Cc: Jianmin Lv , Yinbo Zhu , Liu Peibao , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/2] irqchip: loongarch-cpu: add DT support Date: Mon, 7 Nov 2022 10:34:03 +0800 Message-Id: <20221107023404.26730-1-liupeibao@loongson.cn> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dxr+Ccbmhj2D0OAA--.40061S2 X-CM-SenderInfo: xolx1vpled0qxorr0wxvrqhubq/1tbiAQABCmNmUmQAPwAGsA X-Coremail-Antispam: 1Uk129KBjvJXoW7Cw4fCw1fZFyUXryxAF48Crg_yoW8Jw13pa y7u3yavr1xJFnrWwn3C345Wr9Ivr1rK3y2qayfKa4Skrs8G34DZF10yF9xuFs5C3y3JF12 9F18tF18uF15JFDanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU b7xYFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVWUCVW8JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UM2AI xVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41l42xK82IYc2Ij64vIr41l4I8I3I 0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWU GVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI 0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0 rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r 4UYxBIdaVFxhVjvjDU0xZFpf9x07j1WlkUUUUU= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748803065441785553?= X-GMAIL-MSGID: =?utf-8?q?1748803065441785553?= LoongArch is coming to support booting with FDT, so DT support of this driver is desired. Signed-off-by: Liu Peibao --- drivers/irqchip/irq-loongarch-cpu.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/irqchip/irq-loongarch-cpu.c b/drivers/irqchip/irq-loongarch-cpu.c index 741612ba6a52..a28b7c549654 100644 --- a/drivers/irqchip/irq-loongarch-cpu.c +++ b/drivers/irqchip/irq-loongarch-cpu.c @@ -92,6 +92,25 @@ static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = { .xlate = irq_domain_xlate_onecell, }; +#ifdef CONFIG_OF +int __init loongarch_cpu_irq_of_init(struct device_node *of_node, + struct device_node *parent) +{ + cpuintc_handle = of_node_to_fwnode(of_node); + + irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM, + &loongarch_cpu_intc_irq_domain_ops, NULL); + if (!irq_domain) + panic("Failed to add irqdomain for loongarch CPU"); + + set_handle_irq(&handle_cpu_irq); + + return 0; +} +IRQCHIP_DECLARE(cpu_intc, "loongson,cpu-interrupt-controller", + loongarch_cpu_irq_of_init); +#endif + static int __init liointc_parse_madt(union acpi_subtable_headers *header, const unsigned long end) From patchwork Mon Nov 7 02:34:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liu Peibao X-Patchwork-Id: 16220 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1790435wru; Sun, 6 Nov 2022 18:36:36 -0800 (PST) X-Google-Smtp-Source: AMsMyM4WkuBTeu8XgAs8LoWAjAlzo0cN1he/4+kwQTWdT+nAVLBbc0dic9VvFwBSRoWd6moM3nN5 X-Received: by 2002:a17:903:2489:b0:187:3a59:570a with SMTP id p9-20020a170903248900b001873a59570amr30484550plw.35.1667788596557; Sun, 06 Nov 2022 18:36:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667788596; cv=none; d=google.com; s=arc-20160816; b=zqpbFmnb9QvWFWjqSyI4OmIhhkVTPLsT555Xnn9JWEhkMqKUPjVTbSPwjKW+h0i7gM Xm9WUELmilqGujJ/4Quyv5vrzFbtmYJR+NLSd4jEAwt0Wtccqp3p7dIIGKTsm8cekAVa js9r3UVzjZhBRfMgOPhNGXXohiaz+l9/fcDCqtKv4sB0w0iNl1UDKiQGF593sBRjP8Zw 76UuNrVTHQEqLhh/punqYKEc8WFnwMgOgeIwPVcNlKgxYD3eqwKzN81JoS49IKCM6b5o PpWdPyy//34OsOV8mm6GUhT7uPz0YWMPW8BCe0PNPfHgqpXgN0VK4bTBUGoNWMGiwqcZ cwAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=ZazwhyD1sbuBagdTWwpeaT6Ghcbp/acmFgdqcBh0AFk=; b=em0kp1yj0391WxY0Lf4ya9o2TG9GKAdTScq9YG808324f36w82NHvqNSTQlBGTY7za WVgBx6kUz5SQYUiJOJ3lheFU7Qvo4dZCYbQOjS4ZDA0OjFqBrK7nnCREt+GDOIskgS39 xQ1TnS8U9JxZs4ac3vtc5SnAdtZAVr78xJobjmaXtS5VnEbMvBTKlXgw2D95W8kY8pGw g73WZq6f5w38qNuLrHeofbQTTL0xi2kjSewkBlCwlXilC7qLiHigbqn9wUn61PIhmoX5 nvxXLkt96caCynVoJePzfpxFag4UeHGZrN/DI8vgahYjjE1G2YYWzHvtN4R5Dmr9Qj+e BNzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Sun, 6 Nov 2022 18:34:12 -0800 (PST) Received: from loongson.cn (unknown [10.20.42.77]) by gateway (Coremail) with SMTP id _____8Axz7ejbmhjgu0EAA--.11534S3; Mon, 07 Nov 2022 10:34:11 +0800 (CST) Received: from loongson-PC.loongson.cn (unknown [10.20.42.77]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dxr+Ccbmhj2D0OAA--.40061S3; Mon, 07 Nov 2022 10:34:09 +0800 (CST) From: Liu Peibao To: Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui Cc: Jianmin Lv , Yinbo Zhu , Liu Peibao , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller Date: Mon, 7 Nov 2022 10:34:04 +0800 Message-Id: <20221107023404.26730-2-liupeibao@loongson.cn> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20221107023404.26730-1-liupeibao@loongson.cn> References: <20221107023404.26730-1-liupeibao@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dxr+Ccbmhj2D0OAA--.40061S3 X-CM-SenderInfo: xolx1vpled0qxorr0wxvrqhubq/1tbiAQADCmNno+QHGAAAsU X-Coremail-Antispam: 1Uk129KBjvJXoW7CFy5Gw4xKF17Gw1kWrWfZrb_yoW8CF1kpF W7CanxWF40qF43Cws2ga40krnxZFnxJrna9ws3tw47Gr1ag343XFW29F95JFW8GrZ2qw17 Z3WFv3W0q3ZrJF7anT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj qI5I8CrVACY4xI64kE6c02F40Ex7xfYxn0WfASr-VFAUDa7-sFnT9fnUUIcSsGvfJTRUUU bS8YFVCjjxCrM7AC8VAFwI0_Jr0_Gr1l1xkIjI8I6I8E6xAIw20EY4v20xvaj40_Wr0E3s 1l1IIY67AEw4v_Jrv_JF1l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2x7M28EF7xv wVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVW8JVWxJwA2z4 x0Y4vEx4A2jsIE14v26F4j6r4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJwAa w2AFwI0_Jrv_JF1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqjxCEc2xF0cIa020Ex4CE44 I27wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcVAFwI0_Jw0_WrylYx0Ex4A2 jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG0xvY0x0EwIxGrwCY1x0262 kKe7AKxVWUAVWUtwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwCFI7km 07C267AKxVWUXVWUAwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r 1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWU CVW8JwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r 1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1U YxBIdaVFxhVjvjDU0xZFpf9x07jrcTPUUUUU= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748803095601193812?= X-GMAIL-MSGID: =?utf-8?q?1748803095601193812?= Signed-off-by: Liu Peibao --- .../loongarch,cpu-interrupt-controller.yaml | 42 +++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml new file mode 100644 index 000000000000..30b742661a3f --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LoongArch CPU Interrupt Controller + +description: > + On LoongArch the loongarch_cpu_irq_of_init() helper can be used to initialize + the 14 CPU IRQs from a devicetree file and create a irq_domain for this IRQ + controller. + + With the irq_domain in place we can describe how the 14 IRQs are wired to the + platforms internal interrupt controller cascade. + +maintainers: + - Liu Peibao + +properties: + compatible: + const: loongarch,cpu-interrupt-controller + + '#interrupt-cells': + const: 1 + + interrupt-controller: true + +additionalProperties: false + +required: + - compatible + - '#interrupt-cells' + - interrupt-controller + +examples: + - | + interrupt-controller { + compatible = "loongarch,cpu-interrupt-controller"; + #interrupt-cells = <1>; + interrupt-controller; + };