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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id g7-20020a170906594700b009b92b7579b4si6407734ejr.25.2023.10.11.15.38.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 15:38:45 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=CYNaQwBK; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 8C2773875453 for ; Wed, 11 Oct 2023 22:27:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id 6DB533858434 for ; Wed, 11 Oct 2023 22:26:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 6DB533858434 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=ventanamicro.com Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1c62d61dc96so2681275ad.0 for ; Wed, 11 Oct 2023 15:26:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697063206; x=1697668006; darn=gcc.gnu.org; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:from:to:cc:subject:date:message-id:reply-to; bh=gFl+2kmoGpff6pXNEotKmc+nIiTNgaaJEJXAtdZCwNI=; b=CYNaQwBKspSO5jSP03pIGpTunVy3s9b44oYBmvFqhgGcFBDHas8USeID4ZXt31qOX2 upRE9g2J05yPCz1so/NwSf8luxr8cSa4xd9jiG/lfoDSdxMS0gkIayoNO6IsqSQmULUi auSyx7uOyHhrwt96YsvpW7NMYHCkMRbZItQh6Asa12r06mDhx63QUEO3Iub4r8ZOjqwS kLDv9UBdo7Hdy1m3HiDqh+WId8MBEryctZUDn5ctZfvt+xKCXmw2wxo7LkCjLTks+4Ui DA4O0jPC5AeGnHVUC3M2wwf08A9eD6vftsFlkDZjtsxJMujMWEhu+WWjdTJpFz3ErAWH yA9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697063206; x=1697668006; h=to:subject:from:content-language:user-agent:mime-version:date :message-id:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=gFl+2kmoGpff6pXNEotKmc+nIiTNgaaJEJXAtdZCwNI=; b=icBrGAF0brKYH3yjFM1OJSd8g6ifTQRfiKbT7VutEvYwXfVrvCGXm0p8EEOX+eF6HO eg5GrWJW8501NO9ZK/OkXvpnsntrdNZ2mWrXvArzJYr6Yq1EsmElzp0fxVvcIWieAgsV GIdkD2lRU/i5azbRXQv/UJAuf4InOE+1Ch9HKjonM+fHenpOGM/4yu2t6hqki2OBtz5p XKf9hsxJcRxsy2i/sWPqVgOnm83rn5d6Ee4sHvgmO1U/4ZqtcvQNsAhAESiRNfevg+Uy TOyrYtkWs19FSZG/95R9zL2pZDsXNO4I26/wwQtkqXwO/29ajI6bHwCRycRKBGeqjJcW 8tQw== X-Gm-Message-State: AOJu0Yz36sX6W0YSCZJkgzkPMLlsgAby4mMJvZybj+AMcdgCTBrfMRHj 21MF5iVFfdH6WCfHa85MjGcURnOf7mZZ7zNtA9o= X-Received: by 2002:a17:902:e5cc:b0:1c8:a06e:fce9 with SMTP id u12-20020a170902e5cc00b001c8a06efce9mr10357080plf.52.1697063205959; Wed, 11 Oct 2023 15:26:45 -0700 (PDT) Received: from [172.31.0.109] ([136.36.130.248]) by smtp.gmail.com with ESMTPSA id ju1-20020a170903428100b001b9d335223csm368701plb.26.2023.10.11.15.26.43 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Oct 2023 15:26:45 -0700 (PDT) Message-ID: <04984416-680a-4768-92fb-95daab4c4017@ventanamicro.com> Date: Wed, 11 Oct 2023 16:26:41 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Content-Language: en-US From: Jeff Law Subject: [committed] RISC-V: Adjust long unconditional branch sequence To: "gcc-patches@gcc.gnu.org" X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779500502613370119 X-GMAIL-MSGID: 1779500502613370119 Andrew and I independently noted the long unconditional branch sequence was using the "call" pseudo op. Technically it works, but it's a bit odd. This patch flips it to use the "jump" pseudo-op. This was tested with a hacked-up local compiler which forced all branches/jumps to be long jumps. Naturally it triggered some failures for scan-asm tests but no execution regressions (which is mostly what I was testing for). I've updated the long branch support item in the RISE wiki to indicate that we eventually want a register scavenging approach with a fallback to $ra in the future so that we don't muck up the return address predictors. It's not super-high priority and shouldn't be terrible to implement given we've got the $ra fallback when a suitable register can not be found. Pushed to the trunk, Jeff commit a3e50ee96dc3e25ca52608e58c4e653f9976cb4e Author: Jeff Law Date: Wed Oct 11 16:18:22 2023 -0600 RISC-V Adjust long unconditional branch sequence Andrew and I independently noted the long unconditional branch sequence was using the "call" pseudo op. Technically it works, but it's a bit odd. This patch flips it to use the "jump" pseudo-op. This was tested with a hacked-up local compiler which forced all branches/jumps to be long jumps. Naturally it triggered some failures for scan-asm tests but no execution regressions (which is mostly what I was testing for). I've updated the long branch support item in the RISE wiki to indicate that we eventually want a register scavenging approach with a fallback to $ra in the future so that we don't muck up the return address predictors. It's not super-high priority and shouldn't be terrible to implement given we've got the $ra fallback when a suitable register can not be found. gcc/ * config/riscv/riscv.md (jump): Adjust sequence to use a "jump" pseudo op instead of a "call" pseudo op. diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c26541bd5ce..23d91331290 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2924,7 +2924,7 @@ (define_insn "jump" /* Hopefully this does not happen often as this is going to clobber $ra and muck up the return stack predictors. */ if (get_attr_length (insn) == 8) - return "call\t%l0"; + return "jump\t%l0,ra"; return "j\t%l0"; }