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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id wy8-20020a170906fe0800b00791a7e441a3si7620414ejb.459.2022.11.06.17.42.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 17:42:10 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=CkJWoX+R; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7C00B38582A2 for ; Mon, 7 Nov 2022 01:42:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7C00B38582A2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667785324; bh=k+ep+Zh1Sfyntw/WI0oJl4gLvYvNaGrxV1iVp4r3Mzs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=CkJWoX+RF1OY0o7dwFba0Omv8hshsQXEvGeAsVJNyXOvmOo4AH1QjygnXZTepY2Fl dTKGoRIiFTTHobw28vTvAA48+i7bfci1FpXwyfY39GwLO5x93oA08Rua12oLHo5jrq NirrsNmLWVdsuJXJhAMU9VFhrA4HPnHueJsBoX08= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id CF2393858C74 for ; Mon, 7 Nov 2022 01:41:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CF2393858C74 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="396601347" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="396601347" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2022 17:41:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="880887332" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="880887332" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga006.fm.intel.com with ESMTP; 06 Nov 2022 17:41:17 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 31D0B1005674; Mon, 7 Nov 2022 09:41:16 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 1/2] Initial Grand Ridge support Date: Mon, 7 Nov 2022 09:41:13 +0800 Message-Id: <20221107014114.71155-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221107014114.71155-1-haochen.jiang@intel.com> References: <20221107014114.71155-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748799671256264399?= X-GMAIL-MSGID: =?utf-8?q?1748799671256264399?= gcc/ChangeLog: * common/config/i386/i386-common.cc (processor_names): Add grandridge. (processor_alias_table): Ditto. * common/config/i386/i386-cpuinfo.h: (enum processor_types): Add INTEL_GRANDRIDGE. * config.gcc: Add -march=grandridge. * config/i386/driver-i386.cc (host_detect_local_cpu): Handle grandridge. * config/i386/i386-c.cc (ix86_target_macros_internal): Ditto. * config/i386/i386-options.cc (m_GRANDRIDGE): New define. (processor_cost_table): Add grandridge. * config/i386/i386.h (enum processor_type): Add PROCESSOR_GRANDRIDGE. (PTA_GRANDRIDGE): Ditto. * doc/extend.texi: Add grandridge. * doc/invoke.texi: Ditto. gcc/testsuite/ChangeLog: * gcc/testsuite/g++.target/i386/mv16.C: Add grandridge. * gcc.target/i386/funcspec-56.inc: Handle new march. --- gcc/common/config/i386/cpuinfo.h | 6 ++++++ gcc/common/config/i386/i386-common.cc | 3 +++ gcc/common/config/i386/i386-cpuinfo.h | 1 + gcc/config.gcc | 2 +- gcc/config/i386/driver-i386.cc | 5 ++++- gcc/config/i386/i386-c.cc | 7 +++++++ gcc/config/i386/i386-options.cc | 2 ++ gcc/config/i386/i386.h | 2 ++ gcc/doc/extend.texi | 3 +++ gcc/doc/invoke.texi | 9 +++++++++ gcc/testsuite/g++.target/i386/mv16.C | 6 ++++++ gcc/testsuite/gcc.target/i386/funcspec-56.inc | 1 + 12 files changed, 45 insertions(+), 2 deletions(-) diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index df3500adc83..4d1bcffb978 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -573,6 +573,12 @@ get_intel_cpu (struct __processor_model *cpu_model, cpu_model->__cpu_type = INTEL_COREI7; cpu_model->__cpu_subtype = INTEL_COREI7_GRANITERAPIDS; break; + case 0xb6: + /* Grand Ridge. */ + cpu = "grandridge"; + CHECK___builtin_cpu_is ("grandridge"); + cpu_model->__cpu_type = INTEL_GRANDRIDGE; + break; case 0x17: case 0x1d: /* Penryn. */ diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 60a193a651c..431fd0d3ad1 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -1920,6 +1920,7 @@ const char *const processor_names[] = "goldmont-plus", "tremont", "sierraforest", + "grandridge", "knl", "knm", "skylake", @@ -2071,6 +2072,8 @@ const pta processor_alias_table[] = M_CPU_TYPE (INTEL_TREMONT), P_PROC_SSE4_2}, {"sierraforest", PROCESSOR_SIERRAFOREST, CPU_HASWELL, PTA_SIERRAFOREST, M_CPU_SUBTYPE (INTEL_SIERRAFOREST), P_PROC_AVX2}, + {"grandridge", PROCESSOR_GRANDRIDGE, CPU_HASWELL, PTA_GRANDRIDGE, + M_CPU_TYPE (INTEL_GRANDRIDGE), P_PROC_AVX2}, {"knl", PROCESSOR_KNL, CPU_SLM, PTA_KNL, M_CPU_TYPE (INTEL_KNL), P_PROC_AVX512F}, {"knm", PROCESSOR_KNM, CPU_SLM, PTA_KNM, diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index 345fda648ff..fe2e9e21fd2 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -61,6 +61,7 @@ enum processor_types AMDFAM19H, ZHAOXIN_FAM7H, INTEL_SIERRAFOREST, + INTEL_GRANDRIDGE, CPU_TYPE_MAX, BUILTIN_CPU_TYPE_MAX = CPU_TYPE_MAX }; diff --git a/gcc/config.gcc b/gcc/config.gcc index 84c040746dc..b5eda046033 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -669,7 +669,7 @@ silvermont knl knm skylake-avx512 cannonlake icelake-client icelake-server \ skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \ sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \ nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \ -sierraforest graniterapids native" +sierraforest graniterapids grandridge native" # Additional x86 processors supported by --with-cpu=. Each processor # MUST be separated by exactly one space. diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 3117d83de00..95c16c23c7f 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -591,8 +591,11 @@ const char *host_detect_local_cpu (int argc, const char **argv) /* This is unknown family 0x6 CPU. */ if (has_feature (FEATURE_AVX)) { + /* Assume Grand Ridge. */ + if (has_feature (FEATURE_RAOINT)) + cpu = "grandridge"; /* Assume Granite Rapids. */ - if (has_feature (FEATURE_AMX_FP16)) + else if (has_feature (FEATURE_AMX_FP16)) cpu = "graniterapids"; /* Assume Sierra Forest. */ else if (has_feature (FEATURE_AVXVNNIINT8)) diff --git a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index a877d24148d..44fab6e80ae 100644 --- a/gcc/config/i386/i386-c.cc +++ b/gcc/config/i386/i386-c.cc @@ -206,6 +206,10 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, def_or_undef (parse_in, "__sierraforest"); def_or_undef (parse_in, "__sierraforest__"); break; + case PROCESSOR_GRANDRIDGE: + def_or_undef (parse_in, "__grandridge"); + def_or_undef (parse_in, "__grandridge__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__knl"); def_or_undef (parse_in, "__knl__"); @@ -395,6 +399,9 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, case PROCESSOR_SIERRAFOREST: def_or_undef (parse_in, "__tune_sierraforest__"); break; + case PROCESSOR_GRANDRIDGE: + def_or_undef (parse_in, "__tune_grandridge__"); + break; case PROCESSOR_KNL: def_or_undef (parse_in, "__tune_knl__"); break; diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 3c7570c5edd..23ab1f867d0 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -138,6 +138,7 @@ along with GCC; see the file COPYING3. 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[8.43.85.97]) by mx.google.com with ESMTPS id sa32-20020a1709076d2000b0078c39937f73si8785759ejc.798.2022.11.06.17.43.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Nov 2022 17:43:02 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=ytYm0cBQ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=gnu.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 916373858C2D for ; Mon, 7 Nov 2022 01:43:01 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 916373858C2D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667785381; bh=dJ9VbhmGc8IKYz8kcnCi6rcvN8/sOjT5ok0Y3dHZ9So=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=ytYm0cBQufPZQRp9Hha5Bvtog3fdIUDd9A5ImJl82V3Vxp4FDFqPkwmupxpQg9zsS 6df5RakJIhdZE1lUwFYacDY7y/1dGgf8xR9RxS57sPp+fR4kYkj8jL9fMDkXhg/t9K hzY6nr+5t00OYymyl/4PM4OY3CTlI6D7WBBqJtyQ= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 350BF3858C00 for ; Mon, 7 Nov 2022 01:41:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 350BF3858C00 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="396601349" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="396601349" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2022 17:41:19 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10523"; a="880887335" X-IronPort-AV: E=Sophos;i="5.96,143,1665471600"; d="scan'208";a="880887335" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga006.fm.intel.com with ESMTP; 06 Nov 2022 17:41:17 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 68B5D1005676; Mon, 7 Nov 2022 09:41:16 +0800 (CST) To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH 2/2] Add m_CORE_ATOM for atom cores Date: Mon, 7 Nov 2022 09:41:14 +0800 Message-Id: <20221107014114.71155-3-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20221107014114.71155-1-haochen.jiang@intel.com> References: <20221107014114.71155-1-haochen.jiang@intel.com> X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Haochen Jiang via Gcc-patches From: "Jiang, Haochen" Reply-To: Haochen Jiang Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748799725612862887?= X-GMAIL-MSGID: =?utf-8?q?1748799725612862887?= gcc/ChangeLog: * config/i386/i386-options.cc (m_CORE_ATOM): New. * config/i386/x86-tune.def (X86_TUNE_SCHEDULE): Initial tune for CORE_ATOM. (X86_TUNE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_FP_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_SSE_PARTIAL_REG_CONVERTS_DEPENDENCY): Ditto. (X86_TUNE_DEST_FALSE_DEP_FOR_GLC): Ditto. (X86_TUNE_MEMORY_MISMATCH_STALL): Ditto. (X86_TUNE_USE_LEAVE): Ditto. (X86_TUNE_PUSH_MEMORY): Ditto. (X86_TUNE_USE_INCDEC): Ditto. (X86_TUNE_INTEGER_DFMODE_MOVES): Ditto. (X86_TUNE_PREFER_KNOWN_REP_MOVSB_STOSB): Ditto. (X86_TUNE_MISALIGNED_MOVE_STRING_PRO_EPILOGUES): Ditto. (X86_TUNE_USE_SAHF): Ditto. (X86_TUNE_USE_BT): Ditto. (X86_TUNE_AVOID_FALSE_DEP_FOR_BMI): Ditto. (X86_TUNE_ONE_IF_CONV_INSN): Ditto. (X86_TUNE_AVOID_MFENCE): Ditto. (X86_TUNE_USE_SIMODE_FIOP): Ditto. (X86_TUNE_EXT_80387_CONSTANTS): Ditto. (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL): Ditto. (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL): Ditto. (X86_TUNE_SSE_TYPELESS_STORES): Ditto. (X86_TUNE_SSE_LOAD0_BY_PXOR): Ditto. (X86_TUNE_AVOID_4BYTE_PREFIXES): Ditto. (X86_TUNE_USE_GATHER_2PARTS): Ditto. (X86_TUNE_USE_GATHER_4PARTS): Ditto. (X86_TUNE_USE_GATHER): Ditto. --- gcc/config/i386/i386-options.cc | 1 + gcc/config/i386/x86-tune.def | 71 +++++++++++++++++++-------------- 2 files changed, 41 insertions(+), 31 deletions(-) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index 23ab1f867d0..e5c77f3a84d 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -139,6 +139,7 @@ along with GCC; see the file COPYING3. If not see #define m_TREMONT (HOST_WIDE_INT_1U<> (W-1) ^ x) - @@ -372,7 +379,7 @@ DEF_TUNE (X86_TUNE_USE_SIMODE_FIOP, "use_simode_fiop", ~(m_PENT | m_LAKEMONT | m_PPRO | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_AMD_MULTIPLE | m_LUJIAZUI | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT - | m_ALDERLAKE | m_GENERIC)) + | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_FFREEP: Use freep instruction instead of fstp. */ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) @@ -381,7 +388,8 @@ DEF_TUNE (X86_TUNE_USE_FFREEP, "use_ffreep", m_AMD_MULTIPLE | m_LUJIAZUI) DEF_TUNE (X86_TUNE_EXT_80387_CONSTANTS, "ext_80387_constants", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_K6_GEODE | m_ATHLON_K8 | m_LUJIAZUI - | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM + | m_GENERIC) /*****************************************************************************/ /* SSE instruction selection tuning */ @@ -397,14 +405,15 @@ DEF_TUNE (X86_TUNE_GENERAL_REGS_SSE_SPILL, "general_regs_sse_spill", DEF_TUNE (X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, "sse_unaligned_load_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) + | m_CORE_ATOM | m_AMDFAM10 | m_BDVER | m_BTVER | m_ZNVER | m_LUJIAZUI + | m_GENERIC) /* X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL: Use movups for misaligned stores instead of a sequence loading registers by parts. */ DEF_TUNE (X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, "sse_unaligned_store_optimal", m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2 | m_SILVERMONT | m_KNL | m_KNM | m_INTEL | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) + | m_CORE_ATOM | m_BDVER | m_ZNVER | m_LUJIAZUI | m_GENERIC) /* X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL: Use packed single precision 128bit instructions instead of double where possible. */ @@ -414,13 +423,13 @@ DEF_TUNE (X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, "sse_packed_single_insn_optim /* X86_TUNE_SSE_TYPELESS_STORES: Always movaps/movups for 128bit stores. */ DEF_TUNE (X86_TUNE_SSE_TYPELESS_STORES, "sse_typeless_stores", m_AMD_MULTIPLE | m_LUJIAZUI | m_CORE_ALL | m_TREMONT | m_ALDERLAKE - | m_GENERIC) + | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_SSE_LOAD0_BY_PXOR: Always use pxor to load0 as opposed to xorps/xorpd and other variants. */ DEF_TUNE (X86_TUNE_SSE_LOAD0_BY_PXOR, "sse_load0_by_pxor", m_PPRO | m_P4_NOCONA | m_CORE_ALL | m_BDVER | m_BTVER | m_ZNVER - | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_GENERIC) + | m_LUJIAZUI | m_TREMONT | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC) /* X86_TUNE_INTER_UNIT_MOVES_TO_VEC: Enable moves in from integer to SSE registers. If disabled, the moves will be done by storing @@ -467,22 +476,22 @@ DEF_TUNE (X86_TUNE_SLOW_PSHUFB, "slow_pshufb", /* X86_TUNE_AVOID_4BYTE_PREFIXES: Avoid instructions requiring 4+ bytes of prefixes. */ DEF_TUNE (X86_TUNE_AVOID_4BYTE_PREFIXES, "avoid_4byte_prefixes", m_SILVERMONT | m_GOLDMONT | m_GOLDMONT_PLUS | m_TREMONT | m_ALDERLAKE - | m_INTEL) + | m_CORE_ATOM | m_INTEL) /* X86_TUNE_USE_GATHER_2PARTS: Use gather instructions for vectors with 2 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_2PARTS, "use_gather_2parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_GATHER_4PARTS: Use gather instructions for vectors with 4 elements. */ DEF_TUNE (X86_TUNE_USE_GATHER_4PARTS, "use_gather_4parts", - ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ZNVER3 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_USE_GATHER: Use gather instructions for vectors with 8 or more elements. */ DEF_TUNE (X86_TUNE_USE_GATHER, "use_gather", - ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_GENERIC)) + ~(m_ZNVER1 | m_ZNVER2 | m_ALDERLAKE | m_CORE_ATOM | m_GENERIC)) /* X86_TUNE_AVOID_128FMA_CHAINS: Avoid creating loops with tight 128bit or smaller FMA chain. */