From patchwork Tue Oct 10 14:04:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 150808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp227502vqb; Tue, 10 Oct 2023 07:07:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQITESszXuSL6991f1Pf075zgSVkD/Cm6jP6NygK0aqedbRKI8F/ARmyz8SmyhIxMxKRK2 X-Received: by 2002:a17:906:106:b0:9b9:8f9c:c777 with SMTP id 6-20020a170906010600b009b98f9cc777mr16139201eje.30.1696946875737; Tue, 10 Oct 2023 07:07:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696946875; cv=pass; d=google.com; s=arc-20160816; b=u2dCIw0KNjZWayPBXscGXK9yG4nfk6kwTyxz0Nqn6U1h1sEFmSdi11HWZyMRRiNkE+ AyA4TTyDtXXloK1d385OTtpuv7+p2OOZe48urgoIFxRk09vpUtfKc66JpEQzXzaNNrke kYa2Nvxsev9mph00AZIHN0U4foiJB90GNUj4I38WMnQUPxlDUcQjBCe2MkO5iCyhNvxp wnVvE6fDW60Vv3vazEw9a7GeIUUdTXOTMaRyIhr60puR88sqvHp+oabwObaChmjbl7TK kYoQSKn1YyJpvO2Swmm5SO6DWFXZ0n6Q6TK4ol/zYJMucQHMg/bC8sQMueM1L+T/TGYE 6Vpg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :dmarc-filter:delivered-to; bh=CfWHBXzaDlcOcvil9W62+iLGVaAPihnvtdjJo1Xs5mI=; fh=cdLUSjbFO0/cTi+z3xcckFOOtvTDyNZWtn2WcodW9fw=; b=wFZu1gmgU03sYrWQxLBP/F+/al5yvvt0NMZ20BH0RjWD5kbJE3HwiEbTV982k6bMId S9wjsRG84GXy2mKM1Sy9eT1oiKPJISAFWb8Yd6d0LdELjSKaz0f4yHe1UH60bvHCvfRD b7B/Kq049Ku+falp7x5phYI73Jqz8BOW8EM63JDNlQgcOGQwVYejV9/wq/joOLpSWFHI 9WS/pk2oE/6cBwOjxfy9fBfnNoaoBWQI1XPZTtR1BrShHMr1L/Ri4XLH06QQdRfMXK8e CEcBArS/C/ehfPb5O0iEZHOacUINxTfZZeDVitmqpUjs3YqeMvgBxw3QMCIh6tP0rlYa HFow== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=scaWlqbV; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=scaWlqbV; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id pv17-20020a170907209100b009ae4f7c9754si5485156ejb.3.2023.10.10.07.07.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 07:07:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=scaWlqbV; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=scaWlqbV; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 23E97385CC8F for ; Tue, 10 Oct 2023 14:06:09 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2049.outbound.protection.outlook.com [40.107.6.49]) by sourceware.org (Postfix) with ESMTPS id 2D2A83858C5E for ; Tue, 10 Oct 2023 14:05:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 2D2A83858C5E Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CfWHBXzaDlcOcvil9W62+iLGVaAPihnvtdjJo1Xs5mI=; b=scaWlqbVBgF1KTnwrgxTjnWY9B7kVkzFYV3c41SLn1X2RHPYY0msJMnkR9jOKbSewtntXhW83yo+CoQ+zLiN4Qe4vOIrHXFlXa+eapIY6Yo8zGkJQMroJODTRfv9ClbMlRIzZdrINQA0mHHU5glh49AIYmxoSiLMuw/sNvwtdwE= Received: from DU2PR04CA0352.eurprd04.prod.outlook.com (2603:10a6:10:2b4::23) by AM8PR08MB6372.eurprd08.prod.outlook.com (2603:10a6:20b:369::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.37; Tue, 10 Oct 2023 14:05:08 +0000 Received: from DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:2b4:cafe::2) by DU2PR04CA0352.outlook.office365.com (2603:10a6:10:2b4::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.38 via Frontend Transport; Tue, 10 Oct 2023 14:05:08 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT056.mail.protection.outlook.com (100.127.142.88) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:05:08 +0000 Received: ("Tessian outbound 6d14f3380669:v211"); Tue, 10 Oct 2023 14:05:08 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: d32462cc16a87ba9 X-CR-MTA-TID: 64aa7808 Received: from ae9a8ad54743.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 9E5FB32A-6536-4947-AE86-C26EB3A5DDF9.1; Tue, 10 Oct 2023 14:05:01 +0000 Received: from EUR01-VE1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id ae9a8ad54743.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 10 Oct 2023 14:05:01 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZH6yj7V00/Qw6jPTYULUdeJ5eyozyyNv6RaS5T1bb+MHFPi0a8liN1B80O3S/tEXyFU1e0OHzU14/LKNCD6XSmr+ijIPEOuMuEVxrStLfOKCJ7mpOYONZdoQuUxwUbg8r7tdB6vYSKBb6Tf1lNItZf6+N+hdB2J+BJnLXEvfK/KDKv7tgbuRc6Mtu+SW2tzWLpsIVMGRe/m85OUyTJPt8bQxy8KdNbErxbTIdSX9MKlXCKFAOc70tjT6WBY2zZnhbe478c2W5v1BunxsHDmgmKk5u5vzUxoovx91hH50g3cMb43gIsLkGPoiSdCbUm6hLBeZDcuklZugRnqY15hM/A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CfWHBXzaDlcOcvil9W62+iLGVaAPihnvtdjJo1Xs5mI=; b=gMKP0FqdQA+MnwbqsylaMDfbFvVoZrHs9hfsW1vzfn8wC3uQS81LXW66dGwSzMDFicg5fSI643A8JElxg0jqUkRX8I2NtIUuMiiNlacl9hAmNl2THnLnnBEbY+Kr4l1POGdu4a2Ck9CsJi9jU8c3wPIxiiP1bczRZOsbUIuXswUpH9WAMo2PBLbZSAVNqRU24D+UTrRPwf5rykz3qTr7H9QSAMpe26DGNJC7greICyXvxu7FOGsQsCGt3wmYnzV+Xp5XvXa5pOzL+R9gc0uCrV9xlYE7a7Xr4M0tCzOpE3JJ1XLXZfX39WniJThinDmFBhz7gxXCW6X0yEYW3R5g+A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CfWHBXzaDlcOcvil9W62+iLGVaAPihnvtdjJo1Xs5mI=; b=scaWlqbVBgF1KTnwrgxTjnWY9B7kVkzFYV3c41SLn1X2RHPYY0msJMnkR9jOKbSewtntXhW83yo+CoQ+zLiN4Qe4vOIrHXFlXa+eapIY6Yo8zGkJQMroJODTRfv9ClbMlRIzZdrINQA0mHHU5glh49AIYmxoSiLMuw/sNvwtdwE= Received: from DB8PR06CA0045.eurprd06.prod.outlook.com (2603:10a6:10:120::19) by GV2PR08MB9399.eurprd08.prod.outlook.com (2603:10a6:150:df::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.38; Tue, 10 Oct 2023 14:04:58 +0000 Received: from DBAEUR03FT063.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:120:cafe::32) by DB8PR06CA0045.outlook.office365.com (2603:10a6:10:120::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.31 via Frontend Transport; Tue, 10 Oct 2023 14:04:57 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT063.mail.protection.outlook.com (100.127.142.255) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:04:57 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 10 Oct 2023 14:04:56 +0000 Received: from e127754.arm.com (10.57.5.240) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Tue, 10 Oct 2023 14:04:56 +0000 From: To: CC: , Subject: [PATCH 1/3] [GCC] arm: vst1q_types_x2 ACLE intrinsics Date: Tue, 10 Oct 2023 15:04:43 +0100 Message-ID: <20231010140445.2084-2-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231010140445.2084-1-Ezra.Sitorus@arm.com> References: <20231010140445.2084-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT063:EE_|GV2PR08MB9399:EE_|DBAEUR03FT056:EE_|AM8PR08MB6372:EE_ X-MS-Office365-Filtering-Correlation-Id: 5ac90ca8-e1ff-43b8-c6b1-08dbc999e958 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: NFGQ6j6bgQ2CYIkGSVqJ4py9ruM4Bblw84BRSuK12zdKBsx2J2tjAfavF63YqFauYvGp+h2A6VnZBhnI8G9CobwuRGru9Z3M+PG3CEMm2Ndwzka++cUioRtUaOGLmkJLRqpt7l367dVeNUe6kj1KDxwtYB1OSHhltm6k87hRx4MwIb/JMYO6HAGw/HmrEEU5sD2yR95BwK5BwTOn9jQo5Y632JFDEv9FHD0pj0AjrPRkyh/IOGw7Wes2HWoq/RsWs1Xn4+CLShgy42k5MvG3xcC7Ibwy6jPqXa5XrZ5FwveAhGzpLbxdXzrNxGRFeFmSgjcU905WHuNVN4ECBN+6tIs+XkmbiYYgQPlBILOjGhuenLV8PcM+yZyYSVAp7KZv73zfAhd4NzSxYPME0SCOH5zKTAgvrP2B79/jb+X4EzTBJSEoyJ1QBOB3rJmmL9xwiyM7bW4oYml9X3awi4NoobG6hOyvBkPXS5SSvuPG/u8r6Ubb87NwR7op/wxC+quY1cu7OgAmvMB2kc5W1CUlpox6vAHcjIhF3tUjtxWUBtTAv6hNkYmr7c9PAIHBrlAtYQH0F0PtjsFq5QJFMTE3qnNF1H5dIOcxh/L9knWvS5zMiAQMdr9GxllVYpFbCF5vFj+3hEofmI+W+yMNr7YZFlvOCmIATO14j6KeliXYAHguX4bO9U3AcdTq8F70/A6dCCzZU5fddw+f7oyYDbLPJ3GfgMk3uSS15VtignVcbYcBba1LGoLcB7p56knxNg+BFdWdFsCGevPvOs1WwoDNTPkppVkGuWn/bS/vSNYeAqivMQwJ3O40hL71ZK28lGk+D3CasWI35ei4lHnw9m2d3A== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(396003)(39860400002)(346002)(376002)(136003)(230922051799003)(64100799003)(451199024)(186009)(1800799009)(82310400011)(36840700001)(40470700004)(46966006)(84970400001)(1076003)(40460700003)(356005)(36756003)(40480700001)(86362001)(82740400003)(81166007)(36860700001)(336012)(26005)(47076005)(426003)(2906002)(83380400001)(2876002)(30864003)(966005)(2616005)(6666004)(7696005)(478600001)(8676002)(4326008)(6916009)(8936002)(41300700001)(5660300002)(70586007)(70206006)(54906003)(316002)(36900700001)(357404004); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: GV2PR08MB9399 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: a86b876d-644f-407c-50cf-08dbc999e2e8 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: O4yA74jgB4chKm4tsfcZUU+vmMQUrf9ed9IyWCu9K7I5atc1lqRb2jFEQXVgcEL1nQqfMTde++AXhKh1LfkV6ANl1AEWsZEVW/ERoFpIJGv2u7ckS8+RMLk1+U/ts31m/n1Tws10p6WLdzBSkH41ccPnTsG6MRoXkbic1TjeavF+HUCu57Tt/YjoFiL1iDuv3vfMIqOCyjgX5amG2A+sgPlsS8W3msKQa0iQ7N/FtZkBdb0SfrDLSPZKAwYCGDs6xXVQvQpV06z1UXyADCuuYGN24ZlbvCRV/3YIeB9QsJgPyUDCQXPi/sl8jk4AiRwBDAGFIEmnN3VK7Pe3LsKsBxu5JJ/VMu0i+w+mT9jv006Fz8fLWzWdS3lOkLQsyD036mRdog9jHvUaOhpmh3X9O/yaaAmMCvxKba62pur7wgJcsfondeCBqphJWRdFl5Rsv3gWXRUivd3l+BVPWcHfDq3794QB53y3AYPhiGZhMoE5IgMyiiWzpHqt4rzofFyK+uEhJF8qRBYRz3nHSZYgOWu84kysASEz+hjm6IVOgO1Hs9VUsFog2np6m61iGd5/FvxhUfIt0J8TUpkTDfZlTvQ3zJDrR1U548RgAjFdBIs0TPSTpEBusqWaklJ3/W/rzDDw6acwnl7ESKuff655y5N3zvafED5dSn9XhlKTJuNn6AmvjC8b+OhJGyDJte7UIkzj7Mr5ZK0LcIVGV6vRyjpCLphi3C2NUOaDoL6z6d2s0HuKLXmsK2CZR9PBY7aBRruTIvjCdoBGKEHA+ZMBUjLL3bUKWSIwir5uLfgTu4I= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(346002)(136003)(39860400002)(396003)(230922051799003)(186009)(1800799009)(82310400011)(64100799003)(451199024)(36840700001)(46966006)(40470700004)(84970400001)(40460700003)(36756003)(30864003)(86362001)(2876002)(2906002)(5660300002)(4326008)(8676002)(8936002)(41300700001)(82740400003)(54906003)(81166007)(70206006)(6916009)(426003)(336012)(7696005)(36860700001)(40480700001)(316002)(70586007)(47076005)(6666004)(83380400001)(478600001)(26005)(2616005)(966005)(1076003)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 14:05:08.4989 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5ac90ca8-e1ff-43b8-c6b1-08dbc999e958 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT056.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM8PR08MB6372 X-Spam-Status: No, score=-11.9 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779377766875068160 X-GMAIL-MSGID: 1779377766875068160 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for AArch32. This patch adds the _x2 variants of the vst1q intrinsic. Tests use xN so that the latter variants (_x3, _x4) could be added. ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/ ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x2, vst1q_u16_x2, vst1q_u32_x2, vst1q_u64_x32): New. (vst1q_s8_x2, vst1q_s16_x2, vst1q_s32_x2, vst1q_s64_x2): New. (vst1q_f16_x2, vst1q_f32_x2): New. (vst1q_p8_x2, vst1q_p16_x2, vst1q_p64_x2): New. (vst1q_bf16_x2): New. * config/arm/arm_neon_builtins.def (vst1<_x2): New entries. * config/arm/neon.md (neon_vst1_x2): Updated from neon_vst1_x2. * config/arm/iterators.md (VMEMX2): New mode iterator. (VMEMX2_q): New mode attribute. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/iterators.md | 6 + gcc/config/arm/neon.md | 6 +- .../gcc.target/arm/simd/vst1q_base_xN_1.c | 70 +++++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 13 ++ .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 13 ++ 8 files changed, 233 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 41e645d8352..b8f3fca3060 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11327,6 +11327,38 @@ vst1_s64_x2 (int64_t * __a, int64x1x2_t __b) __builtin_neon_vst1_x2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x2 (int8_t * __a, int8x16x2_t __b) +{ + union { int8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x2 (int16_t * __a, int16x8x2_t __b) +{ + union { int16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x2 (int32_t * __a, int32x4x2_t __b) +{ + union { int32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b) +{ + union { int64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11656,6 +11688,14 @@ vst1q_p64 (poly64_t * __a, poly64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b) +{ + union { poly64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11701,6 +11741,24 @@ vst1q_f32 (float32_t * __a, float32x4_t __b) __builtin_neon_vst1v4sf ((__builtin_neon_sf *) __a, __b); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x2 (float16_t * __a, float16x8x2_t __b) +{ + union { float16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b) +{ + union { float32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11729,6 +11787,38 @@ vst1q_u64 (uint64_t * __a, uint64x2_t __b) __builtin_neon_vst1v2di ((__builtin_neon_di *) __a, (int64x2_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x2 (uint8_t * __a, uint8x16x2_t __b) +{ + union { uint8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x2 (uint16_t * __a, uint16x8x2_t __b) +{ + union { uint16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x2 (uint32_t * __a, uint32x4x2_t __b) +{ + union { uint32x4x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b) +{ + union { uint64x2x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11743,6 +11833,22 @@ vst1q_p16 (poly16_t * __a, poly16x8_t __b) __builtin_neon_vst1v8hi ((__builtin_neon_hi *) __a, (int16x8_t) __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x2 (poly8_t * __a, poly8x16x2_t __b) +{ + union { poly8x16x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b) +{ + union { poly16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20419,6 +20525,14 @@ vst1q_bf16 (bfloat16_t * __a, bfloat16x8_t __b) __builtin_neon_vst1v8bf (__a, __b); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b) +{ + union { bfloat16x8x2_t __i; __builtin_neon_oi __o; } __bu = { __b }; + __builtin_neon_vst1q_x2v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 95300cb0fe4..496d267fab8 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -309,6 +309,7 @@ VAR12 (LOAD1LANE, vld1_lane, VAR10 (LOAD1, vld1_dup, v8qi, v4hi, v2si, v2sf, di, v16qi, v8hi, v4si, v4sf, v2di) VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1, vst1, diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index a9803538101..6c5a80d9348 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -141,6 +141,9 @@ ;; Opaque structure types used in table lookups (except vtbl1/vtbx1). (define_mode_iterator VTAB [TI EI OI]) +;; Opaque structure types for x2 variants of VSTR1/VSTR1Q or VLD1/VLD1Q. +(define_mode_iterator VMEMX2 [TI OI]) + ;; Widenable modes. (define_mode_iterator VW [V8QI V4HI V2SI]) @@ -1533,6 +1536,9 @@ ;; vtbl suffix for NEON vector modes. (define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) +;; Suffix for x2 variants of vld1 and vst1. +(define_mode_attr VMEMX2_q [(TI "") (OI "q")]) + ;; fp16 or bf16 marker for 16-bit float modes. (define_mode_attr fporbf [(HF "fp16") (BF "bf16")]) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index f5d583129fa..088277ee6ed 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5125,9 +5125,9 @@ if (BYTES_BIG_ENDIAN) UNSPEC_VST1))] "TARGET_NEON") -(define_insn "neon_vst1_x2" - [(set (match_operand:TI 0 "neon_struct_operand" "=Um") - (unspec:TI [(match_operand:TI 1 "s_register_operand" "w") +(define_insn "neon_vst1_x2" + [(set (match_operand:VMEMX2 0 "neon_struct_operand" "=Um") + (unspec:VMEMX2 [(match_operand:VMEMX2 1 "s_register_operand" "w") (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] UNSPEC_VST1))] "TARGET_NEON" diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c new file mode 100644 index 00000000000..232feafade0 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -0,0 +1,70 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon } */ + +#include "arm_neon.h" + + +void test_vst1q_u8_x2 (uint8_t * ptr, uint8x16x2_t val) +{ + vst1q_u8_x2 (ptr, val); +} + +void test_vst1q_u16_x2 (uint16_t * ptr, uint16x8x2_t val) +{ + vst1q_u16_x2 (ptr, val); +} + +void test_vst1q_u32_x2 (uint32_t * ptr, uint32x4x2_t val) +{ + vst1q_u32_x2 (ptr, val); +} + +void test_vst1q_u64_x2 (uint64_t * ptr, uint64x2x2_t val) +{ + vst1q_u64_x2 (ptr, val); +} + +void test_vst1q_s8_x2 (int8_t * ptr, int8x16x2_t val) +{ + vst1q_s8_x2 (ptr, val); +} + +void test_vst1q_s16_x2 (int16_t * ptr, int16x8x2_t val) +{ + vst1q_s16_x2 (ptr, val); +} + +void test_vst1q_s32_x2 (int32_t * ptr, int32x4x2_t val) +{ + vst1q_s32_x2 (ptr, val); +} + +void test_vst1q_s64_x2 (int64_t * ptr, int64x2x2_t val) +{ + vst1q_s64_x2 (ptr, val); +} + +void test_vst1q_f32_x2 (float32_t * ptr, float32x4x2_t val) +{ + vst1q_f32_x2 (ptr, val); +} + +void test_vst1q_p8_x2 (poly8_t * ptr, poly8x16x2_t val) +{ + vst1q_p8_x2 (ptr, val); +} + +void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val) +{ + vst1q_p16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c new file mode 100644 index 00000000000..2a4579f0aae --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_v8_2a_bf16_neon_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_v8_2a_bf16_neon } */ + +#include "arm_neon.h" + +void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val) +{ + vst1q_bf16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c new file mode 100644 index 00000000000..61a7e558c48 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_neon_fp16_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_neon_fp16 } */ + +#include "arm_neon.h" + +void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val) +{ + vst1q_f16_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c new file mode 100644 index 00000000000..82f3dad293c --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -0,0 +1,13 @@ +/* { dg-do assemble } */ +/* { dg-require-effective-target arm_crypto_ok } */ +/* { dg-options "-save-temps -O2" } */ +/* { dg-add-options arm_crypto } */ + +#include "arm_neon.h" + +void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val) +{ + vst1q_p64_x2 (ptr, val); +} + +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ From patchwork Tue Oct 10 14:04:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 150807 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp226713vqb; Tue, 10 Oct 2023 07:07:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFzkgCHvw0u+BUJ3SxV+RKhGTqxyg/uXIT8jm2ddO5WPxNIvM4VcltY0Yq3b2UdLfogkeN5 X-Received: by 2002:aa7:df86:0:b0:52a:1d9c:83ff with SMTP id b6-20020aa7df86000000b0052a1d9c83ffmr16573569edy.1.1696946827705; Tue, 10 Oct 2023 07:07:07 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696946827; cv=pass; d=google.com; s=arc-20160816; b=J8XApDuqRa6F/dNSqiKCU5Rneo0ZEnZ3MwCaRb+ni/2AXby6FzVeu4n3AN2LVVfl1g 5BT5wswdfJv52MQX6LT/f0FVME06jgL8x+uZ6rTHtt5de+bC49QAoU4RnEjYjg3Waaoz V66tAYcX7nIkFAhaO+WNMA6NfGe9XSLFavjcxcTHesFDepDZvfMjFPyTSohl53Xfa1Tl 0oRKoDxQau55gab0Gc548QPVlj3B5/LuL8EfpFZNh3Mu1gwmOMoZDVhUH7bXs54jwCRQ EjPTUe2QHdeaNDbjF4Awgj2KSQoGwLTrY40tSUxPBEMKJDNxSNAfatGV98QTi3J7gQp8 4VhA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :dmarc-filter:delivered-to; bh=cBhMPDQ7nmukDDTbMAsvQPvih7aQmTqsM1kvyuB+ShY=; fh=cdLUSjbFO0/cTi+z3xcckFOOtvTDyNZWtn2WcodW9fw=; b=x/s1iDf3sQooUWym+momKYN96HlTFyqWL9gdsAlS3Pii+DVgw5EH8OvhrtLcazlygV PjhZFPhM5BIjC8nMoW8FUW7iu3n/9qtj8gY0zSVCSO/tJU375uXJ0WXk+UT3pzCE5AjB i3r5yagjzTISiwFEJOZ/itu12azP2MCUUMAgb8+ZyIVd1+EZoR6UIifux9SaJBCEbMHI kPqkG4kb9iEsjx0leQ92joXpsaVqru85db5CnRxZ0PJNP+/z2ECWIkPgIyR+Tob6t1Hs gAhLIGss3kBgARpbF5UbT7ERvivv301eiaQaGtyH2sirJCeWsmego0EBnBvw1DBeWJvY TwSw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=b7plMuSd; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=b7plMuSd; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id r3-20020aa7c143000000b005362c97bccdsi5643331edp.195.2023.10.10.07.07.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 07:07:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=b7plMuSd; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=b7plMuSd; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 18296385CC89 for ; Tue, 10 Oct 2023 14:05:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2053.outbound.protection.outlook.com [40.107.20.53]) by sourceware.org (Postfix) with ESMTPS id 8B72538582B0 for ; Tue, 10 Oct 2023 14:05:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8B72538582B0 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cBhMPDQ7nmukDDTbMAsvQPvih7aQmTqsM1kvyuB+ShY=; b=b7plMuSdv+lcJXZodO7XQFWH+zBrVsDw4p8mmWijzP/v4oYpL6iz/+4vF4y/rgrubYgG1uHAMuLDqyURO2pjVqXFagVM3+jNzRxWptF6CVQXQPHs/f+Wlval5mD+H6mChlugcbli6UmZxLP2ESUUS13H56KC0AySe++mxmEgKyU= Received: from AS9PR07CA0007.eurprd07.prod.outlook.com (2603:10a6:20b:46c::15) by AS2PR08MB10178.eurprd08.prod.outlook.com (2603:10a6:20b:64c::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.38; Tue, 10 Oct 2023 14:05:10 +0000 Received: from AM7EUR03FT055.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:46c:cafe::5f) by AS9PR07CA0007.outlook.office365.com (2603:10a6:20b:46c::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.20 via Frontend Transport; Tue, 10 Oct 2023 14:05:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM7EUR03FT055.mail.protection.outlook.com (100.127.141.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:05:10 +0000 Received: ("Tessian outbound 6d14f3380669:v211"); Tue, 10 Oct 2023 14:05:10 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 470e5d4153499413 X-CR-MTA-TID: 64aa7808 Received: from f1aa6ad107cf.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 5A48A7D3-9E06-4315-878E-1875CEF1BD50.1; Tue, 10 Oct 2023 14:05:04 +0000 Received: from EUR05-AM6-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id f1aa6ad107cf.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 10 Oct 2023 14:05:04 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZsrcmiqMJ7byEy2C9dk9K5/81/4xyeSdfz8+6omxwl5QHxizNmKwvydoLL12wrHIVnv51UCpYbVXJ95PZ4JOunovly/x6tBMN7kQVSVqtEyH9/iRJN3JAMH9Gll54W9hzOHxtMkTlI28i2HVEmuplQlSLxAa0TrLVAVei6bf4ihQHS5zeFV4PEQm/tVa/1UA5L/97x6H1of2ctcPqzH/92TNEtoPLh9zVONNCsxKJqJt2uIj/tdJYkB2PNIF860LFVy0Q0KceTvqFLhutVxJwoy2BRDpdh76UvkgFQ965IGUq+1nAT51zWYWRjhwSty24Zw+bmMivyumFuHXrNwIfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=cBhMPDQ7nmukDDTbMAsvQPvih7aQmTqsM1kvyuB+ShY=; b=FbXLBND6fN5/Qx0m0ZQQVm9eOKWRZvzwCFNjpuceDjtxgFK/lMX8EmsdNfU/LfjWuz4iwLndEAv3j/VWrf8GcPRcUahPAY27IFdtqcT116IpADUNOMidJGq/sqJDlygzvXMvjHGVqCx8QEcNaETc19Ebj9Keu+CdA4iVhBbqoGNUMFPpXngV2VwNNyRP4po1Tcr9ChFYoBkSSIbuvnkBgMOLdjN3s6YG8RGOCUgZ/ToZIH4ItEY+/NM7SobM9eoKQH00o+QX50TaObM6T80wkwJVLHehAPy3iqAILscPNaDnAJR7pWojfpaEHni8VQEtjjl4D6onrAbFw24+mBIBvg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=cBhMPDQ7nmukDDTbMAsvQPvih7aQmTqsM1kvyuB+ShY=; b=b7plMuSdv+lcJXZodO7XQFWH+zBrVsDw4p8mmWijzP/v4oYpL6iz/+4vF4y/rgrubYgG1uHAMuLDqyURO2pjVqXFagVM3+jNzRxWptF6CVQXQPHs/f+Wlval5mD+H6mChlugcbli6UmZxLP2ESUUS13H56KC0AySe++mxmEgKyU= Received: from DB8PR06CA0042.eurprd06.prod.outlook.com (2603:10a6:10:120::16) by AM9PR08MB5892.eurprd08.prod.outlook.com (2603:10a6:20b:2dd::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.36; Tue, 10 Oct 2023 14:05:00 +0000 Received: from DBAEUR03FT063.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:120:cafe::59) by DB8PR06CA0042.outlook.office365.com (2603:10a6:10:120::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.29 via Frontend Transport; Tue, 10 Oct 2023 14:05:00 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT063.mail.protection.outlook.com (100.127.142.255) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:05:00 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 10 Oct 2023 14:04:59 +0000 Received: from e127754.arm.com (10.57.5.240) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Tue, 10 Oct 2023 14:04:58 +0000 From: To: CC: , Subject: [PATCH 2/3] [GCC] arm: vst1q_types_x3 ACLE intrinsics Date: Tue, 10 Oct 2023 15:04:44 +0100 Message-ID: <20231010140445.2084-3-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231010140445.2084-1-Ezra.Sitorus@arm.com> References: <20231010140445.2084-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT063:EE_|AM9PR08MB5892:EE_|AM7EUR03FT055:EE_|AS2PR08MB10178:EE_ X-MS-Office365-Filtering-Correlation-Id: 827e0957-2c41-403e-88a7-08dbc999eabb x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: FljA29Oe1q8RT8VJV+tZgSchqISNTiQK8kTCiFqjZ5S6XFcSHI12B76u6ubi9eJyQJQQ7Ti+o/ybqP+66Tfex20kYNmFex/8PvdyuSrKwRm5GyiQ7/TGpoYqGFbeak2qUbWNzdNCYabib06LzivJ7amLGNRoDpk4XIgTsyZnJ1R2q60vHJb2hnfLY/f3qebtQ1cYuyKUoyLPgsEpzKrsKnCdvGgsTLmZqFpfEuocOp1fPWuSN6HcW0wxWIqcp6RhP02bvI4G/fPowLA5O9UF7vKq6Hpz0Yywm0adNiRkj8it0BK0wJylFgpYOC0XpOaLNM5UAA6zdxhipa7ElC/kWH02e95ts8dYruYKS9WgWVFnc5GgGEuPRM1lc/ykMt0ssu2Av+wndOt8WifNE9A/ifzjYg/LwViswQ9ZzIf9wqdxeO6TW24DZwDXkzoOXaFBXgokIkFbKKLiCtCKXfkxUKALM8TA3Fy+CPm2Ys97n0TXlW6rPliyXelPPXQxPwN2lSgcrztToexHoRBF+gSyU/iSWi8x5pIoDJCTypYRBPuZOf+cI3EfAx3az4gLTyxvqRn1v5Ew2rCiXvjBaqLT5t08lHzwPKuYQyP8wRDKEGL+IhkensHY9tTTYRQgJ0rUi1lAIUWhAWd4k2qIDv0dfUQD5OrPtGwngqAmZV2r25Cq8J784k6/aeDpRqFtKkphM/6A5TH2T0yUSPH8xh0BH0dpd/STonH9llvc8aB/CHedGDXZuEkXaXAErZ5dGQi8uy34pf5inQau/EAqwIdLe0i8EJUWGoEHbpnqxTefmTGieEhgfzeR1pnjzez0OTO5TlWzJfLuvcLTHEQyxETGFw== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(346002)(39860400002)(396003)(136003)(376002)(230922051799003)(64100799003)(451199024)(82310400011)(186009)(1800799009)(40470700004)(36840700001)(46966006)(40480700001)(2906002)(40460700003)(2616005)(336012)(966005)(426003)(1076003)(47076005)(36860700001)(26005)(6916009)(70586007)(54906003)(8676002)(70206006)(6666004)(4326008)(5660300002)(7696005)(8936002)(82740400003)(41300700001)(478600001)(30864003)(2876002)(316002)(36756003)(356005)(86362001)(81166007)(84970400001)(36900700001)(357404004); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB5892 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM7EUR03FT055.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: fdd6e71c-5c0a-43d0-2b4e-08dbc999e468 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tVF7cOFwLs+gDKbMLcsXEc93XLktSA964I/+Udhg81QELm4hbMvG9IcoID3+rVufeIlBrKa1s4kdtmmNe8mYL2C0rZdhiAd9d6DAl2jrYPT0zliQ/lYgC/+QPXQkYLF82uvoCbx4kb1exwaHnfPYe6XO0D2FE3pmo+aUPkOr4C5Rnd6yp41xnJNo1AmtQStynqp8o4rvw1EpquxOlhgPQxHU8MY7GPhLQ715ZP4qTLPMmsNNIAWOxCnDXk1UBUVwMW4nXrGxJUoqGvZgILuE9tfW2i5TvQCdPgupDClCwSKO3rG4lW4q7MKY4BodPC8DUFRR3JheJceatZQHq2iyyKPkZ/o+bwllCp6V+wmQdP6HZJ1KN3JFKG2WBIZGHpNZQ+cAI4PXaKa+oo0DomKBECijiWCZJt4SCnz8JOqNXhFmKXZXMzUAvzQn23U3jppzxI0My/pn9DwAvFEqxAyRvdTkuEFzr0jn3AYhWt/nkLd+pHuuutNkjTLyntmxxkSMXWc6k9ALUNetTZV/zMtg8JPrIwn9PfskNVvRGfvuW4C4PhddPDdbddTPbDl6Xr06BGwodvRFR9L4vdryzpzCusJbUvRYqouf8tPHeGNSb3OGYzrPa8/p7TGse+l//d/tzOBGvQEM8+KegzvsktFo5mwvP9DSDKhzjOe2Prn9ZgfCuK1ikR/NCEPY5Cgr+fFuuYw1Bz6tzZ4UYdKbG7SUz1WeJGzaZChi+C7mfM9xvXMu0HJmiTUFUeqPCccuwqVe0xNjJmceQEbuZT8lwzuawGMAH42EGtET5ypPW/wFsEw= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(396003)(376002)(39860400002)(136003)(230922051799003)(82310400011)(64100799003)(186009)(451199024)(1800799009)(40470700004)(46966006)(36840700001)(40460700003)(2906002)(2876002)(47076005)(36860700001)(86362001)(36756003)(40480700001)(81166007)(82740400003)(336012)(26005)(30864003)(2616005)(8676002)(8936002)(4326008)(6666004)(41300700001)(84970400001)(70206006)(70586007)(6916009)(54906003)(316002)(426003)(1076003)(7696005)(5660300002)(966005)(478600001)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 14:05:10.7613 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 827e0957-2c41-403e-88a7-08dbc999eabb X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM7EUR03FT055.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB10178 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779377716607498953 X-GMAIL-MSGID: 1779377716607498953 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for AArch32. This patch adds the _x3 variants of the vst1q intrinsic. ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/ ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x3, vst1q_u16_x3, vst1q_u32_x3, vst1q_u64_x3): New. (vst1q_s8_x3, vst1q_s16_x3, vst1q_s32_x3, vst1q_s64_x3): New. (vst1q_f16_x3, vst1q_f32_x3): New. (vst1q_p8_x3, vst1q_p16_x3, vst1q_p64_x3): New. (vst1q_bf16_x3): New. * config/arm/arm_neon_builtins.def (vst1q_x3): New entries. * config/arm/neon.md (neon_vst1q_x3): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 24 ++++ .../gcc.target/arm/simd/vst1q_base_xN_1.c | 60 +++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 6 + 7 files changed, 217 insertions(+) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index b8f3fca3060..46ee888410f 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11359,6 +11359,38 @@ vst1q_s64_x2 (int64_t * __a, int64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x3 (int8_t * __a, int8x16x3_t __b) +{ + union { int8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x3 (int16_t * __a, int16x8x3_t __b) +{ + union { int16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x3 (int32_t * __a, int32x4x3_t __b) +{ + union { int32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b) +{ + union { int64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11696,6 +11728,14 @@ vst1q_p64_x2 (poly64_t * __a, poly64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b) +{ + union { poly64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11759,6 +11799,24 @@ vst1q_f32_x2 (float32_t * __a, float32x4x2_t __b) __builtin_neon_vst1q_x2v4sf (__a, __bu.__o); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x3 (float16_t * __a, float16x8x3_t __b) +{ + union { float16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b) +{ + union { float32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11819,6 +11877,38 @@ vst1q_u64_x2 (uint64_t * __a, uint64x2x2_t __b) __builtin_neon_vst1q_x2v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x3 (uint8_t * __a, uint8x16x3_t __b) +{ + union { uint8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x3 (uint16_t * __a, uint16x8x3_t __b) +{ + union { uint16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x3 (uint32_t * __a, uint32x4x3_t __b) +{ + union { uint32x4x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b) +{ + union { uint64x2x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11849,6 +11939,22 @@ vst1q_p16_x2 (poly16_t * __a, poly16x8x2_t __b) __builtin_neon_vst1q_x2v8hi ((__builtin_neon_hi *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x3 (poly8_t * __a, poly8x16x3_t __b) +{ + union { poly8x16x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b) +{ + union { poly16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20533,6 +20639,14 @@ vst1q_bf16_x2 (bfloat16_t * __a, bfloat16x8x2_t __b) __builtin_neon_vst1q_x2v8bf (__a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b) +{ + union { bfloat16x8x3_t __i; __builtin_neon_ci __o; } __bu = { __b }; + __builtin_neon_vst1q_x3v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index 496d267fab8..b1886372a1f 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -311,6 +311,7 @@ VAR10 (LOAD1, vld1_dup, VAR7 (STORE1, vst1_x2, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR14 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index 088277ee6ed..b69ed24c018 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5145,6 +5145,30 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_store1_3reg")] ) +(define_insn "neon_vst1q_x3" + [(set (match_operand:CI 0 "neon_struct_operand" "=Um") + (unspec:CI [(match_operand:CI 1 "s_register_operand" "w") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST1))] + "TARGET_NEON" +{ + int regno = REGNO (operands[1]); + rtx ops[4]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + output_asm_insn ("vst1.\t{%P1, %P2, %P3}, %A0", ops); + + ops[1] = gen_rtx_REG (DImode, regno + 6); + ops[2] = gen_rtx_REG (DImode, regno + 8); + ops[3] = gen_rtx_REG (DImode, regno + 10); + output_asm_insn ("vst1.\t{%P1, %P2, %P3}, %A0", ops); + return ""; +} + [(set_attr "type" "neon_store1_3reg")] +) + (define_insn "neon_vst1_x4" [(set (match_operand:OI 0 "neon_struct_operand" "=Um") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c index 232feafade0..ba30fda514f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -61,10 +61,70 @@ void test_vst1q_p16_x2 (poly16_t * ptr, poly16x8x2_t val) vst1q_p16_x2 (ptr, val); } +void test_vst1q_u8_x3 (uint8_t * ptr, uint8x16x3_t val) +{ + vst1q_u8_x3 (ptr, val); +} + +void test_vst1q_u16_x3 (uint16_t * ptr, uint16x8x3_t val) +{ + vst1q_u16_x3 (ptr, val); +} + +void test_vst1q_u32_x3 (uint32_t * ptr, uint32x4x3_t val) +{ + vst1q_u32_x3 (ptr, val); +} + +void test_vst1q_u64_x3 (uint64_t * ptr, uint64x2x3_t val) +{ + vst1q_u64_x3 (ptr, val); +} + +void test_vst1q_s8_x3 (int8_t * ptr, int8x16x3_t val) +{ + vst1q_s8_x3 (ptr, val); +} + +void test_vst1q_s16_x3 (int16_t * ptr, int16x8x3_t val) +{ + vst1q_s16_x3 (ptr, val); +} + +void test_vst1q_s32_x3 (int32_t * ptr, int32x4x3_t val) +{ + vst1q_s32_x3 (ptr, val); +} + +void test_vst1q_s64_x3 (int64_t * ptr, int64x2x3_t val) +{ + vst1q_s64_x3 (ptr, val); +} + +void test_vst1q_f32_x3 (float32_t * ptr, float32x4x3_t val) +{ + vst1q_f32_x3 (ptr, val); +} + +void test_vst1q_p8_x3 (poly8_t * ptr, poly8x16x3_t val) +{ + vst1q_p8_x3 (ptr, val); +} + +void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val) +{ + vst1q_p16_x3 (ptr, val); +} + + /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c index 2a4579f0aae..2593c31c756 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_bf16_x2 (bfloat16_t * ptr, bfloat16x8x2_t val) vst1q_bf16_x2 (ptr, val); } +void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val) +{ + vst1q_bf16_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c index 61a7e558c48..28e949b557a 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_f16_x2 (float16_t * ptr, float16x8x2_t val) vst1q_f16_x2 (ptr, val); } +void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val) +{ + vst1q_f16_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c index 82f3dad293c..7878d936b9f 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -10,4 +10,10 @@ void test_vst1q_p64_x2 (poly64_t * ptr, poly64x2x2_t val) vst1q_p64_x2 (ptr, val); } +void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val) +{ + vst1q_p64_x3 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ From patchwork Tue Oct 10 14:04:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ezra Sitorus X-Patchwork-Id: 150809 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp228107vqb; Tue, 10 Oct 2023 07:08:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGbC+7AFozQ7h3RoH4rpvN8zZvSuWdETAj11qXnpqV9KCIbsEZwLUai6/2C69wu0953El7 X-Received: by 2002:a17:907:1dd8:b0:9ad:f143:e554 with SMTP id og24-20020a1709071dd800b009adf143e554mr14553418ejc.30.1696946917027; Tue, 10 Oct 2023 07:08:37 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696946917; cv=pass; d=google.com; s=arc-20160816; b=EYkVqE+MbJE144PgLHitrEefLzkSsSIqRoCktMq07Yana50gJ22BcdT6+96W8qDigQ T070aTQ5eWr+VFNH2LyXkNgwvv22P4fFeg0PYzedTkVADrxrz+qOeJwM9+koBlYbO9OA MBt2RYHazlpMQZljctmrk94i4PuzCcAECpUeu5yW+TAj1x0c13kPUPCXPELsRfXEa68i 3m3YkKw+KHC9DrH1TOBtz9+yAqgDb6o8+fZVsR7YQr93FvvYSZ5pbPaq0uuxUm6NwzZj Pvhd27oZAEnrZfqwVep8rq7e6dtJpPb7gzarEHQHygTNU5bb0OmJV4i2DqKpWV6cmaLy +RqA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-signature :dmarc-filter:delivered-to; bh=LVy8h4DA3bPbJIsxJQ+qxdQq3dEuiWTzVDcbPB1lE18=; fh=cdLUSjbFO0/cTi+z3xcckFOOtvTDyNZWtn2WcodW9fw=; b=MuaZJhaujX2mahW6E71O82AE058osgWeero1V8Q+T/kV9B/R9SMFpgKb8138MAMtyq LraTRglxq6AaRZignyVUZNAz64NFZ/YqlxikyvP1tgAc/X083ElOmbxc6enzKWbCNNif 64fpYzQXf2yjRToshu4Mxyn+EeBjsAOWdMTMnRBd9AEG+kmEVcaoyvpdC8Rjv9hm1xva VGLFxwnkTjKc+KAEunSWW8l194DSzh+1KS09tIGQKmpECgpgy2ArkyximjcBEPxlMWKa GrvRNbEBqkztx1MZTQQ0IgutSuLCUMm/qwgQoP78orPZT11rTicmVPzZ9fajfasHzZ4w D85Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=TJSsTkpk; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=TJSsTkpk; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id j18-20020a170906475200b00988939ad0bdsi5550602ejs.321.2023.10.10.07.08.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Oct 2023 07:08:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=TJSsTkpk; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=TJSsTkpk; arc=pass (i=1 spf=pass spfdomain=arm.com dmarc=pass fromdomain=arm.com); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id E24DB386190D for ; Tue, 10 Oct 2023 14:06:41 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-HE1-obe.outbound.protection.outlook.com (mail-he1eur04on2047.outbound.protection.outlook.com [40.107.7.47]) by sourceware.org (Postfix) with ESMTPS id CD65F3856DC7 for ; Tue, 10 Oct 2023 14:05:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CD65F3856DC7 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LVy8h4DA3bPbJIsxJQ+qxdQq3dEuiWTzVDcbPB1lE18=; b=TJSsTkpkQWQ5jwL2YfcGtyTv5SpU5I6Kz36VZfIwrmzryvxmdssSlDDFI240ng7b3XgulysvFfjtQqUkRn0ajAKkW7HV/6Dg+a8enD2M0EMouF8+CyX4MUYL+UD6qEYitaRoU5K3/A+rGaYqtQ6kaSoEFviQCTtPyKiNx1NQLOA= Received: from DU2PR04CA0246.eurprd04.prod.outlook.com (2603:10a6:10:28e::11) by DU2PR08MB7326.eurprd08.prod.outlook.com (2603:10a6:10:2e5::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.43; Tue, 10 Oct 2023 14:05:12 +0000 Received: from DBAEUR03FT035.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:28e:cafe::8b) by DU2PR04CA0246.outlook.office365.com (2603:10a6:10:28e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.38 via Frontend Transport; Tue, 10 Oct 2023 14:05:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT035.mail.protection.outlook.com (100.127.142.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:05:12 +0000 Received: ("Tessian outbound d219f9a4f5c9:v211"); Tue, 10 Oct 2023 14:05:12 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: dbf6d05bb06b0b2a X-CR-MTA-TID: 64aa7808 Received: from 0b70640f4aef.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id CB3F2AE0-6C02-4D2D-A51F-8966E65F4AE1.1; Tue, 10 Oct 2023 14:05:04 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 0b70640f4aef.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Tue, 10 Oct 2023 14:05:04 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=F/9l+G4mwW3Jti1mV1VyzsoW33yMBAePlQBpWMuXVL6TG6sOusrsS/WRZ515OHrQLHCZdgRk/sF0/GqDJwfOZCllhmwUYZhxTE+vJllm6Oe5x+tHAv4HQLEIrphmujtkItkj0Z3Q/U509MdZnTqNV3FfHkMabL/LMoSDovt0NWc/z97yYJHs421v0driLukLqWVP1pWAEIIuedStMDPKJe/P/YQx5GgkOa6BpgZcREi/0eLKCdYKbPhHOqFd3qRNbh6WLyKKX3MDShL76PyvzaIuWuLNquolHryXHno/m50f40cRAe+Wx1bes71zMZh2mKPxvuVuUpL79v/AcSaBAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=LVy8h4DA3bPbJIsxJQ+qxdQq3dEuiWTzVDcbPB1lE18=; b=Mdj5tEQMaISA2i3wv1GNFEdIZsMCHK6Cn5P3njUJc1JpCTm8fxsW4psTkbicNDbHhbK5+cJfngb3sXLDDB+CbjekyYdO8zb5Ae33zFMj34m0SfQNT8JP2kmpJGE182MO6dRBVwCzY2c2ljvzhhGCN/6ogEWru2u1Xzvmzod7pz0Wi4RvChW8aAwAaH1Mq77//GgT/eJpt4uyzbdJs7cBIKEjnNJEUwHCKlb8bo7WIKL8ShJMG8CIRZOoCWicpjAEXXBzYm4QMHmKUjY3W00mymizP3ZlvAeWxy7yfjKmvC1f3iAGJenCWr2ojvm1NL2NhPk87DNp9tpGKwirhkw/Pw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=LVy8h4DA3bPbJIsxJQ+qxdQq3dEuiWTzVDcbPB1lE18=; b=TJSsTkpkQWQ5jwL2YfcGtyTv5SpU5I6Kz36VZfIwrmzryvxmdssSlDDFI240ng7b3XgulysvFfjtQqUkRn0ajAKkW7HV/6Dg+a8enD2M0EMouF8+CyX4MUYL+UD6qEYitaRoU5K3/A+rGaYqtQ6kaSoEFviQCTtPyKiNx1NQLOA= Received: from DB8PR06CA0060.eurprd06.prod.outlook.com (2603:10a6:10:120::34) by AM7PR08MB5383.eurprd08.prod.outlook.com (2603:10a6:20b:102::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6863.37; Tue, 10 Oct 2023 14:05:02 +0000 Received: from DBAEUR03FT063.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:120:cafe::7a) by DB8PR06CA0060.outlook.office365.com (2603:10a6:10:120::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.37 via Frontend Transport; Tue, 10 Oct 2023 14:05:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DBAEUR03FT063.mail.protection.outlook.com (100.127.142.255) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6886.23 via Frontend Transport; Tue, 10 Oct 2023 14:05:02 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX03.Arm.com (10.251.24.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Tue, 10 Oct 2023 14:05:01 +0000 Received: from e127754.arm.com (10.57.5.240) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Tue, 10 Oct 2023 14:05:01 +0000 From: To: CC: , Subject: [PATCH 3/3] [GCC] arm: vst1q_types_x4 ACLE intrinsics Date: Tue, 10 Oct 2023 15:04:45 +0100 Message-ID: <20231010140445.2084-4-Ezra.Sitorus@arm.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20231010140445.2084-1-Ezra.Sitorus@arm.com> References: <20231010140445.2084-1-Ezra.Sitorus@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DBAEUR03FT063:EE_|AM7PR08MB5383:EE_|DBAEUR03FT035:EE_|DU2PR08MB7326:EE_ X-MS-Office365-Filtering-Correlation-Id: 3e4bb5b2-2373-4021-5426-08dbc999ebea x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: VuZDkyJnUxCdcxto4TpjSo1sjm07TJM068EGnIEZrAjApsjJOrptH1fssNPoZY/loDf6P4Isa4dYb5z95YHYQWiAXm/d3NbjytbFjRzvMdt7NSD+rg//pAzV8FOLWtYInmB49t8oibfMpxmA00vQAsN6Y9cn3ePNbkjv7+O6MQhNkO7AfT0RxK/s0Sjo8+/9TJk9eGStp9wnGwrkSqbwdKQwrxgn2r6eOWylKErX4FKSkHum8jeOoIc5xVz2dVFWkQ3Of7jCZSMlYia8wuC5ow/FNwPdvkQFD/4X5/0trR6pSQDL4LwofKXwRAXKJdBOaKGAIN+xhPu4Slbwi4AZOFBso1a/OPeFSHuX+j8pEtnX7rkvvGXcEkSywJPQ9OfU0RlrssTMQKmWWgt2RpdyTdtbypkcBsTK08NIX8CFwRvdGCj9RlwO4Cj5RFG5b1ss+/hQmn/5j813R6lpNU4JU1jpQXgSTku9M9ISJj650tdspjOKozyhYpUdLQ9MH9zaBq06WxqE7xY84+OGl02oba6vSAEpZ32vaSx/QlHIkF5qnPc2P4bi7WVmKGeNvWpNquzuHcU1q7LD5q0zlMqek9QR7KT/uv+663dL+L482VBu2pfQm04pVeGSjbfOaNfV8yuTqzslvXFDwGiS8lT87WAq/DT71dLyo7tvqKbhKxzERgJKyO3OwhRR3IB0GQSzbwglm5l/kjx792HMFYwOfgGhySy7jzfTN632/nC/G7pad0WfA7ROgKw5Ahk8HEFmlAZAnvO7iEiW5f50jnb32gL7nf/RncHsJsHjCSdHPq8= X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(39860400002)(396003)(136003)(346002)(376002)(230922051799003)(186009)(82310400011)(64100799003)(451199024)(1800799009)(46966006)(36840700001)(6666004)(82740400003)(2616005)(7696005)(1076003)(41300700001)(478600001)(2906002)(336012)(30864003)(83380400001)(47076005)(966005)(2876002)(426003)(70586007)(5660300002)(6916009)(54906003)(70206006)(8676002)(4326008)(8936002)(26005)(316002)(36756003)(356005)(36860700001)(81166007)(40480700001)(86362001)(84970400001)(36900700001)(357404004); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR08MB5383 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 7902d4fe-0fee-49d3-f30c-08dbc999e5d4 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: uKkQCxeBuEB0v4dJac3c1Urc4QvWEGajLyzPEcn3hpmSRgtx5ZM0HqaVTjROMRKZTBrmofZpDhIroOnR5PMkJJ+33Lwtq8/4/ILqZWgb5qXLU5tJPa3gt4DigaJvmrrUbEV+lUAnYFMEAdfRR0PikfS0flQKIP26EtJjAH/wn+pzT+D0jBZgG+8bnbQ86vewXpOBBIn5ppYK5ETzQzvppIs+IRxIcHOu7kkqVwdqw9j/wdHPEzBbOC2rlP5bgG14gyJu3SQM4QVOJ8eyNpyLTwykJrfM9LXDlTmsuhEsND6jGRJjoHmhcEj80LmQDIbQRU5ZVQENQNZEl19+w8m7YmuJ83KHIMaViObhmnIO3cV8mRzKygmk+z7u2mrUIfb721wJUZlI5SEWBls5dOYa37RjVKHDgELTgBOq2cO/rd0n9XjV0T3h5JvN+DyhVDhaFrR6fdSH7OL0ekodCQGU4ZjUOftjEY8K9W3ciesDBYm79LVQ34a+2/1hy4Y4L6sYfo53PYvYEI4phBbGP/3bB+Al8gBOqjg/mZlKn8/oHgGyF5e2ywvKQkdCYPRv2/w/G1cGSiF+p+lyaqhjoBHHq110EDvgKPFSZwjpZuRVMRXg+Pt9jrRMAS8WD2JHSy1Er+t6YLLlrDjUGCd6KVYg5bWur//3TZ0gbOqeGOSse9Te51eW+mKkpLVCnYABwje2pHW4+B5hzmk6Ul/k8bR6cBuXPZizwZknAikNHmngc5WnP2k+5INax3G1vMW9kN232HdkOh7fnB9wcCkxTGSABykAIG6tF3qyP+rwrRPgN2Q= X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(396003)(136003)(39860400002)(376002)(346002)(230922051799003)(451199024)(1800799009)(82310400011)(186009)(64100799003)(36840700001)(40470700004)(46966006)(2616005)(1076003)(2906002)(7696005)(40460700003)(2876002)(81166007)(36756003)(82740400003)(86362001)(36860700001)(47076005)(40480700001)(426003)(26005)(336012)(83380400001)(5660300002)(8676002)(8936002)(84970400001)(4326008)(966005)(478600001)(41300700001)(316002)(6916009)(54906003)(70206006)(70586007)(6666004)(30864003)(357404004); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Oct 2023 14:05:12.8082 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3e4bb5b2-2373-4021-5426-08dbc999ebea X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT035.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU2PR08MB7326 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779377810802414436 X-GMAIL-MSGID: 1779377810802414436 From: Ezra Sitorus This patch is part of a series of patches implementing the _xN variants of the vst1q intrinsic for AArch32. This patch adds the _x4 variants of the vst1q intrinsic. ACLE documents are at https://developer.arm.com/documentation/ihi0053/latest/ ISA documents are at https://developer.arm.com/documentation/ddi0487/latest/ gcc/ChangeLog: * config/arm/arm_neon.h (vst1q_u8_x4, vst1q_u16_x4, vst1q_u32_x4, vst1q_u64_x4): New. (vst1q_s8_x4, vst1q_s16_x4, vst1q_s32_x4, vst1q_s64_x4): New. (vst1q_f16_x4, vst1q_f32_x4): New. (vst1q_p8_x4, vst1q_p16_x4, vst1q_p64_x4): New. (vst1q_bf16_x4): New. * config/arm/arm_neon_builtins.def (vst1q_x4): New entries. * config/arm/neon.md (neon_vst1q_x4): New. gcc/testsuite/ChangeLog: * gcc.target/arm/simd/vst1q_base_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_bf16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_fp16_xN_1.c: Add new tests. * gcc.target/arm/simd/vst1q_p64_xN_1.c: Add new tests. --- gcc/config/arm/arm_neon.h | 114 ++++++++++++++++++ gcc/config/arm/arm_neon_builtins.def | 1 + gcc/config/arm/neon.md | 26 ++++ .../gcc.target/arm/simd/vst1q_base_xN_1.c | 59 +++++++++ .../gcc.target/arm/simd/vst1q_bf16_xN_1.c | 8 +- .../gcc.target/arm/simd/vst1q_fp16_xN_1.c | 6 + .../gcc.target/arm/simd/vst1q_p64_xN_1.c | 6 + 7 files changed, 219 insertions(+), 1 deletion(-) diff --git a/gcc/config/arm/arm_neon.h b/gcc/config/arm/arm_neon.h index 46ee888410f..df3e23b6e95 100644 --- a/gcc/config/arm/arm_neon.h +++ b/gcc/config/arm/arm_neon.h @@ -11391,6 +11391,38 @@ vst1q_s64_x3 (int64_t * __a, int64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s8_x4 (int8_t * __a, int8x16x4_t __b) +{ + union { int8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s16_x4 (int16_t * __a, int16x8x4_t __b) +{ + union { int16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s32_x4 (int32_t * __a, int32x4x4_t __b) +{ + union { int32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_s64_x4 (int64_t * __a, int64x2x4_t __b) +{ + union { int64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_s8_x3 (int8_t * __a, int8x8x3_t __b) @@ -11736,6 +11768,14 @@ vst1q_p64_x3 (poly64_t * __a, poly64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p64_x4 (poly64_t * __a, poly64x2x4_t __b) +{ + union { poly64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + #pragma GCC pop_options __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) @@ -11817,6 +11857,24 @@ vst1q_f32_x3 (float32_t * __a, float32x4x3_t __b) __builtin_neon_vst1q_x3v4sf (__a, __bu.__o); } +#if defined (__ARM_FP16_FORMAT_IEEE) || defined (__ARM_FP16_FORMAT_ALTERNATIVE) +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f16_x4 (float16_t * __a, float16x8x4_t __b) +{ + union { float16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hf (__a, __bu.__o); +} +#endif + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_f32_x4 (float32_t * __a, float32x4x4_t __b) +{ + union { float32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4sf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_u8 (uint8_t * __a, uint8x16_t __b) @@ -11909,6 +11967,38 @@ vst1q_u64_x3 (uint64_t * __a, uint64x2x3_t __b) __builtin_neon_vst1q_x3v2di ((__builtin_neon_di *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u8_x4 (uint8_t * __a, uint8x16x4_t __b) +{ + union { uint8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u16_x4 (uint16_t * __a, uint16x8x4_t __b) +{ + union { uint16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u32_x4 (uint32_t * __a, uint32x4x4_t __b) +{ + union { uint32x4x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v4si ((__builtin_neon_si *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_u64_x4 (uint64_t * __a, uint64x2x4_t __b) +{ + union { uint64x2x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v2di ((__builtin_neon_di *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1q_p8 (poly8_t * __a, poly8x16_t __b) @@ -11955,6 +12045,22 @@ vst1q_p16_x3 (poly16_t * __a, poly16x8x3_t __b) __builtin_neon_vst1q_x3v8hi ((__builtin_neon_hi *) __a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p8_x4 (poly8_t * __a, poly8x16x4_t __b) +{ + union { poly8x16x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v16qi ((__builtin_neon_qi *) __a, __bu.__o); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_p16_x4 (poly16_t * __a, poly16x8x4_t __b) +{ + union { poly16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8hi ((__builtin_neon_hi *) __a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst1_lane_s8 (int8_t * __a, int8x8_t __b, const int __c) @@ -20647,6 +20753,14 @@ vst1q_bf16_x3 (bfloat16_t * __a, bfloat16x8x3_t __b) __builtin_neon_vst1q_x3v8bf (__a, __bu.__o); } +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +vst1q_bf16_x4 (bfloat16_t * __a, bfloat16x8x4_t __b) +{ + union { bfloat16x8x4_t __i; __builtin_neon_xi __o; } __bu = { __b }; + __builtin_neon_vst1q_x4v8bf (__a, __bu.__o); +} + __extension__ extern __inline void __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) vst2_bf16 (bfloat16_t * __ptr, bfloat16x4x2_t __val) diff --git a/gcc/config/arm/arm_neon_builtins.def b/gcc/config/arm/arm_neon_builtins.def index b1886372a1f..12f78800588 100644 --- a/gcc/config/arm/arm_neon_builtins.def +++ b/gcc/config/arm/arm_neon_builtins.def @@ -313,6 +313,7 @@ VAR7 (STORE1, vst1q_x2, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x3, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) VAR7 (STORE1, vst1q_x3, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR7 (STORE1, vst1_x4, v8qi, v4hi, v2si, di, v4hf, v2sf, v4bf) +VAR7 (STORE1, vst1q_x4, v16qi, v8hi, v4si, v2di, v8hf, v4sf, v8bf) VAR14 (STORE1, vst1, v8qi, v4hi, v4hf, v2si, v2sf, di, v16qi, v8hi, v8hf, v4si, v4sf, v2di, v4bf, v8bf) diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index b69ed24c018..2fa4f85b820 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -5169,6 +5169,32 @@ if (BYTES_BIG_ENDIAN) [(set_attr "type" "neon_store1_3reg")] ) +(define_insn "neon_vst1q_x4" + [(set (match_operand:XI 0 "neon_struct_operand" "=Um") + (unspec:XI [(match_operand:XI 1 "s_register_operand" "w") + (unspec:VDQX [(const_int 0)] UNSPEC_VSTRUCTDUMMY)] + UNSPEC_VST1))] + "TARGET_NEON" +{ + int regno = REGNO (operands[1]); + rtx ops[5]; + ops[0] = operands[0]; + ops[1] = gen_rtx_REG (DImode, regno); + ops[2] = gen_rtx_REG (DImode, regno + 2); + ops[3] = gen_rtx_REG (DImode, regno + 4); + ops[4] = gen_rtx_REG (DImode, regno + 6); + output_asm_insn ("vst1.\t{%P1, %P2, %P3, %P4}, %A0", ops); + + ops[1] = gen_rtx_REG (DImode, regno + 8); + ops[2] = gen_rtx_REG (DImode, regno + 10); + ops[3] = gen_rtx_REG (DImode, regno + 12); + ops[4] = gen_rtx_REG (DImode, regno + 14); + output_asm_insn ("vst1.\t{%P1, %P2, %P3, %P4}, %A0", ops); + return ""; +} + [(set_attr "type" "neon_store1_4reg")] +) + (define_insn "neon_vst1_x4" [(set (match_operand:OI 0 "neon_struct_operand" "=Um") (unspec:OI [(match_operand:OI 1 "s_register_operand" "w") diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c index ba30fda514f..461aae3af62 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_base_xN_1.c @@ -116,15 +116,74 @@ void test_vst1q_p16_x3 (poly16_t * ptr, poly16x8x3_t val) vst1q_p16_x3 (ptr, val); } +void test_vst1q_u8_x4 (uint8_t * ptr, uint8x16x4_t val) +{ + vst1q_u8_x4 (ptr, val); +} + +void test_vst1q_u16_x4 (uint16_t * ptr, uint16x8x4_t val) +{ + vst1q_u16_x4 (ptr, val); +} + +void test_vst1q_u32_x4 (uint32_t * ptr, uint32x4x4_t val) +{ + vst1q_u32_x4 (ptr, val); +} + +void test_vst1q_u64_x4 (uint64_t * ptr, uint64x2x4_t val) +{ + vst1q_u64_x4 (ptr, val); +} + +void test_vst1q_s8_x4 (int8_t * ptr, int8x16x4_t val) +{ + vst1q_s8_x4 (ptr, val); +} + +void test_vst1q_s16_x4 (int16_t * ptr, int16x8x4_t val) +{ + vst1q_s16_x4 (ptr, val); +} + +void test_vst1q_s32_x4 (int32_t * ptr, int32x4x4_t val) +{ + vst1q_s32_x4 (ptr, val); +} + +void test_vst1q_s64_x4 (int64_t * ptr, int64x2x4_t val) +{ + vst1q_s64_x4 (ptr, val); +} + +void test_vst1q_f32_x4 (float32_t * ptr, float32x4x4_t val) +{ + vst1q_f32_x4 (ptr, val); +} + +void test_vst1q_p8_x4 (poly8_t * ptr, poly8x16x4_t val) +{ + vst1q_p8_x4 (ptr, val); +} + +void test_vst1q_p16_x4 (poly16_t * ptr, poly16x8x4_t val) +{ + vst1q_p16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.8\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 3 } } */ /* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ +/* { dg-final { scan-assembler-times {vst1.32\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 6 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 4 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c index 2593c31c756..84fa8509db8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_bf16_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_bf16_x3 (bfloat16_t * ptr, bfloat16x8x3_t val) vst1q_bf16_x3 (ptr, val); } +void test_vst1q_bf16_x4 (bfloat16_t * ptr, bfloat16x8x4_t val) +{ + vst1q_bf16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ -/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c index 28e949b557a..5b13edf9998 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_fp16_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_f16_x3 (float16_t * ptr, float16x8x3_t val) vst1q_f16_x3 (ptr, val); } +void test_vst1q_f16_x4 (float16_t * ptr, float16x8x4_t val) +{ + vst1q_f16_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+\]\n} 1 } } */ /* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.16\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+\]\n} 2 } } */ diff --git a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c index 7878d936b9f..f49917d5ec8 100644 --- a/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c +++ b/gcc/testsuite/gcc.target/arm/simd/vst1q_p64_xN_1.c @@ -15,5 +15,11 @@ void test_vst1q_p64_x3 (poly64_t * ptr, poly64x2x3_t val) vst1q_p64_x3 (ptr, val); } +void test_vst1q_p64_x4 (poly64_t * ptr, poly64x2x4_t val) +{ + vst1q_p64_x4 (ptr, val); +} + /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+-d[0-9]+\}, \[r[0-9]+:64\]\n} 1 } } */ /* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */ +/* { dg-final { scan-assembler-times {vst1.64\t\{d[0-9]+, d[0-9]+, d[0-9]+, d[0-9]+\}, \[r[0-9]+:64\]\n} 2 } } */