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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id lz6-20020a170906fb0600b0099cf9bf4c98sm7278399ejb.8.2023.10.09.15.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Oct 2023 15:47:16 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Palmer Dabbelt , Andrew Waterman , Philipp Tomsich , Jeff Law , Patrick O'Neill , Vineet Gupta Cc: =?utf-8?q?Christoph_M=C3=BCllner?= Subject: [PATCH] RISC-V: Make xtheadcondmov-indirect tests robust against instruction reordering Date: Tue, 10 Oct 2023 00:47:11 +0200 Message-ID: <20231009224711.1105509-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_MANYTO, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779319881682804056 X-GMAIL-MSGID: 1779319881682804056 From: Christoph Müllner Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA") A recent change broke the xtheadcondmov-indirect tests, because the order of emitted instructions changed. Since the test is too strict when testing for a fixed instruction order, let's change the tests to simply count instruction, like it is done for similar tests. Reported-by: Patrick O'Neill Signed-off-by: Christoph Müllner gcc/testsuite/ChangeLog: * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against instruction reordering. Signed-off-by: Christoph Müllner --- .../gcc.target/riscv/xtheadcondmov-indirect.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c index c3253ba5239..eba1b86137b 100644 --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c @@ -1,8 +1,7 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv32gc_xtheadcondmov -fno-sched-pressure" { target { rv32 } } } */ -/* { dg-options "-march=rv64gc_xtheadcondmov -fno-sched-pressure" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */ +/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */ /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */ -/* { dg-final { check-function-bodies "**" "" } } */ /* ** ConEmv_imm_imm_reg: @@ -116,3 +115,9 @@ int ConNmv_reg_reg_reg(int x, int y, int z, int n) return z; return n; } + +/* { dg-final { scan-assembler-times "addi\t" 5 } } */ +/* { dg-final { scan-assembler-times "li\t" 4 } } */ +/* { dg-final { scan-assembler-times "sub\t" 4 } } */ +/* { dg-final { scan-assembler-times "th.mveqz\t" 4 } } */ +/* { dg-final { scan-assembler-times "th.mvnez\t" 4 } } */