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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 3C025360707; Sun, 6 Nov 2022 08:01:28 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 1/6] dt-bindings: pinctrl: update pcie/pwm/spi bindings for MT7986 SoC Date: Sun, 6 Nov 2022 09:01:08 +0100 Message-Id: <20221106080114.7426-2-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 930663f8-d39f-4ea1-b476-287d1e74bae5 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733018723626173?= X-GMAIL-MSGID: =?utf-8?q?1748733018723626173?= From: Frank Wunderlich Allow multiple items for pcie, pwm and spi function. Signed-off-by: Frank Wunderlich Acked-by: Krzysztof Kozlowski --- .../bindings/pinctrl/mediatek,mt7986-pinctrl.yaml | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 89b8f3dd67a1..75766956cfad 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -197,7 +197,9 @@ patternProperties: then: properties: groups: - enum: [pcie_clk, pcie_wake, pcie_pereset] + items: + enum: [pcie_clk, pcie_wake, pcie_pereset] + maxItems: 3 - if: properties: function: @@ -205,7 +207,9 @@ patternProperties: then: properties: groups: - enum: [pwm0, pwm1_0, pwm1_1] + items: + enum: [pwm0, pwm1_0, pwm1_1] + maxItems: 2 - if: properties: function: @@ -213,7 +217,9 @@ patternProperties: then: properties: groups: - enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + items: + enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3] + maxItems: 2 - if: properties: function: From patchwork Sun Nov 6 08:01:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 16082 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1381306wru; Sun, 6 Nov 2022 01:03:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7G2HuEZvZmHdyKgTGln4lYyx08EEv1APtKV2MoroHe8zGPZ+EFTViOziPc6GYtaSDIGvxE X-Received: by 2002:a05:6402:27cf:b0:462:75b3:a277 with SMTP id c15-20020a05640227cf00b0046275b3a277mr45982588ede.175.1667721782509; Sun, 06 Nov 2022 01:03:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667721782; cv=none; d=google.com; s=arc-20160816; b=xGRFQK5uG24c8tOpGTmn7FrZGezTK4EqflXeuKtsrRV77Gl/EdEn6qPBWPNCePgLo8 zNVb/9lNnAgWaw4qbiPz0GoLjWthrD27gHbLHYJFYXGAZeUOo9TMSbl2qpmjw8MNZK0L XzHH1r//3X8iwNXJym4dmz/c4s9BTXPH+ZJDjQshNXL7UVZUfFxHzYeWh6dEv9ruqRxi VkltevUhUqy0csufOmMDfhTcW1nZl1hCxwUNgBa+q7ofBFbEIsPGwUFMYFqZ9HPccWaH l3BnhKbNYH522g7nVppabN2N5ApFbEJeVETJah1tiPWbMiW/XXUgIn46MZ6UMkhydXlC w/6w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CwzgypedxlgZw3WEvEFkcsmGoeorFZCgPtvDphQ59OA=; b=pahbnjwqDhjsQh7L4O6kM2JT+fYMTVejq9bV+FozBeBBCDIJscbYAPbvF1a6rhGQo7 xmAnOObqM5cFZTJqUgK3bS3lA2UTMQK6ahg1cCa8L97pTv1NX201i78s/OFkId5Y0ZPQ sPYy5ZE62qeskjyy4PVfPoEhstH2/0GYT/+lzianlw2DxkbSyUfrO7RD0hFw939eDs9h gGcrrtD9t72Fq3nwEnzvKQwpwICOtaAfo1VnPhhuHWWeminWat5kaI6aVm0Mox9rcEVd /sUsm/I7nEaaLYEC0bODH31H/lf3yq30TIZ2ExqM0ikwc9aukq+p7n8qFochWhvfJjHp e76A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mailerdienst.de header.s=20200217 header.b=Q1LcpD1a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id E85063608D6; Sun, 6 Nov 2022 08:01:28 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/6] dt-bindings: pinctrl: update uart/mmc bindings for MT7986 SoC Date: Sun, 6 Nov 2022 09:01:09 +0100 Message-Id: <20221106080114.7426-3-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 3e7652be-892b-4782-86de-b1a45213699a X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733036005882107?= X-GMAIL-MSGID: =?utf-8?q?1748733036005882107?= From: Frank Wunderlich Fix mmc and uart pins after uart splitting. Some pinmux pins of the mt7986 pinctrl driver is composed of multiple pinctrl groups, the original binding only allows one pinctrl group per dts node, this patch sets "maxItems" for these groups and add new examples to the binding documentation. Fixes: 65916a1ca90a ("dt-bindings: pinctrl: update bindings for MT7986 SoC") Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Acked-by: Krzysztof Kozlowski --- v3: - squashed version from sam - v2 was ack'd by Krzysztof, but sams patch included updated emmc-names and different structure for uart to allow 2 pingroups v2: - wrap on col 80 --- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 46 +++++++++++++++++-- 1 file changed, 41 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index 75766956cfad..b2b9c01efd70 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -87,6 +87,8 @@ patternProperties: "wifi_led" "led" 1, 2 "i2c" "i2c" 3, 4 "uart1_0" "uart" 7, 8, 9, 10 + "uart1_rx_tx" "uart" 42, 43 + "uart1_cts_rts" "uart" 44, 45 "pcie_clk" "pcie" 9 "pcie_wake" "pcie" 10 "spi1_0" "spi" 11, 12, 13, 14 @@ -98,9 +100,11 @@ patternProperties: "emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 "spi1_1" "spi" 23, 24, 25, 26 - "uart1_2" "uart" 29, 30, 31, 32 + "uart1_2_rx_tx" "uart" 29, 30 + "uart1_2_cts_rts" "uart" 31, 32 "uart1_1" "uart" 23, 24, 25, 26 - "uart2_0" "uart" 29, 30, 31, 32 + "uart2_0_rx_tx" "uart" 29, 30 + "uart2_0_cts_rts" "uart" 31, 32 "spi0" "spi" 33, 34, 35, 36 "spi0_wp_hold" "spi" 37, 38 "uart1_3_rx_tx" "uart" 35, 36 @@ -157,7 +161,7 @@ patternProperties: then: properties: groups: - enum: [emmc, emmc_rst] + enum: [emmc_45, emmc_51] - if: properties: function: @@ -227,8 +231,12 @@ patternProperties: then: properties: groups: - enum: [uart1_0, uart1_1, uart1_2, uart1_3_rx_tx, - uart1_3_cts_rts, uart2_0, uart2_1, uart0, uart1, uart2] + items: + enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1, + uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx, + uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts, + uart2_1, uart0, uart1, uart2] + maxItems: 2 - if: properties: function: @@ -362,6 +370,27 @@ examples: interrupt-parent = <&gic>; #interrupt-cells = <2>; + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi0_pins: spi0-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + uart1_pins: uart1-pins { mux { function = "uart"; @@ -369,6 +398,13 @@ examples: }; }; + uart1_3_pins: uart1-3-pins { + mux { + function = "uart"; + groups = "uart1_3_rx_tx", "uart1_3_cts_rts"; + }; + }; + uart2_pins: uart2-pins { mux { function = "uart"; From patchwork Sun Nov 6 08:01:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 16080 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1381214wru; Sun, 6 Nov 2022 01:02:51 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6g3iMDVFfsaYsx3A/rx+PJAvUPc70xAYaGelFT1mWhLEALVFORrgFCY+rJlKKnlRRGIwtN X-Received: by 2002:a17:902:834c:b0:187:49e0:fd4d with SMTP id z12-20020a170902834c00b0018749e0fd4dmr22278567pln.81.1667721771559; Sun, 06 Nov 2022 01:02:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667721771; cv=none; d=google.com; s=arc-20160816; b=xNF94gs//93qerqx2SwUgqb7GOrpVgq1Q4reBIjqEGHDB3xshCLARll8DkdjTAAy13 5CiavHLGgjsPCch1wiMiCtH4+RUba2PwzfZrw3/2J95ljK8XOY5btMUzaDo0iyjQD74a xiaiGduylJpsklyiBTX5kjkW5wINricvdGVKtLX62diNY/hQPSS/UyBap+W2AwOecJjJ YT9wuyy72Airwvg5itW2Anxmt5cT48eEtCDPsD3GPVtDAidYV9fOvEb+LVEXCL0i5db3 /eQxV+CyALV3YAN0y//L58i5EPkYmVaTy9hByo9EGeVjeDC3nAKgY/kCbTJFgEKvoM3g LtJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MHVO61sMpRHTxKeTwC3bQjHXnh5eWGHHpN5gb6vKtgc=; b=ynmAkV4UjZRTj4CG+N+vk5/RXArX47kCYGsMCFciU6wcfAoXJcWnPe0dJqihCGjR0o 9PqtoCeg4SsHn5m0cQuSLyxIOI9Tt7v070Ot1h/IdITGC68T07PkeeTWA8PA6lhDi3AW Mg7JJzbB4L9BXEMW6bgRE3WYEhKHFsWCx6u4iWiUfItgn5XTCPjGjfKfLzQPvVUU/9Eg Bypxw8c5Xvxf7ernAQp+beJ9e2Ng/dDK+YjmX5I7rBUJgc1uQw5F38VwEAH4uVVSP+el wsf3ig4HstQRFVUlCkgAiS6iiVld3jbipmJCKa+1u/1qYQ7uaELVOyBwtkLQPNrF95w7 fmsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mailerdienst.de header.s=20200217 header.b=YcXi9Kio; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 9223A3602A8; Sun, 6 Nov 2022 08:01:29 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/6] dt-bindings: pinctrl: mt7986: add generic bias-pull* support Date: Sun, 6 Nov 2022 09:01:10 +0100 Message-Id: <20221106080114.7426-4-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 5333ed4a-a8b8-42f9-93fa-0fd8ca8d62b3 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733024580151750?= X-GMAIL-MSGID: =?utf-8?q?1748733024580151750?= From: Sam Shih Since the bias-pull-{up,down} attribute already defines in pinctrl driver of mediatek MT7986 SoC, this patch updates bindings to support mediatek common bias-pull* function. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Acked-by: Krzysztof Kozlowski --- .../pinctrl/mediatek,mt7986-pinctrl.yaml | 50 +++++++++++++++++-- 1 file changed, 47 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml index b2b9c01efd70..216b356cd519 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7986-pinctrl.yaml @@ -292,9 +292,23 @@ patternProperties: bias-disable: true - bias-pull-up: true - - bias-pull-down: true + bias-pull-up: + oneOf: + - type: boolean + description: normal pull up. + - enum: [100, 101, 102, 103] + description: | + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. + + bias-pull-down: + oneOf: + - type: boolean + description: normal pull down. + - enum: [100, 101, 102, 103] + description: | + PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in + dt-bindings/pinctrl/mt65xx.h. input-enable: true @@ -346,6 +360,7 @@ examples: - | #include #include + #include soc { #address-cells = <2>; @@ -412,5 +427,34 @@ examples: }; }; + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + }; }; From patchwork Sun Nov 6 08:01:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 16081 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1381298wru; Sun, 6 Nov 2022 01:03:01 -0700 (PDT) X-Google-Smtp-Source: AMsMyM6MI2tFAoMP+tBoYp0RwXl2fwF6nfbyRyneDJk9oF4jOmuvp6YbuklT5ExZSHzHfBV2xxGA X-Received: by 2002:a17:903:26cd:b0:188:4c74:e1de with SMTP id jg13-20020a17090326cd00b001884c74e1demr20613820plb.56.1667721781314; Sun, 06 Nov 2022 01:03:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667721781; cv=none; d=google.com; s=arc-20160816; b=nJXzd7AUE9zSgcufjHSLAaemXm0uSE9uWXBNzM+eoSJMFNZMiy2WDuzPjHETW1ujzJ 80uf2volHu0kLVuqainu+Zu9aYG1Dpka1wVpF6sAJGJi+neo6jIs8hcHid/Cm1cFWeEC x+uAoc+qPGKmcg9Dwma/ztZTx+N4lKnVvCSmIKMfjOfHsuerhPK3Ewtlb9NcMTJI+qK5 6pEj2xqsMPt0icQFNizP4matVNAjmzH3Oj7R8gHb15W4MppW64wwOMxx1IX53csW/vVN GwrWVrNwrl4K6nVyPt8NZbHDlu+N5Wgy9MUZFGRly/ceJdO+T4o8xfYhv00AfXneNuya +OcA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pEJQGyDJSuh4+z5LtnMFKscBXW0isz3f4WizAj2Jdxw=; b=b8gNqQb7Ad+WauG6784xn1Ksbe3mxuwMLEsN3VzHUZnXWeaDs9fClUId3eHpLwBVtY 9LChAnUalXQFtX53CjWymLiZ9Sog6IKfoMHm1gBgkgWFwmzROQ7rs719Gih0PRN5J0Ou wuXwK+SSzoXYGdieS7ZTf7o1hhS/LqaF6DmWVhlQJMLJgb5CeT8Yh1YTcwiqdTzxCYvP 5K/sJeCMWuRD+ZfSzh2c790Lo6fVaw+qC3Ijb2aivuFK6KOjBo5fYomQ0Op/OR3OJaMu a+9lf4GbELZ66/EnYi7QhQ2u8WaZ4EFoganFvLFp2JaSPRvrluUehkRIlaqSUnK474/A 7YsA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mailerdienst.de header.s=20200217 header.b=YfVPiKnr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 3E916360707; Sun, 6 Nov 2022 08:01:30 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 4/6] pinctrl: mediatek: fix the pinconf register offset of some pins Date: Sun, 6 Nov 2022 09:01:11 +0100 Message-Id: <20221106080114.7426-5-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 13d05f96-153e-485d-878b-9d50fa9b3bcd X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733034693511265?= X-GMAIL-MSGID: =?utf-8?q?1748733034693511265?= From: Sam Shih Correct the bias-pull-up, bias-pull-down and bias-disable register offset of mt7986 pin-42 to pin-49, in the original driver, the relative offset value was erroneously decremented by 1. Fixes: 360de6728064 ("pinctrl: mediatek: add support for MT7986 SoC") Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 24 +++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index 95f32e62e02f..d13c59510468 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -316,10 +316,10 @@ static const struct mtk_pin_field_calc mt7986_pin_pupd_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x30, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x60, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x60, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x60, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x60, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x60, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x60, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x40, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x40, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x40, 0x10, 0, 1), @@ -354,10 +354,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r0_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x40, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x70, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x70, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x70, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x70, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x70, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x70, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x50, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x50, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x50, 0x10, 0, 1), @@ -392,10 +392,10 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(38, 38, IOCFG_LT_BASE, 0x50, 0x10, 9, 1), PIN_FIELD_BASE(39, 40, IOCFG_RB_BASE, 0x80, 0x10, 18, 1), PIN_FIELD_BASE(41, 41, IOCFG_RB_BASE, 0x80, 0x10, 12, 1), - PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 22, 1), - PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 20, 1), - PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 26, 1), - PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 24, 1), + PIN_FIELD_BASE(42, 43, IOCFG_RB_BASE, 0x80, 0x10, 23, 1), + PIN_FIELD_BASE(44, 45, IOCFG_RB_BASE, 0x80, 0x10, 21, 1), + PIN_FIELD_BASE(46, 47, IOCFG_RB_BASE, 0x80, 0x10, 27, 1), + PIN_FIELD_BASE(48, 49, IOCFG_RB_BASE, 0x80, 0x10, 25, 1), PIN_FIELD_BASE(50, 57, IOCFG_RT_BASE, 0x60, 0x10, 2, 1), PIN_FIELD_BASE(58, 58, IOCFG_RT_BASE, 0x60, 0x10, 1, 1), PIN_FIELD_BASE(59, 59, IOCFG_RT_BASE, 0x60, 0x10, 0, 1), From patchwork Sun Nov 6 08:01:12 2022 Content-Type: text/plain; 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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id D871C3608D6; Sun, 6 Nov 2022 08:01:30 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 5/6] pinctrl: mediatek: extend pinctrl-moore to support new bias functions Date: Sun, 6 Nov 2022 09:01:12 +0100 Message-Id: <20221106080114.7426-6-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 834ebe36-977f-4cff-aa59-d34b09342e20 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733046476884322?= X-GMAIL-MSGID: =?utf-8?q?1748733046476884322?= From: Sam Shih Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") introduced SoC specify 'pull_type' attribute to mtk_pinconf_bias_set_combo and mtk_pinconf_bias_get_combo, and make the functions able to support almost all Mediatek SoCs that use pinctrl-mtk-common-v2.c. This patch enables pinctrl_moore to support these functions. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- drivers/pinctrl/mediatek/pinctrl-moore.c | 49 ++++++++++++++++++++---- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/drivers/pinctrl/mediatek/pinctrl-moore.c b/drivers/pinctrl/mediatek/pinctrl-moore.c index 526faaebaf77..cdc002d29932 100644 --- a/drivers/pinctrl/mediatek/pinctrl-moore.c +++ b/drivers/pinctrl/mediatek/pinctrl-moore.c @@ -8,6 +8,7 @@ * */ +#include #include #include "pinctrl-moore.h" @@ -105,7 +106,7 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, { struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev); u32 param = pinconf_to_config_param(*config); - int val, val2, err, reg, ret = 1; + int val, val2, err, pullup, reg, ret = 1; const struct mtk_pin_desc *desc; desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin]; @@ -114,7 +115,13 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret != MTK_PUPD_SET_R1R0_00 && ret != MTK_DISABLE) + return -EINVAL; + } else if (hw->soc->bias_disable_get) { err = hw->soc->bias_disable_get(hw, desc, &ret); if (err) return err; @@ -123,7 +130,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (!pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 1, &ret); if (err) return err; @@ -132,7 +147,15 @@ static int mtk_pinconf_get(struct pinctrl_dev *pctldev, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_get) { + if (hw->soc->bias_get_combo) { + err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret); + if (err) + return err; + if (ret == MTK_PUPD_SET_R1R0_00 || ret == MTK_DISABLE) + return -EINVAL; + if (pullup) + return -EINVAL; + } else if (hw->soc->bias_get) { err = hw->soc->bias_get(hw, desc, 0, &ret); if (err) return err; @@ -235,7 +258,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, switch (param) { case PIN_CONFIG_BIAS_DISABLE: - if (hw->soc->bias_disable_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE); + if (err) + return err; + } else if (hw->soc->bias_disable_set) { err = hw->soc->bias_disable_set(hw, desc); if (err) return err; @@ -244,7 +271,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_UP: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 1, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 1); if (err) return err; @@ -253,7 +284,11 @@ static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, } break; case PIN_CONFIG_BIAS_PULL_DOWN: - if (hw->soc->bias_set) { + if (hw->soc->bias_set_combo) { + err = hw->soc->bias_set_combo(hw, desc, 0, arg); + if (err) + return err; + } else if (hw->soc->bias_set) { err = hw->soc->bias_set(hw, desc, 0); if (err) return err; From patchwork Sun Nov 6 08:01:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 16084 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp1381404wru; Sun, 6 Nov 2022 01:03:18 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4tPRLe/zNSXgqpu/dTi0Jga9FfYfrl+YppPGenhBTnypwPPzWas3OR6iZhG5Mc9vqacMQg X-Received: by 2002:a17:902:ea85:b0:187:1851:bb02 with SMTP id x5-20020a170902ea8500b001871851bb02mr38395354plb.57.1667721798302; Sun, 06 Nov 2022 01:03:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667721798; cv=none; d=google.com; s=arc-20160816; b=xOGP3z3wzX4L4xMOvXi77D+9ducX9BK6XF0FmBXSkkipqFIQwXoT6tsIlrK7jqG5Ke vepXx98cQ+mVA7mNNKI7i+0kZGiMjee4ihkrSAza4AX0zir5rVQ74xE2StPpKUEgJX3l LMy6LamUPQrikiuC5QZp8YuzZ8bRSBwjNNafUmjifm15GDS1NvHGJJpFikY0WhHufZiF 5d+VmFNOS/bpliHwYwlpzuKnI1reZMyX6nvhd2RZDa86I3wdSIsont6rZ5Rs5LvfeAuw bmnrin+/tGesxYPF3b9psSil3pg0uNH1gfXcESQRtDiVGaOvj1/iRjzYOLVNe83sYQZU ocZA== ARC-Message-Signature: i=1; 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(fttx-pool-80.245.79.199.bambit.de [80.245.79.199]) by mxbox3.masterlogin.de (Postfix) with ESMTPSA id 8820E360707; Sun, 6 Nov 2022 08:01:31 +0000 (UTC) From: Frank Wunderlich To: linux-mediatek@lists.infradead.org Cc: Frank Wunderlich , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Sean Wang , Sam Shih , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 6/6] pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC Date: Sun, 6 Nov 2022 09:01:13 +0100 Message-Id: <20221106080114.7426-7-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221106080114.7426-1-linux@fw-web.de> References: <20221106080114.7426-1-linux@fw-web.de> MIME-Version: 1.0 X-Mail-ID: 1833dc4d-5032-4cbc-ab32-c25b5990d83b X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748733052223628061?= X-GMAIL-MSGID: =?utf-8?q?1748733052223628061?= From: Sam Shih Commit fb34a9ae383a ("pinctrl: mediatek: support rsel feature") add SoC specify 'pull_type' attribute for bias configuration. This patch add pull_type attribute to pinctrl-mt7986.c, and make bias_set_combo and bias_get_combo available to mediatek MT7986 SoC. Signed-off-by: Sam Shih Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- v2: - fix odd numbers in comments --- drivers/pinctrl/mediatek/pinctrl-mt7986.c | 56 +++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7986.c b/drivers/pinctrl/mediatek/pinctrl-mt7986.c index d13c59510468..db3497d6787a 100644 --- a/drivers/pinctrl/mediatek/pinctrl-mt7986.c +++ b/drivers/pinctrl/mediatek/pinctrl-mt7986.c @@ -407,6 +407,60 @@ static const struct mtk_pin_field_calc mt7986_pin_r1_range[] = { PIN_FIELD_BASE(66, 68, IOCFG_LB_BASE, 0x60, 0x10, 2, 1), }; +static const unsigned int mt7986_pull_type[] = { + MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ + MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ + MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ + MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PUPD_R1R0_TYPE,/*7*/ + MTK_PULL_PUPD_R1R0_TYPE,/*8*/ MTK_PULL_PUPD_R1R0_TYPE,/*9*/ + MTK_PULL_PUPD_R1R0_TYPE,/*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ + MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PUPD_R1R0_TYPE,/*13*/ + MTK_PULL_PUPD_R1R0_TYPE,/*14*/ MTK_PULL_PUPD_R1R0_TYPE,/*15*/ + MTK_PULL_PUPD_R1R0_TYPE,/*16*/ MTK_PULL_PUPD_R1R0_TYPE,/*17*/ + MTK_PULL_PUPD_R1R0_TYPE,/*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ + MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ + MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ + MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ + MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ + MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ + MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ + MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ + MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ + MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ + MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ + MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ + MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ + MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ + MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ + MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ + MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ + MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ + MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ + MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ + MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ + MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ + MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PUPD_R1R0_TYPE,/*63*/ + MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ + MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ + MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PU_PD_TYPE,/*69*/ + MTK_PULL_PU_PD_TYPE,/*70*/ MTK_PULL_PU_PD_TYPE,/*71*/ + MTK_PULL_PU_PD_TYPE,/*72*/ MTK_PULL_PU_PD_TYPE,/*73*/ + MTK_PULL_PU_PD_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE,/*75*/ + MTK_PULL_PU_PD_TYPE,/*76*/ MTK_PULL_PU_PD_TYPE,/*77*/ + MTK_PULL_PU_PD_TYPE,/*78*/ MTK_PULL_PU_PD_TYPE,/*79*/ + MTK_PULL_PU_PD_TYPE,/*80*/ MTK_PULL_PU_PD_TYPE,/*81*/ + MTK_PULL_PU_PD_TYPE,/*82*/ MTK_PULL_PU_PD_TYPE,/*83*/ + MTK_PULL_PU_PD_TYPE,/*84*/ MTK_PULL_PU_PD_TYPE,/*85*/ + MTK_PULL_PU_PD_TYPE,/*86*/ MTK_PULL_PU_PD_TYPE,/*87*/ + MTK_PULL_PU_PD_TYPE,/*88*/ MTK_PULL_PU_PD_TYPE,/*89*/ + MTK_PULL_PU_PD_TYPE,/*90*/ MTK_PULL_PU_PD_TYPE,/*91*/ + MTK_PULL_PU_PD_TYPE,/*92*/ MTK_PULL_PU_PD_TYPE,/*93*/ + MTK_PULL_PU_PD_TYPE,/*94*/ MTK_PULL_PU_PD_TYPE,/*95*/ + MTK_PULL_PU_PD_TYPE,/*96*/ MTK_PULL_PU_PD_TYPE,/*97*/ + MTK_PULL_PU_PD_TYPE,/*98*/ MTK_PULL_PU_PD_TYPE,/*99*/ + MTK_PULL_PU_PD_TYPE,/*100*/ +}; + static const struct mtk_pin_reg_calc mt7986_reg_cals[] = { [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7986_pin_mode_range), [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7986_pin_dir_range), @@ -866,6 +920,7 @@ static struct mtk_pin_soc mt7986a_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1, @@ -887,6 +942,7 @@ static struct mtk_pin_soc mt7986b_data = { .ies_present = false, .base_names = mt7986_pinctrl_register_base_names, .nbase_names = ARRAY_SIZE(mt7986_pinctrl_register_base_names), + .pull_type = mt7986_pull_type, .bias_set_combo = mtk_pinconf_bias_set_combo, .bias_get_combo = mtk_pinconf_bias_get_combo, .drive_set = mtk_pinconf_drive_set_rev1,