From patchwork Fri Oct 6 09:40:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 149163 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:403:3b70:6f57 with SMTP id x8csp198651vqo; Fri, 6 Oct 2023 02:41:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpL+McUSuNp8zYYFSSbehFHpAdksc2vVxyyAMMb/sWvZ38NWK9tZjqxaKxsOZxYix1px0Y X-Received: by 2002:aa7:88c2:0:b0:68e:36bc:194a with SMTP id k2-20020aa788c2000000b0068e36bc194amr9614107pff.15.1696585278084; Fri, 06 Oct 2023 02:41:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696585278; cv=none; d=google.com; s=arc-20160816; b=D+AB/yhBM3ldVfsjG40A9sVs0+svzMveFR5j/CsrkyC3RyIN3BCHSQxMKOOoo2XCNu N2d1+TI1ngVnimBLwuJfRMCXm8EobvMdv3AGtZ6u4dMkmbI8zdpA/NKcrqDIYMkRq/Ls e23slmFWyQMZSCkaeh5NdQcVswoelaWvc4/kQY5X2qyfUn0LjDB5Fp8dxfFgI4itcIC4 vFmc2MnN8JD0urDDK5tWqS4SU+bgHp2TCHI01t925GEDYsbm18OACmBpK0tSrTjN75qD A/brpJUbCF4lw8bEDMOZjonhoAnfNl+AWGetiOP4ReCo71SGqeaAMl/B3ORth21Pl1AI Z13Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=fByIALREpuZEnX1N7Qd/juqzTHFvvIFwDWYVwVnb2cs=; fh=kdcNZYnkyZ+ZWfDO4WbeMSITNbqBTBm9j2eQc7KT0Q8=; b=K+YIYd6Tmre5fRunFAtGQxkNdVp+syAshv0tYmum84uXA0qfzYsynUUlwXwNcGFSay 3lhxpYaxtroVr4owm7t8J7cxVAEK4SifCozJj8HalOw5jP+ZgLIxK50Wl/5N+faU3iCU zODNADxH8FB+G7ERBRjXuNQAIt8pTFtHYQF/ZzLMaCfVu301JYfmmtM+rSHfUejIZJ7T th0B0xAbzF4wUvyAroJ3oDo75Ei8Tfy5rckCOePV1yvQN2yRslZmEWPOgPS8wrcZTsYz UJtojv4WDqFSIba0fq14mSi3BCNgWJUhdAFfK7M4Mrvqi2tnDm554mn6rzBiIO9MRX6O RvMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WI24N4DD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id m4-20020a633f04000000b00578a79e8f8bsi3097576pga.551.2023.10.06.02.41.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 02:41:18 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=WI24N4DD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 23A0F827030F; Fri, 6 Oct 2023 02:41:14 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231509AbjJFJkr (ORCPT + 18 others); Fri, 6 Oct 2023 05:40:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36716 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231373AbjJFJko (ORCPT ); Fri, 6 Oct 2023 05:40:44 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4205D9F; Fri, 6 Oct 2023 02:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696585241; x=1728121241; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=DBh81qjzYPJxlX4/+EjBm0h8lY3RyxT+qZS+GrWwc2I=; b=WI24N4DDSa7zCjIKhhjunaw8dIWImFXD45tbut2z8phPprSHN5GytB5b 8EYjXCubSY6B3E8H7jZjKKlGzdP+xY2+ht2xJZGKSFbgT93A/sHDJ2oGu BbSajsoFnkFE1h3Clj8mCzduqUobRWw6VaxdJb8z64ms9p7uA5c2rfNEZ sJ8BMDGguXRHcE80T29EVOnnH4dbsxrYaKdXV+425dNvr8K7/MEsGDunq EiKsfM4TG1QAR9GInXowJSZdsTbMSSw5M0aRxGR75GqMsEqRe9DmEhvvM ATfti2IYBzFH85swExlM0UEjd+HW7P+gNpoBA5wgeE4bzG8l6+KWSCGgL w==; X-IronPort-AV: E=McAfee;i="6600,9927,10854"; a="381000761" X-IronPort-AV: E=Sophos;i="6.03,203,1694761200"; d="scan'208";a="381000761" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 02:40:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10854"; a="999273973" X-IronPort-AV: E=Sophos;i="6.03,203,1694761200"; d="scan'208";a="999273973" Received: from black.fi.intel.com ([10.237.72.28]) by fmsmga006.fm.intel.com with ESMTP; 06 Oct 2023 02:40:38 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id A982E574; Fri, 6 Oct 2023 12:40:37 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij , Raag Jadav Subject: [PATCH v1 1/2] pinctrl: cherryview: Avoid duplicated I/O Date: Fri, 6 Oct 2023 12:40:32 +0300 Message-Id: <20231006094033.3082468-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.40.0.1.gaa8946217a0b MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Fri, 06 Oct 2023 02:41:14 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778998604566105092 X-GMAIL-MSGID: 1778998604566105092 In some cases we already read the value from the register followed by a reading of it again for other purposes, but the both reads are under the lock and bits we are insterested in are not going to change (they are not volatile from HW perspective). Hence, no need to read the same registeer twice. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index f047f7bf4afb..9b9f18f50c1d 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -612,9 +612,14 @@ static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned i } /* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ +static bool chv_pad_is_locked(u32 ctrl1) +{ + return ctrl1 & CHV_PADCTRL1_CFGLOCK; +} + static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) { - return chv_readl(pctrl, offset, CHV_PADCTRL1) & CHV_PADCTRL1_CFGLOCK; + return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1)); } static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, @@ -623,13 +628,11 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); unsigned long flags; u32 ctrl0, ctrl1; - bool locked; raw_spin_lock_irqsave(&chv_lock, flags); ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); - locked = chv_pad_locked(pctrl, offset); raw_spin_unlock_irqrestore(&chv_lock, flags); @@ -646,7 +649,7 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); - if (locked) + if (chv_pad_is_locked(ctrl1)) seq_puts(s, " [LOCKED]"); } From patchwork Fri Oct 6 09:40:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Shevchenko X-Patchwork-Id: 149164 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:a888:0:b0:403:3b70:6f57 with SMTP id x8csp198760vqo; Fri, 6 Oct 2023 02:41:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGVKsTT/B78ZOsWBrnr3veUq57ayX+P9RygsVKzD98lwNOZ8Tm9tBlZ06o4xxwN3EbAs9j8 X-Received: by 2002:a05:6a00:124f:b0:68a:3b39:a486 with SMTP id u15-20020a056a00124f00b0068a3b39a486mr7919616pfi.24.1696585295118; Fri, 06 Oct 2023 02:41:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696585295; cv=none; d=google.com; s=arc-20160816; b=i8I3LiJCOW8CUWpF3kv9nAT3+h08daemR3/Lx2ID4ZtgT00VbvhwBBQlYM/QlXjJyT BVi7WZ+OAsshBU1nYR3Kq9UwumF9GXHl+x5uWnm5ZUlExwrNhx6s5chXpDZRYPgPbKG3 m3wu9jdlAQqJhvcACUfEoCiCwG6vgd9+jLu1QX9WV1rU0s4J/s1fZFPDy4aeMwoBEwr8 aezPhhH8jsNu+AcgAzZ23e/yODvhCxK9YjRvXG1x9QTOWOsih0wlazjl+o74LP8IkGQV wQ1wFKyaRb5bFWbLh5dvlZFeCrfckgmrkRlMVwaBciculL8FtF0WNpqLqB99vcKBpxvo UGzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=HlBTlCv2aS78raV5vf3bL/RnSAMqA3dlpD3L54iU6KQ=; fh=kdcNZYnkyZ+ZWfDO4WbeMSITNbqBTBm9j2eQc7KT0Q8=; b=JXxUo4ag487AqzFKlnYy8J3mvCoErUvI8uOPUVUieJ4ReheKDRuBIdcorv7LPD63uB Xl3CyHrgVanvDAxDGOsoILApljmKEHC83Ui90/xE9MGNdVHaPl+w/50yom0q4Hs/W3dG sGOA+08aVJf5njSlviD7PbjLDGQgLmphWJQHO0bx6u+6fWyZBNoTUB4pVPcozPfhgoQi gvGIRAqFgcUNS2is/G+tUfAziV2HO262c5eedQ5E88AhCC7H0pm2ypxQVOVvnQP97+ew zBKMaSFOWJIGlvdPcpc+U3QjRX50ye99bsFxmTpEzI0Wwv0pAk7svUekc7WEfX4f2sqm eviw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=H0j0BqAP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id u21-20020a056a00099500b0068a68054661si1172780pfg.71.2023.10.06.02.41.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Oct 2023 02:41:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=H0j0BqAP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id E37698099270; Fri, 6 Oct 2023 02:41:31 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231446AbjJFJky (ORCPT + 18 others); Fri, 6 Oct 2023 05:40:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36730 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231443AbjJFJkp (ORCPT ); Fri, 6 Oct 2023 05:40:45 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0332DE4; Fri, 6 Oct 2023 02:40:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696585243; x=1728121243; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E5jCYljZFG9TXhPWBougop/emuTH6QaDm8PEpiHK0Sk=; b=H0j0BqAPcyyBuThH2uC81BoWZZXdzp1G2OlFfjDU0r5NxF599g1Ww5ej LGrVUqrgJiwlfs2llTxdsZL8CxQT6Y78dkhKLQusDnXrTKYzZG+BPxtay V+1eNhRSLRk9OGwA6IXkoWYdGQsd86/d4lkS6GnwOxNxFomhGwkSCWxsp arg61iiyBUtupCMvmjfxFigU1Vi+WIii7O9UV11mDXW9fMdFWMDkTy/Nl 4KAJlDRJ3QjhYbcTQVHOsZGnVzBh3N9d4yrZ4a/o0ZIecbut2Das88rx4 O6l2NtlJaLEhRRZgWz59hsGYszl57E8m91byQeede89NJgTJXVpTnZhQ2 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10854"; a="387597897" X-IronPort-AV: E=Sophos;i="6.03,203,1694761200"; d="scan'208";a="387597897" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2023 02:40:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10854"; a="925914578" X-IronPort-AV: E=Sophos;i="6.03,203,1694761200"; d="scan'208";a="925914578" Received: from black.fi.intel.com ([10.237.72.28]) by orsmga005.jf.intel.com with ESMTP; 06 Oct 2023 02:40:40 -0700 Received: by black.fi.intel.com (Postfix, from userid 1003) id 426675C2; Fri, 6 Oct 2023 12:40:39 +0300 (EEST) From: Andy Shevchenko To: Andy Shevchenko , linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Mika Westerberg , Andy Shevchenko , Linus Walleij , Raag Jadav Subject: [PATCH v1 2/2] pinctrl: cherryview: Simplify code with cleanup helpers Date: Fri, 6 Oct 2023 12:40:33 +0300 Message-Id: <20231006094033.3082468-2-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.40.0.1.gaa8946217a0b In-Reply-To: <20231006094033.3082468-1-andriy.shevchenko@linux.intel.com> References: <20231006094033.3082468-1-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 06 Oct 2023 02:41:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778998622228641196 X-GMAIL-MSGID: 1778998622228641196 Use macros defined in linux/cleanup.h to automate resource lifetime control in the driver. Signed-off-by: Andy Shevchenko Acked-by: Mika Westerberg --- drivers/pinctrl/intel/pinctrl-cherryview.c | 137 +++++++-------------- 1 file changed, 47 insertions(+), 90 deletions(-) diff --git a/drivers/pinctrl/intel/pinctrl-cherryview.c b/drivers/pinctrl/intel/pinctrl-cherryview.c index 9b9f18f50c1d..2ffeccc83ccd 100644 --- a/drivers/pinctrl/intel/pinctrl-cherryview.c +++ b/drivers/pinctrl/intel/pinctrl-cherryview.c @@ -12,6 +12,7 @@ #include #include +#include #include #include #include @@ -626,15 +627,12 @@ static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, unsigned int offset) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; u32 ctrl0, ctrl1; - raw_spin_lock_irqsave(&chv_lock, flags); - - ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); - ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); - - raw_spin_unlock_irqrestore(&chv_lock, flags); + scoped_guard(raw_spinlock_irqsave, &chv_lock) { + ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); + ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); + } if (ctrl0 & CHV_PADCTRL0_GPIOEN) { seq_puts(s, "GPIO "); @@ -666,17 +664,15 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); struct device *dev = pctrl->dev; const struct intel_pingroup *grp; - unsigned long flags; int i; grp = &pctrl->soc->groups[group]; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); /* Check first that the pad is not locked */ for (i = 0; i < grp->grp.npins; i++) { if (chv_pad_locked(pctrl, grp->grp.pins[i])) { - raw_spin_unlock_irqrestore(&chv_lock, flags); dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]); return -EBUSY; } @@ -716,8 +712,6 @@ static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, invert_oe ? "" : "not "); } - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; } @@ -748,16 +742,14 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, unsigned int offset) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; u32 value; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); if (chv_pad_locked(pctrl, offset)) { value = chv_readl(pctrl, offset, CHV_PADCTRL0); if (!(value & CHV_PADCTRL0_GPIOEN)) { /* Locked so cannot enable */ - raw_spin_unlock_irqrestore(&chv_lock, flags); return -EBUSY; } } else { @@ -792,8 +784,6 @@ static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, chv_writel(pctrl, offset, CHV_PADCTRL0, value); } - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; } @@ -802,14 +792,13 @@ static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, unsigned int offset) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); - if (!chv_pad_locked(pctrl, offset)) - chv_gpio_clear_triggering(pctrl, offset); + if (chv_pad_locked(pctrl, offset)) + return; - raw_spin_unlock_irqrestore(&chv_lock, flags); + chv_gpio_clear_triggering(pctrl, offset); } static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, @@ -817,10 +806,9 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, unsigned int offset, bool input) { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); - unsigned long flags; u32 ctrl0; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; if (input) @@ -829,8 +817,6 @@ static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; } @@ -849,15 +835,14 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, { struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); enum pin_config_param param = pinconf_to_config_param(*config); - unsigned long flags; u32 ctrl0, ctrl1; u16 arg = 0; u32 term; - raw_spin_lock_irqsave(&chv_lock, flags); - ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); - ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); - raw_spin_unlock_irqrestore(&chv_lock, flags); + scoped_guard(raw_spinlock_irqsave, &chv_lock) { + ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); + ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); + } term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; @@ -932,10 +917,10 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, enum pin_config_param param, u32 arg) { - unsigned long flags; u32 ctrl0, pull; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); + ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); switch (param) { @@ -958,7 +943,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; break; default: - raw_spin_unlock_irqrestore(&chv_lock, flags); return -EINVAL; } @@ -976,7 +960,6 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; break; default: - raw_spin_unlock_irqrestore(&chv_lock, flags); return -EINVAL; } @@ -984,12 +967,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, break; default: - raw_spin_unlock_irqrestore(&chv_lock, flags); return -EINVAL; } chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); - raw_spin_unlock_irqrestore(&chv_lock, flags); return 0; } @@ -997,10 +978,10 @@ static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, bool enable) { - unsigned long flags; u32 ctrl1; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); + ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); if (enable) @@ -1009,7 +990,6 @@ static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, ctrl1 &= ~CHV_PADCTRL1_ODEN; chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); - raw_spin_unlock_irqrestore(&chv_lock, flags); return 0; } @@ -1119,28 +1099,26 @@ static struct pinctrl_desc chv_pinctrl_desc = { static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); - unsigned long flags; u32 ctrl0, cfg; - raw_spin_lock_irqsave(&chv_lock, flags); - ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); - raw_spin_unlock_irqrestore(&chv_lock, flags); + scoped_guard(raw_spinlock_irqsave, &chv_lock) + ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); + return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); } static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); - unsigned long flags; u32 ctrl0; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); @@ -1150,19 +1128,15 @@ static void chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); - - raw_spin_unlock_irqrestore(&chv_lock, flags); } static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct intel_pinctrl *pctrl = gpiochip_get_data(chip); u32 ctrl0, direction; - unsigned long flags; - raw_spin_lock_irqsave(&chv_lock, flags); - ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); - raw_spin_unlock_irqrestore(&chv_lock, flags); + scoped_guard(raw_spinlock_irqsave, &chv_lock) + ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; @@ -1203,23 +1177,20 @@ static void chv_gpio_irq_ack(struct irq_data *d) irq_hw_number_t hwirq = irqd_to_hwirq(d); u32 intr_line; - raw_spin_lock(&chv_lock); + guard(raw_spinlock)(&chv_lock); intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intr_line &= CHV_PADCTRL0_INTSEL_MASK; intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); - - raw_spin_unlock(&chv_lock); } static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) { struct intel_pinctrl *pctrl = gpiochip_get_data(gc); u32 value, intr_line; - unsigned long flags; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intr_line &= CHV_PADCTRL0_INTSEL_MASK; @@ -1231,8 +1202,6 @@ static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq else value |= BIT(intr_line); chv_pctrl_writel(pctrl, CHV_INTMASK, value); - - raw_spin_unlock_irqrestore(&chv_lock, flags); } static void chv_gpio_irq_mask(struct irq_data *d) @@ -1257,7 +1226,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) { /* * Check if the interrupt has been requested with 0 as triggering - * type. In that case it is assumed that the current values + * type. If not, bail out, ... + */ + if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) { + chv_gpio_irq_unmask(d); + return 0; + } + + /* + * ...otherwise it is assumed that the current values * programmed to the hardware are used (e.g BIOS configured * defaults). * @@ -1265,17 +1242,15 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) * read back the values from hardware now, set correct flow handler * and update mappings before the interrupt is being used. */ - if (irqd_get_trigger_type(d) == IRQ_TYPE_NONE) { + scoped_guard(raw_spinlock_irqsave, &chv_lock) { struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); struct device *dev = pctrl->dev; struct intel_community_context *cctx = &pctrl->context.communities[0]; irq_hw_number_t hwirq = irqd_to_hwirq(d); irq_flow_handler_t handler; - unsigned long flags; u32 intsel, value; - raw_spin_lock_irqsave(&chv_lock, flags); intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); intsel &= CHV_PADCTRL0_INTSEL_MASK; intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; @@ -1292,7 +1267,6 @@ static unsigned chv_gpio_irq_startup(struct irq_data *d) intsel, hwirq); cctx->intr_lines[intsel] = hwirq; } - raw_spin_unlock_irqrestore(&chv_lock, flags); } chv_gpio_irq_unmask(d); @@ -1357,17 +1331,14 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct intel_pinctrl *pctrl = gpiochip_get_data(gc); irq_hw_number_t hwirq = irqd_to_hwirq(d); - unsigned long flags; u32 value; int ret; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); ret = chv_gpio_set_intr_line(pctrl, hwirq); - if (ret) { - raw_spin_unlock_irqrestore(&chv_lock, flags); + if (ret) return ret; - } /* * Pins which can be used as shared interrupt are configured in @@ -1408,8 +1379,6 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) else if (type & IRQ_TYPE_LEVEL_MASK) irq_set_handler_locked(d, handle_level_irq); - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; } @@ -1433,14 +1402,12 @@ static void chv_gpio_irq_handler(struct irq_desc *desc) struct intel_community_context *cctx = &pctrl->context.communities[0]; struct irq_chip *chip = irq_desc_get_chip(desc); unsigned long pending; - unsigned long flags; u32 intr_line; chained_irq_enter(chip, desc); - raw_spin_lock_irqsave(&chv_lock, flags); - pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); - raw_spin_unlock_irqrestore(&chv_lock, flags); + scoped_guard(raw_spinlock_irqsave, &chv_lock) + pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); for_each_set_bit(intr_line, &pending, community->nirqs) { unsigned int offset; @@ -1629,21 +1596,17 @@ static acpi_status chv_pinctrl_mmio_access_handler(u32 function, void *handler_context, void *region_context) { struct intel_pinctrl *pctrl = region_context; - unsigned long flags; - acpi_status ret = AE_OK; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); if (function == ACPI_WRITE) chv_pctrl_writel(pctrl, address, *value); else if (function == ACPI_READ) *value = chv_pctrl_readl(pctrl, address); else - ret = AE_BAD_PARAMETER; + return AE_BAD_PARAMETER; - raw_spin_unlock_irqrestore(&chv_lock, flags); - - return ret; + return AE_OK; } static int chv_pinctrl_probe(struct platform_device *pdev) @@ -1751,10 +1714,9 @@ static int chv_pinctrl_suspend_noirq(struct device *dev) { struct intel_pinctrl *pctrl = dev_get_drvdata(dev); struct intel_community_context *cctx = &pctrl->context.communities[0]; - unsigned long flags; int i; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); @@ -1772,8 +1734,6 @@ static int chv_pinctrl_suspend_noirq(struct device *dev) ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); } - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; } @@ -1781,10 +1741,9 @@ static int chv_pinctrl_resume_noirq(struct device *dev) { struct intel_pinctrl *pctrl = dev_get_drvdata(dev); struct intel_community_context *cctx = &pctrl->context.communities[0]; - unsigned long flags; int i; - raw_spin_lock_irqsave(&chv_lock, flags); + guard(raw_spinlock_irqsave)(&chv_lock); /* * Mask all interrupts before restoring per-pin configuration @@ -1826,8 +1785,6 @@ static int chv_pinctrl_resume_noirq(struct device *dev) chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); - raw_spin_unlock_irqrestore(&chv_lock, flags); - return 0; }