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Thu, 05 Oct 2023 09:50:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778935112740969374 X-GMAIL-MSGID: 1778935112740969374 The primary,secondary and sub-ordinate bus number registers are updated by Linux PCI core, so remove code which updates respective fields of type 1 header. Signed-off-by: Thippeswamy Havalige --- changes in v5: - None changes in v4: - None changes in v3: - Remove unnecessary period at end of subject line. - Updated commit message. changes in v2: - Code increasing ECAM Size value is added into a seperate patch. - Modified commit messages. changes in v1: - Modified commit messages. --- drivers/pci/controller/pcie-xilinx-nwl.c | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 176686bdb15c..d8a3a08be1d5 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -166,7 +166,6 @@ struct nwl_pcie { int irq_intx; int irq_misc; u32 ecam_value; - u8 last_busno; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -625,7 +624,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) { struct device *dev = pcie->dev; struct platform_device *pdev = to_platform_device(dev); - u32 breg_val, ecam_val, first_busno = 0; + u32 breg_val, ecam_val; int err; breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT; @@ -683,15 +682,6 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base), E_ECAM_BASE_HI); - /* Get bus range */ - ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL); - pcie->last_busno = (ecam_val & E_ECAM_SIZE_LOC) >> E_ECAM_SIZE_SHIFT; - /* Write primary, secondary and subordinate bus numbers */ - ecam_val = first_busno; - ecam_val |= (first_busno + 1) << 8; - ecam_val |= (pcie->last_busno << E_ECAM_SIZE_SHIFT); - writel(ecam_val, (pcie->ecam_base + PCI_PRIMARY_BUS)); - if (nwl_pcie_link_up(pcie)) dev_info(dev, "Link is UP\n"); else From patchwork Thu Oct 5 16:40:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 148937 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp436810vqb; Thu, 5 Oct 2023 10:01:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHc2JZXhPCu8cFdadk4qbwE781vIVqgfBEY1eqczsW770qtWEjfnXG0fAozNabhRZf1ZCKV X-Received: by 2002:a17:90a:d50:b0:277:298:deae with SMTP id 16-20020a17090a0d5000b002770298deaemr5481173pju.11.1696525298698; Thu, 05 Oct 2023 10:01:38 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696525298; cv=pass; d=google.com; s=arc-20160816; b=zrj688XXjGMNVq82kWR3JLEFvfvIv9N++uufswlrVzrIxkIx/Sys15hINkfKpYpJaN HZGUxMJPC1zMQ76KxJySAFD71IxqEaimlzAEst7PyoHaOmdrjCjXkxbOVVnZcWgpWw6M SHnwOIntn1dnnuOw5CXYVSnD1oUIQjPCdXB3Y2Mvq/gxSejOW2i7zaPJeu02bXrO5edZ Pk82cXDV5JDSUGwe4zVWVzW720ar/fVSknzH7bD/rjyrSKKeY9dVXUqkHs0KvJKL//oO A3dL6mph7xMDL0yXYqCP6NMrkqmxZ8ItQ8ivoiwt/LMuFFdE5KNztP1TlWY0SA1My7TH AU6g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=aljHyMWt8R/QLn5d6xJ+f8RBv6t6/Cj1hmwBAKY8Yjw=; fh=J+yYKBVYwP+tVuJGZcZnC9mCeB2cW9ItmP9p4Q4B1v0=; b=Q5e9bwiLM5hnF/NAMRprDu5ZUiseiEFIjbKYYCzvhamCn7R4TS1ZGFaZwo2dH7DLWb noWap7Hjoj81lSuzPkOE5o2F5552TFlObHO4Qrj4Vv93wd9thIXd0Ao1xYU3SYMyIPjf Ii3NV/hKJUHsGkl+QeFmTo4ikWjOPzEE/O2kxWA+hgsr+VSF5WA+V75qqeQMN4nBJS1W QkMqMrALCdL4hZ4MV8CfjVzjG0EUxZsEaBXilfu9k42X4XdZ5bRXMrIQg21N+mpjHzT7 MyWBZwnwCDSMs8szy++P3rpnxdF2G3PxC694p/IVmBPeUGS1xY/bYk8chWMDnkGchbUo Nf5g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=Y4gzniQB; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from groat.vger.email (groat.vger.email. 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Thu, 05 Oct 2023 10:01:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778935711167147657 X-GMAIL-MSGID: 1778935711167147657 Update ECAM size in example to discover up to 256 buses. Signed-off-by: Thippeswamy Havalige Acked-by: Rob Herring --- changes in v5: None changes in v4: None changes in v3: Remove period at end of subject line changes in v2: None. changes in v1: None. --- Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml index 897602559b37..426f90a47f35 100644 --- a/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/xlnx,nwl-pcie.yaml @@ -118,7 +118,7 @@ examples: compatible = "xlnx,nwl-pcie-2.11"; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, - <0x80 0x00000000 0x0 0x1000000>; + <0x80 0x00000000 0x0 0x10000000>; reg-names = "breg", "pcireg", "cfg"; ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>, <0x43000000 0x00000006 0x0 0x00000006 0x0 0x00000002 0x0>; From patchwork Thu Oct 5 16:40:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 148920 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp431272vqb; Thu, 5 Oct 2023 09:52:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7NFMZ9FtEibygojz5fIlIOPgJu8xzMyoN6Nd8spmFMHuIPbsN4eYbiDqKqOcqyBuje/8i X-Received: by 2002:a05:6a21:71c1:b0:161:2389:e34c with SMTP id ay1-20020a056a2171c100b001612389e34cmr5890818pzc.23.1696524729941; Thu, 05 Oct 2023 09:52:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696524729; cv=pass; d=google.com; s=arc-20160816; b=uRD1ExAHdg/dz+yTmrOP73+GioCGMuaOXk/ypuR14uDJRAs9ROCoAv608Mw6VgoOzh e5KUw4bqrin7JDMLdYdOri4h6fb+9yyK1Sx6BKhk+TsxC9LbvrrbaRX3ULwL+gbzeISd /g8Cxx+CIbnuq/sH09yQ7KIq9yaiHpIrA9Q2JT7Fh1f1CdGLMbQ2l6P6gi8830Lb3u3f /2wtwCxqAEO+Nrm5XYaOvvlbuzSWiaDAMjqCmaYNtebpT1RhN0SJZYm9b9UPbhYzuMGp HzJurwmLF9uvFhzERaUp+xD+u2QOsvb1p6/IJjbV9PK05uMwhR4cLGtH/rYxNKdabycb WMVA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=/ESYLK1Re4VerwS7kWjWSjaIYrADQbJMwrXP7iIWn9w=; fh=J+yYKBVYwP+tVuJGZcZnC9mCeB2cW9ItmP9p4Q4B1v0=; b=ot+6qiJ9ScbATHEMyST+VL4f3XWA71Nwt3hamdWUbzonEEnkgDcGxzaL/iDHgnOn2+ 2dJc2+Cse4kOPNVIG7X4ClRA4N1PLEoyZgsJMxzDJdvT1iWPZnQo9VG3uvvp0o3HfTjC xluKxTM7ETeBP9mkbkYMAgtD+82lzbBHreNpBPRQb5vB/iD7slHTyEHbqmytf1pK3Bte 09yI97Zg1ImbcoWerApYzWmwO7H6ZR1Q2Jn3AM0JAYjkElfQgPoL0zZCNPHLQt4GtFNb thyUzfCZlAkiuPL0N8YsVE4JlvvkeAXjv6v55mtqd85gxB6gHpaKWy8Sn8glQ0IfWDdJ lsSg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=qDt03ihS; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from howler.vger.email (howler.vger.email. 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Thu, 05 Oct 2023 09:50:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778935115320419164 X-GMAIL-MSGID: 1778935115320419164 Rename "NWL_ECAM_VALUE_DEFAULT" to a suitable macro name and remove redundant code Signed-off-by: Thippeswamy Havalige --- changes in v5: Remove period at end of subject line. --- drivers/pci/controller/pcie-xilinx-nwl.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index d8a3a08be1d5..8fe0e8a325b0 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_VALUE_DEFAULT 12 +#define NWL_ECAM_MAX_SIZE 12 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0) @@ -165,7 +165,6 @@ struct nwl_pcie { u32 ecam_size; int irq_intx; int irq_misc; - u32 ecam_value; struct nwl_msi msi; struct irq_domain *legacy_irq_domain; struct clk *clk; @@ -674,7 +673,7 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie) E_ECAM_CR_ENABLE, E_ECAM_CONTROL); nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) | - (pcie->ecam_value << E_ECAM_SIZE_SHIFT), + (NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT), E_ECAM_CONTROL); nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base), @@ -782,7 +781,6 @@ static int nwl_pcie_probe(struct platform_device *pdev) pcie = pci_host_bridge_priv(bridge); pcie->dev = dev; - pcie->ecam_value = NWL_ECAM_VALUE_DEFAULT; err = nwl_pcie_parse_dt(pcie, pdev); if (err) { From patchwork Thu Oct 5 16:40:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Havalige, Thippeswamy" X-Patchwork-Id: 148921 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp431606vqb; Thu, 5 Oct 2023 09:52:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGt21ImoLzFnHTrnOxfwBK+2VUNaTP+eJhiK0WsHXfvPkOmzUte8nTORMM/xI7Vy4Hf1v3v X-Received: by 2002:a05:6808:2382:b0:3a4:ccf:6a63 with SMTP id bp2-20020a056808238200b003a40ccf6a63mr6520497oib.55.1696524768490; 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Thu, 5 Oct 2023 11:42:07 -0500 Received: from SATLEXMB03.amd.com (10.181.40.144) by SATLEXMB08.amd.com (10.181.40.132) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 5 Oct 2023 09:42:06 -0700 Received: from xhdthippesw40.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Thu, 5 Oct 2023 11:42:03 -0500 From: Thippeswamy Havalige To: , , , CC: , , , , , , , , Thippeswamy Havalige Subject: [PATCH v5 RESEND 4/4] PCI: xilinx-nwl: Increase ECAM size to accommodate 256 buses Date: Thu, 5 Oct 2023 22:10:51 +0530 Message-ID: <20231005164051.984254-5-thippeswamy.havalige@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231005164051.984254-1-thippeswamy.havalige@amd.com> References: <20231005164051.984254-1-thippeswamy.havalige@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9D5:EE_|IA1PR12MB7566:EE_ X-MS-Office365-Filtering-Correlation-Id: 0c90cb71-aaed-4b09-56b7-08dbc5c203cf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Thu, 05 Oct 2023 09:52:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778935155542917535 X-GMAIL-MSGID: 1778935155542917535 Our controller is expecting ECAM size to be programmed by software. By programming "NWL_ECAM_VALUE_DEFAULT 12" controller can access up to 16MB ECAM region which is used to detect 16 buses, so by updating "NWL_ECAM_VALUE_DEFAULT" to 16 so that controller can access up to 256MB ECAM region to detect 256 buses. Signed-off-by: Thippeswamy Havalige --- changes in v5: None. --- drivers/pci/controller/pcie-xilinx-nwl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c index 8fe0e8a325b0..e307aceba5c9 100644 --- a/drivers/pci/controller/pcie-xilinx-nwl.c +++ b/drivers/pci/controller/pcie-xilinx-nwl.c @@ -126,7 +126,7 @@ #define E_ECAM_CR_ENABLE BIT(0) #define E_ECAM_SIZE_LOC GENMASK(20, 16) #define E_ECAM_SIZE_SHIFT 16 -#define NWL_ECAM_MAX_SIZE 12 +#define NWL_ECAM_MAX_SIZE 16 #define CFG_DMA_REG_BAR GENMASK(2, 0) #define CFG_PCIE_CACHE GENMASK(7, 0)