From patchwork Thu Oct 5 02:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Akashi X-Patchwork-Id: 148727 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp330942vqb; Thu, 5 Oct 2023 07:19:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH09LXjfgL1o+TIltkOmKBCodakmHlUDKWsfmumXbavbbNbBioOlPIzI864Wkk2sPQgnfdl X-Received: by 2002:a05:6358:999f:b0:140:f6ab:b11e with SMTP id j31-20020a056358999f00b00140f6abb11emr5585921rwb.28.1696515542519; Thu, 05 Oct 2023 07:19:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696515542; cv=none; d=google.com; s=arc-20160816; b=Ti2dczaICHg52El4fKLueb8XlxA5wyi8R0E14BgugUM29Bm0q/U9RuLSIC8cIp8IVJ p4/AzqvhJcBWH8fCGYUApFV/0z9bH+/UsKFQtwuPVrFN+hnjyH6HzmeIFtdyZmvClU8j A0E03hU7fTHvK/XfodiowshErQI5jJWTZhpfitcX/aSW0LsvTf58pGymwMYsM+lp5fzQ sUnlwd3zPTTGv2c4orJatmX+1s/f7mo0/+F9p8iN5kXIvSdk5yWNXeqDbY1ZsckQ2BSU YFwY4zPlV/Njlm4PdxEdOThcPOk6uS6rQUsWOjanp/gr8e2njC+wNY+Oco6kYKFCqr2Y RD9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=C71OcQAzBT261vJLaVS0ZLT3a6uuXRpHLmHkJwsnefw=; fh=5LIWo2D/PeZk6SC/rjjkha3vijtdzmZAJYKHEnFRQDY=; b=BxHG5ivmgNaXzhticjNVt0EV1b8YphG2mEvqyprix6vxEQNV0rM8ypkTeAacUsRY1B arf4AdefYULDxuq6QtUnlb5Ro1iD6G6VAgHjJrr94OHV7cIv+qX9ZilsByi+GbWlY8fX 36IDYT1bxPIxl/m1AbxpuzQbIlVWW1bDSuiqyQ6K+1JThrcuxHUx72oSEtwaG2DIGPJF Lrpy5HXsqv7BclHG4Jo/qPLa9Pl8cTzV4a06SbvfDVByaZ0hM0Ev5U/vj7xm2MPvbsyz IoCjeacfDEJ2ZIwv/Pp7LdS7lb/TAKXgUu0ZIH34+N7jx4SxSyA6oNJ42ZJoba1/0/JO C5NQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=P8CD0Huk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from howler.vger.email (howler.vger.email. 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:22 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 1/5] pinctrl: define PIN_CONFIG_INPUT Date: Thu, 5 Oct 2023 11:58:39 +0900 Message-Id: <20231005025843.508689-2-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 05 Oct 2023 07:18:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778925481297614540 X-GMAIL-MSGID: 1778925481297614540 This configuration is intended to be used to allow a pin controller based GPIO driver to obtain a value at a gpio input pin. Signed-off-by: AKASHI Takahiro Reviewed-by: Linus Walleij --- RFC v2 (Oct 5, 2023) * improve a comment against @PIN_CONFIG_INPUT as per Linus RFC(Oct 2, 2023) --- include/linux/pinctrl/pinconf-generic.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/linux/pinctrl/pinconf-generic.h b/include/linux/pinctrl/pinconf-generic.h index d74b7a4ea154..da0d80aa532d 100644 --- a/include/linux/pinctrl/pinconf-generic.h +++ b/include/linux/pinctrl/pinconf-generic.h @@ -67,6 +67,10 @@ struct pinctrl_map; * passed as argument. The argument is in mA. * @PIN_CONFIG_DRIVE_STRENGTH_UA: the pin will sink or source at most the current * passed as argument. The argument is in uA. + * @PIN_CONFIG_INPUT: This will obtain a value on an input pin. To put a line + * into input mode, @PIN_CONFIG_INPUT_ENABLE must be used. Otherwise, + * an error will be returned. The returned argument is 1 for logic high + * and 0 for logic low. * @PIN_CONFIG_INPUT_DEBOUNCE: this will configure the pin to debounce mode, * which means it will wait for signals to settle when reading inputs. The * argument gives the debounce time in usecs. Setting the @@ -128,6 +132,7 @@ enum pin_config_param { PIN_CONFIG_DRIVE_PUSH_PULL, PIN_CONFIG_DRIVE_STRENGTH, PIN_CONFIG_DRIVE_STRENGTH_UA, + PIN_CONFIG_INPUT, PIN_CONFIG_INPUT_DEBOUNCE, PIN_CONFIG_INPUT_ENABLE, PIN_CONFIG_INPUT_SCHMITT, From patchwork Thu Oct 5 02:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Akashi X-Patchwork-Id: 148711 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp323846vqb; Thu, 5 Oct 2023 07:09:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFV5vbQ4QjuivLwPVRMpfo0wWbF0s1QzNBdz+p996GEI+0BqrVZL2S/z/578guuiDL/wct1 X-Received: by 2002:a05:6a00:15c6:b0:68e:45df:4648 with SMTP id o6-20020a056a0015c600b0068e45df4648mr5854162pfu.23.1696514962806; Thu, 05 Oct 2023 07:09:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696514962; cv=none; d=google.com; s=arc-20160816; b=FMl6XGh1lRnDCFaA1JALtskKmDO9OnsxpGsw1E43mrtr8xIk78iL63FmtGI6D2Zf/9 BqiYyiM+ZelkeFRUop6JM7oFXZnhaBdvUayToe4HyqZzNVLCkxByHdtCpZrv5bNNlMVa yPEoXOFVAKT4mGNoIlJW5RgC7Ei1zSgQvZNj3iCY0lvQdzUkynHwsn2Moxz3H8+N8dVe y4UqfvmbtwLN0xLsFkuNq5tCtjahgC251TsdT2w77jov8wWh/9giYezpzHt1b4mlZUl9 h1hlivSvD9oDGLvjrPI+hyLYxuQCYjehuS6pyFLc326o+Q/9cndOGZyDUPxRz7kgQ9Ru FQqw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TSbRKsYb8q8GitmB/U1RL+XJyPpceXOp7I/10Xz1sb8=; fh=DNj3x1LU/bB30oLF4CwdyP4P5x5olvFzEaoaVXEWcUA=; b=N4kmapnYzOkWyogQ8hhx4tc/lhYHKpQ15AA8MdQgtXE6JeocYWUMhIweHxjSZIIr8T WTCYiOYcdWXNeFPeacV+XWfG2jxhwIZ3xriBuOzxjRt7++2qqhbcmrTaVshH7Fgbs/eB qrNuWIU+HAOH8x6jx9kCPjtfeZe7fQKeZvOwjrbaCsLw0K6N0gAm0RU1okw8nmylG2+G eL2ilRjkf2OjhhncnhAIFMqtjPkWzESn8UmVZzfHA070BgKAkl6A8Z2nyqdBKjCqIJhU rPhgEIJ1dN/k0tw39fxwgB8R6++iQt4ykUf1g2R4iXAv1m7Io2rAQuly+mLZkwZrVm6+ zWog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XueE8YDI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from howler.vger.email (howler.vger.email. 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:26 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro , kernel test robot Subject: [RFC v2 2/5] pinctrl: always export pin_config_get_for_pin() Date: Thu, 5 Oct 2023 11:58:40 +0900 Message-Id: <20231005025843.508689-3-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 05 Oct 2023 07:09:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778924873476926628 X-GMAIL-MSGID: 1778924873476926628 This function will be used to implement a new pinctrl_gpio_get_config() outside pinconf.c in a succeeding commit. So make it always visible to avoid a kernel test bot error. Signed-off-by: AKASHI Takahiro Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202310021320.gYfm1nLQ-lkp@intel.com/ Reviewed-by: Linus Walleij --- RFC v2 (Oct 5, 2023) * new --- drivers/pinctrl/pinconf.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinconf.h b/drivers/pinctrl/pinconf.h index 694bfc9961fa..068089b199e4 100644 --- a/drivers/pinctrl/pinconf.h +++ b/drivers/pinctrl/pinconf.h @@ -31,13 +31,13 @@ int pinconf_apply_setting(const struct pinctrl_setting *setting); int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, unsigned long *configs, size_t nconfigs); +int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, + unsigned long *config); /* * You will only be interested in these if you're using PINCONF * so don't supply any stubs for these. */ -int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin, - unsigned long *config); int pin_config_group_get(const char *dev_name, const char *pin_group, unsigned long *config); @@ -74,6 +74,12 @@ static inline int pinconf_set_config(struct pinctrl_dev *pctldev, unsigned pin, return -ENOTSUPP; } +static inline int pin_config_get_for_pin(struct pinctrl_dev *pctldev, + unsigned pin, unsigned long *config) +{ + return -ENOTSUPP; +} + #endif #if defined(CONFIG_PINCONF) && defined(CONFIG_DEBUG_FS) From patchwork Thu Oct 5 02:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Akashi X-Patchwork-Id: 148924 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp434037vqb; Thu, 5 Oct 2023 09:57:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxiV/STq7LYs/XZXUP9XEmRqoA/zCxWL5mmR8CVjtEi7mta90hH4HEj0d3k099zNth00yZ X-Received: by 2002:a05:6a20:158e:b0:16a:bcde:397d with SMTP id h14-20020a056a20158e00b0016abcde397dmr1582423pzj.22.1696525064804; Thu, 05 Oct 2023 09:57:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696525064; cv=none; d=google.com; s=arc-20160816; b=0iHQKjRhfMShr9t4oHJ7YapdQFHgiTbgXHZXS93hEODs2UW7Ssr6k9XNp9vGZ+BPE+ j661cWQehXsBxAKJeTCuujgTl6Vg5WBk2U4XRG1UeBJ57xwZ5Pvf/C1OFRDqdUGWqo7+ OaldGWP0dunIQsNbxig4amN9IeBxACND01TEx/nKEQYWT9IPOCYag9b7/+log1kMi3ZN ttdq1lk4p2cJM/OkbVQPMJ2y6I28XkQo2HdfFxgDf2muh12WYWtyyUvQCCLFKBV4SGK1 dA9yGPZS0QvqFqPznlWxqAmyRWq6G3kJtjTfaw+oNpvMG3KQE/Sntco0wlKSoo8ws8zj PbNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=10JswCDtKjfsgUgjTt05ZkVWjMO4ZebDQWE8d7lo6tc=; fh=5LIWo2D/PeZk6SC/rjjkha3vijtdzmZAJYKHEnFRQDY=; b=OUldgUZI9i5c605eK7nOO6s7JwHoJT+pfqaqQYxZkX8DD0BQMcHf2JEqqz9CxhupHQ /3IX6jDtBrSHWoTMuhMoA9vqxZyM2dkYDaDe7pVafKZpwVhySRGp2Mbpd+LMAqKgBTpY WI3S8fDe6LP7WYLT787z+75irOpSudi6O2whTvXCpxG4ZkyR4BHg/hhGd7+HSv6ZCl01 KWMLwNTYu//KZO8qYq0mPBOmqFjr0rKqDZ9EEw4D7mapuSPVSXdSiT7VeV41FFa5slLv t0UA7XeIxb38gMkkmNwiy1BywaJeWm4IFuqsqSoc+iUQ+3W7VrzKV7O+ayR0tbxtmWaH I4jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VKUQsTLh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from snail.vger.email (snail.vger.email. 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:30 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 3/5] pinctrl: add pinctrl_gpio_get_config() Date: Thu, 5 Oct 2023 11:58:41 +0900 Message-Id: <20231005025843.508689-4-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 05 Oct 2023 09:57:43 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778935466248731944 X-GMAIL-MSGID: 1778935466248731944 This is a counterpart of pinctrl_gpio_set_config() which will be used, at least initially, to implement gpio_get interface in pin controller based generic gpio driver. Signed-off-by: AKASHI Takahiro Reviewed-by: Linus Walleij --- RFC (Oct 2, 2023) --- drivers/pinctrl/core.c | 19 +++++++++++++++++++ include/linux/pinctrl/consumer.h | 8 ++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index e9dc9638120a..2f9c2efdfe0e 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -926,6 +926,25 @@ int pinctrl_gpio_set_config(unsigned gpio, unsigned long config) } EXPORT_SYMBOL_GPL(pinctrl_gpio_set_config); +int pinctrl_gpio_get_config(unsigned int gpio, unsigned long *config) +{ + struct pinctrl_gpio_range *range; + struct pinctrl_dev *pctldev; + int ret, pin; + + ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range); + if (ret) + return ret; + + mutex_lock(&pctldev->mutex); + pin = gpio_to_pin(range, gpio); + ret = pin_config_get_for_pin(pctldev, pin, config); + mutex_unlock(&pctldev->mutex); + + return ret; +} +EXPORT_SYMBOL_GPL(pinctrl_gpio_get_config); + static struct pinctrl_state *find_state(struct pinctrl *p, const char *name) { diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consumer.h index 4729d54e8995..852fac97a79b 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -31,6 +31,8 @@ extern void pinctrl_gpio_free(unsigned gpio); extern int pinctrl_gpio_direction_input(unsigned gpio); extern int pinctrl_gpio_direction_output(unsigned gpio); extern int pinctrl_gpio_set_config(unsigned gpio, unsigned long config); +extern int pinctrl_gpio_get_config(unsigned int gpio, + unsigned long *config); extern struct pinctrl * __must_check pinctrl_get(struct device *dev); extern void pinctrl_put(struct pinctrl *p); @@ -92,6 +94,12 @@ static inline int pinctrl_gpio_set_config(unsigned gpio, unsigned long config) return 0; } +static inline int pinctrl_gpio_get_config(unsigned int gpio, + unsigned long *config) +{ + return 0; +} + static inline struct pinctrl * __must_check pinctrl_get(struct device *dev) { return NULL; From patchwork Thu Oct 5 02:58:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Akashi X-Patchwork-Id: 148731 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp332258vqb; Thu, 5 Oct 2023 07:21:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqfRCB5i+b0F9D/898j8Co+GsqOXGKaEizLVx+tmTzrZvSCvD5GPnK3+kME6suvBzNRobg X-Received: by 2002:a17:902:dc86:b0:1c3:21ae:7a4a with SMTP id n6-20020a170902dc8600b001c321ae7a4amr5194217pld.38.1696515659968; Thu, 05 Oct 2023 07:20:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696515659; cv=none; d=google.com; s=arc-20160816; b=qcWvYS0vEjgpeBjfS5PWWzee0hbWDRJNFPVR3hbb80ELFUwbW9WFLHzcBPKIFg6dGy tIOtjwNGV2RX70d7palZKvv00e/T5j/9+ZA/SdwddgzDYLD9rFDArwI3F/QkL03LqLtM jcM11zXVzhuxofG1UP4aWwrFXlS/nR1fLaITeyZbM7BOfBvw7upmDVwqLSj0Pq5G1/TV VSAikGvAjKOdHCmo4jOTiUjA6ck2TiFeT/sQOMplH+jOPf1CLlK/kyz7fKMHES//1Ura q80Mc7ZnpKCD6l3qRGyD+edOCFnCDqtUJS3eF3Vwh7hnARNC1jwaEIWasuP+N+yBA5xu xzeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o8UbiRXeWQbu5CCxehWCFCKEGYBPmnXfSamsU23VNAk=; fh=5LIWo2D/PeZk6SC/rjjkha3vijtdzmZAJYKHEnFRQDY=; b=MVrQrEquYCvrS8o1FQLz4c6wNZ5/T7lT3vDBNIypTZAWroBWqwwdGVQcST7gx1iPaS K5mn5fX6w6oxEuh6CFwwT9P2g7RlXWnczhiCbe1hsHnZKkJjoB8QVPTk87fgjlEEFgfP rhaAy3HA2nCCN0dyaVkHwovtgDEKUERrxyjbhXvGZDI9pPekMgoRZTBiKQl1rl1iYlLO 3eMyk2QLQ4nwt1lHk9Wi22SL9pANfHCZqLm8ISjuUG7qgDO/WUeEXHjMZEERtXNIJimy U8DYHAIKqvOjbM3HHQZafWHU7W6ziPprUkSVAOKzrlANF270TIiMbPC0i7Npo6KzRr7z fXag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=K+IK+vyD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from groat.vger.email (groat.vger.email. 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:33 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 4/5] gpio: add pinctrl based generic gpio driver Date: Thu, 5 Oct 2023 11:58:42 +0900 Message-Id: <20231005025843.508689-5-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Thu, 05 Oct 2023 07:20:02 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778925515156415749 X-GMAIL-MSGID: 1778925604600523031 Some pin controllers provide not only a method to set up lines but also gpio function. With this commit, a new generic gpio driver will be provided. It is implemented purely by using pinctrl interfaces. One of such pin controllers is Arm's SCMI. Signed-off-by: AKASHI Takahiro --- RFC v2 (Oct 5, 2023) * rename the driver to pin-control-gpio (CONFIG_GPIO_BY_PINCTRL) * return meaningful error codes instead of -1 * remove the masking at PIN_CONFIG_PACKED * handle emulated OPEN_DRAIN configuration at get_direction() * define config_set in gpio_chip * drop remove hook RFC (Oct 2, 2023) --- drivers/gpio/Kconfig | 7 ++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-by-pinctrl.c | 165 +++++++++++++++++++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 drivers/gpio/gpio-by-pinctrl.c diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 673bafb8be58..a60972be114c 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -216,6 +216,13 @@ config GPIO_BRCMSTB help Say yes here to enable GPIO support for Broadcom STB (BCM7XXX) SoCs. +config GPIO_BY_PINCTRL + tristate "GPIO support based on a pure pin control backend" + depends on GPIOLIB + help + Select this option to support GPIO devices based solely on pin + control, specifically pin configuration, such as SCMI. + config GPIO_CADENCE tristate "Cadence GPIO support" depends on OF_GPIO diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index eb73b5d633eb..71458d81e16a 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -43,6 +43,7 @@ obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o obj-$(CONFIG_GPIO_BT8XX) += gpio-bt8xx.o +obj-$(CONFIG_GPIO_BY_PINCTRL) += gpio-by-pinctrl.o obj-$(CONFIG_GPIO_CADENCE) += gpio-cadence.o obj-$(CONFIG_GPIO_CLPS711X) += gpio-clps711x.o obj-$(CONFIG_GPIO_SNPS_CREG) += gpio-creg-snps.o diff --git a/drivers/gpio/gpio-by-pinctrl.c b/drivers/gpio/gpio-by-pinctrl.c new file mode 100644 index 000000000000..c297a9633e03 --- /dev/null +++ b/drivers/gpio/gpio-by-pinctrl.c @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2023 Linaro Inc. +// Author: AKASHI takahiro + +#include +#include +#include +#include +#include +#include +#include "gpiolib.h" + +struct pin_control_gpio_priv { + struct gpio_chip chip; +}; + +static int pin_control_gpio_get_direction(struct gpio_chip *chip, + unsigned int offset) +{ + unsigned long config; + bool out_en, in_en; + int ret; + + config = PIN_CONFIG_OUTPUT_ENABLE; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + out_en = !!config; + else if (ret == -EINVAL) + out_en = false; + else + return ret; + + config = PIN_CONFIG_INPUT_ENABLE; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (!ret) + in_en = !!config; + else if (ret == -EINVAL) + in_en = false; + else + return ret; + + if (in_en && !out_en) + return GPIO_LINE_DIRECTION_IN; + + if (!in_en && out_en) + return GPIO_LINE_DIRECTION_OUT; + + if (in_en && out_en) { + /* This may be an emulation for output with open drain */ + config = PIN_CONFIG_DRIVE_OPEN_DRAIN; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, + &config); + if (!ret && config) + return GPIO_LINE_DIRECTION_OUT; + } + + return -EINVAL; +} + +static int pin_control_gpio_direction_input(struct gpio_chip *chip, + unsigned int offset) +{ + return pinctrl_gpio_direction_input(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_direction_output(struct gpio_chip *chip, + unsigned int offset, int val) +{ + return pinctrl_gpio_direction_output(chip->gpiodev->base + offset); +} + +static int pin_control_gpio_get(struct gpio_chip *chip, unsigned int offset) +{ + unsigned long config; + int ret; + + config = PIN_CONFIG_INPUT; + ret = pinctrl_gpio_get_config(chip->gpiodev->base + offset, &config); + if (ret) + return ret; + + if (config >> 8) + return 1; + + return 0; +} + +static void pin_control_gpio_set(struct gpio_chip *chip, unsigned int offset, + int val) +{ + unsigned long config; + + config = PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, val); + + pinctrl_gpio_set_config(chip->gpiodev->base + offset, config); +} + +static u16 sum_up_ngpios(struct gpio_chip *chip) +{ + struct gpio_pin_range *range; + struct gpio_device *gdev = chip->gpiodev; + u16 ngpios = 0; + + list_for_each_entry(range, &gdev->pin_ranges, node) { + ngpios += range->range.npins; + } + + return ngpios; +} + +static int pin_control_gpio_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pin_control_gpio_priv *priv; + struct gpio_chip *chip; + int ret; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + chip = &priv->chip; + chip->label = dev_name(dev); + chip->parent = dev; + chip->base = -1; + + chip->request = gpiochip_generic_request; + chip->free = gpiochip_generic_free; + chip->get_direction = pin_control_gpio_get_direction; + chip->direction_input = pin_control_gpio_direction_input; + chip->direction_output = pin_control_gpio_direction_output; + chip->get = pin_control_gpio_get; + chip->set = pin_control_gpio_set; + chip->set_config = gpiochip_generic_config; + + ret = devm_gpiochip_add_data(dev, chip, priv); + if (ret) + return ret; + + chip->ngpio = sum_up_ngpios(chip); + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static const struct of_device_id pin_control_gpio_match[] = { + { .compatible = "pin-control-gpio" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, pin_control_gpio_match); + +static struct platform_driver pin_control_gpio_driver = { + .probe = pin_control_gpio_probe, + .driver = { + .name = "pin-control-gpio", + .of_match_table = pin_control_gpio_match, + }, +}; +module_platform_driver(pin_control_gpio_driver); + +MODULE_AUTHOR("AKASHI Takahiro "); +MODULE_DESCRIPTION("Pinctrl based GPIO driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Oct 5 02:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Takahiro Akashi X-Patchwork-Id: 148721 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2016:b0:403:3b70:6f57 with SMTP id fe22csp327655vqb; Thu, 5 Oct 2023 07:14:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH5butQRYnRF2Dtqy3EWL9sWLFZlCk6sAUjOPdXZNWkhTtI0wX0emC2+gctJe4V60gXhV3c X-Received: by 2002:a9d:62d4:0:b0:6be:ea3e:367 with SMTP id z20-20020a9d62d4000000b006beea3e0367mr5046363otk.23.1696515272449; Thu, 05 Oct 2023 07:14:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696515272; cv=none; d=google.com; s=arc-20160816; b=D+nkCC9E5ATl9CvQ3uZYve6zPeaZBUVUWjv6mbB3nxL3r/tBuH5bMwh3UicmcvgjXw 1fBY3Ivm2W7TQqQsE+UgWrx7XJP5H/yEHuTTeWlEl20ip5J/faZG49WB3a1D0G0ZFCU5 L9gAGIu+34XhAitg3CS1NPFx7o0wqAAOOzxzyRiNuf+DLQ6jr5W+2C7hoI5P1lYl1vkr kXBiSPuuFviC7Cqpf6+Q1WIYdcqdcQA/0qBL1o1AzvdvjT83yq/+K6msHMK9WtPrNOiF akaQQHIgeS8I99QiQoiK/QegkYdlTsudrLOfGUo4+c5D4qec+FXUVFtDKxkcRIUOvNIw +Psw== ARC-Message-Signature: i=1; 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([2400:4050:c3e1:100:a16d:fce2:497:afb7]) by smtp.gmail.com with ESMTPSA id b18-20020a637152000000b005782ad723casm269265pgn.27.2023.10.04.19.59.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 19:59:36 -0700 (PDT) From: AKASHI Takahiro To: sudeep.holla@arm.com, cristian.marussi@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, linus.walleij@linaro.org Cc: Oleksii_Moisieiev@epam.com, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, AKASHI Takahiro Subject: [RFC v2 5/5] dt-bindings: gpio: Add bindings for pinctrl based generic gpio driver Date: Thu, 5 Oct 2023 11:58:43 +0900 Message-Id: <20231005025843.508689-6-takahiro.akashi@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231005025843.508689-1-takahiro.akashi@linaro.org> References: <20231005025843.508689-1-takahiro.akashi@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 05 Oct 2023 07:14:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778925198481842142 X-GMAIL-MSGID: 1778925198481842142 A dt binding for pin controller based generic gpio driver is defined in this commit. One usable device is Arm's SCMI. Signed-off-by: AKASHI Takahiro --- RFC v2 (Oct 5, 2023) * rename the binding to pin-control-gpio * add the "description" * remove nodename, hog properties, and a consumer example RFC (Oct 2, 2023) --- .../bindings/gpio/pin-control-gpio.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml diff --git a/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml new file mode 100644 index 000000000000..bc935dbd7edb --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/pin-control-gpio.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/pin-control-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Pin control based generic GPIO controller + +description: + The pin control-based GPIO will facilitate a pin controller's ability + to drive electric lines high/low and other generic properties of a + pin controller to perform general-purpose one-bit binary I/O. + +maintainers: + - AKASHI Takahiro + +properties: + compatible: + const: pin-control-gpio + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: true + + gpio-ranges-group-names: true + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + + required: + - gpio-hog + +required: + - compatible + - gpio-controller + - "#gpio-cells" + - gpio-ranges + +additionalProperties: false + +examples: + - | + gpio0: gpio@0 { + compatible = "pin-control-gpio"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&scmi_pinctrl 0 10 5>, + <&scmi_pinctrl 5 0 0>; + gpio-ranges-group-names = "", + "pinmux_gpio"; + };