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[8.43.85.97]) by mx.google.com with ESMTPS id bs1-20020a056402304100b0043d476f96c1si4265252edb.86.2022.08.24.00.46.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Aug 2022 00:46:20 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 6ADE53856DD5 for ; Wed, 24 Aug 2022 07:46:17 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id EE37038582BE for ; Wed, 24 Aug 2022 07:45:52 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EE37038582BE Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8Dx_2sg1wVjvIwIAA--.35319S2; Wed, 24 Aug 2022 15:45:46 +0800 (CST) From: xuchenghua@loongson.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH] LoongArch: Fix pr106459 by use HWIT instead of 1UL. Date: Wed, 24 Aug 2022 15:45:34 +0800 Message-Id: <20220824074534.3469398-1-xuchenghua@loongson.cn> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8Dx_2sg1wVjvIwIAA--.35319S2 X-Coremail-Antispam: 1UD129KBjvJXoWxCw1Duw48Cr43tr4xtryxKrg_yoWrCF18pr ya93Zxtr48Xr9xGr4DCa45Ww18tryfGr1Sv3WavFyIk3W7Xr97XF1UXrZxZFnrGw4ktrW3 Xw4Sk3Wjga1xJ3JanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUvY14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26r xl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1Y6r17McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4kE6xkIj40Ew7xC 0wCY02Avz4vE-syl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxV Aqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1Y 6r17MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6x kF7I0E14v26r1j6r4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AK xVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIdaVFxhVjvjDU0xZFpf9x0J UgmiiUUUUU= X-CM-SenderInfo: x0xfxv5qjk3to6or00hjvr0hdfq/ X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Chenghua Xu Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1742027809692913570?= X-GMAIL-MSGID: =?utf-8?q?1742027809692913570?= From: Chenghua Xu gcc/ChangeLog: PR target/106459 * config/loongarch/loongarch.cc (loongarch_build_integer): Use HOST_WIDE_INT. * config/loongarch/loongarch.h (IMM_REACH): Likewise. (HWIT_1U): New Defined. (LU12I_OPERAND): Use HOST_WIDE_INT. (LU32I_OPERAND): Likewise. (LU52I_OPERAND): Likewise. (HWIT_UC_0xFFF): Likwise. gcc/testsuite/ChangeLog: * gcc.target/loongarch/pr106459.c: New test. --- gcc/config/loongarch/loongarch.cc | 6 +++--- gcc/config/loongarch/loongarch.h | 15 +++++++++------ gcc/testsuite/gcc.target/loongarch/pr106459.c | 13 +++++++++++++ 3 files changed, 25 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/pr106459.c diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc index 207ac2762c6..1a33f668f20 100644 --- a/gcc/config/loongarch/loongarch.cc +++ b/gcc/config/loongarch/loongarch.cc @@ -1500,8 +1500,8 @@ loongarch_build_integer (struct loongarch_integer_op *codes, bool lu32i[2] = {(value & LU32I_B) == 0, (value & LU32I_B) == LU32I_B}; bool lu52i[2] = {(value & LU52I_B) == 0, (value & LU52I_B) == LU52I_B}; - int sign31 = (value & (1UL << 31)) >> 31; - int sign51 = (value & (1UL << 51)) >> 51; + int sign31 = (value & (HOST_WIDE_INT_1U << 31)) >> 31; + int sign51 = (value & (HOST_WIDE_INT_1U << 51)) >> 51; /* Determine whether the upper 32 bits are sign-extended from the lower 32 bits. If it is, the instructions to load the high order can be ommitted. */ @@ -1522,7 +1522,7 @@ loongarch_build_integer (struct loongarch_integer_op *codes, /* Determine whether the 52-61 bits are sign-extended from the low order, and if not, load the 52-61 bits. */ - if (!lu52i[(value & (1ULL << 51)) >> 51]) + if (!lu52i[(value & (HOST_WIDE_INT_1U << 51)) >> 51]) { codes[cost].method = METHOD_LU52I; codes[cost].value = value & LU52I_B; diff --git a/gcc/config/loongarch/loongarch.h b/gcc/config/loongarch/loongarch.h index 8b1288961e4..f4a9c329fef 100644 --- a/gcc/config/loongarch/loongarch.h +++ b/gcc/config/loongarch/loongarch.h @@ -561,7 +561,8 @@ enum reg_class 64, 65, 66, 67, 68, 69, 70, 71, 72, 73} #define IMM_BITS 12 -#define IMM_REACH (1LL << IMM_BITS) +#define IMM_REACH (HOST_WIDE_INT_1 << IMM_BITS) +#define HWIT_1U HOST_WIDE_INT_1U /* True if VALUE is an unsigned 6-bit number. */ @@ -589,18 +590,20 @@ enum reg_class /* True if VALUE can be loaded into a register using LU12I. */ #define LU12I_OPERAND(VALUE) \ - (((VALUE) | ((1UL << 31) - IMM_REACH)) == ((1UL << 31) - IMM_REACH) \ - || ((VALUE) | ((1UL << 31) - IMM_REACH)) + IMM_REACH == 0) + (((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) == ((HWIT_1U << 31) - IMM_REACH) \ + || ((VALUE) | ((HWIT_1U << 31) - IMM_REACH)) + IMM_REACH == 0) /* True if VALUE can be loaded into a register using LU32I. */ #define LU32I_OPERAND(VALUE) \ - (((VALUE) | (((1ULL << 19) - 1) << 32)) == (((1ULL << 19) - 1) << 32) \ - || ((VALUE) | (((1ULL << 19) - 1) << 32)) + (1ULL << 32) == 0) + (((VALUE) | (((HWIT_1U << 19) - 1) << 32)) == (((HWIT_1U << 19) - 1) << 32) \ + || ((VALUE) | (((HWIT_1U << 19) - 1) << 32)) + (HWIT_1U << 32) == 0) /* True if VALUE can be loaded into a register using LU52I. */ -#define LU52I_OPERAND(VALUE) (((VALUE) | (0xfffULL << 52)) == (0xfffULL << 52)) +#define HWIT_UC_0xFFF HOST_WIDE_INT_UC(0xfff) +#define LU52I_OPERAND(VALUE) \ + (((VALUE) | (HWIT_UC_0xFFF << 52)) == (HWIT_UC_0xFFF << 52)) /* Return a value X with the low 12 bits clear, and such that VALUE - X is a signed 12-bit value. */ diff --git a/gcc/testsuite/gcc.target/loongarch/pr106459.c b/gcc/testsuite/gcc.target/loongarch/pr106459.c new file mode 100644 index 00000000000..eb737dc49c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/pr106459.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ + +/* https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106459 */ + +typedef unsigned int UDItype __attribute__((mode(DI))); +int foo(UDItype x) { + x = x & (((UDItype)(((UDItype)(((UDItype)0x0F << 8) | 0x0F) << (2 * 8)) | + (((UDItype)0x0F << 8) | 0x0F)) + << (4 * 8)) | + (((UDItype)(((UDItype)0x0F << 8) | 0x0F) << (2 * 8)) | + (((UDItype)0x0F << 8) | 0x0F))); + return x; +}