From patchwork Wed Oct 4 18:40:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148458 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333278vqb; Wed, 4 Oct 2023 11:41:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFiGinmtQVJ7jxAxqgVPxzDHJPk19wlDJi7f3lVmyuSB/fnQ0qSuiF0XjKlOpPARNTMu2ki X-Received: by 2002:a05:6358:788:b0:142:d097:3725 with SMTP id n8-20020a056358078800b00142d0973725mr3285245rwj.9.1696444905343; Wed, 04 Oct 2023 11:41:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444905; cv=none; d=google.com; s=arc-20160816; b=jkJAV7zGh7DRH06vFN/ZUU0W4muehkK8pBAyAOFGZY8S+1h9psaMD9GtLJ7qR+sFFT qPc5divS3/9/RH5SNySL/7iuyYX6Pv4w1LG3BFn+x+6hFfBwGvlCNF87T6bxej52nhl/ NgdaRYSEWbWnMys+i5251SvwDz+c75Qi+dG0L7AGtELkqBBxelUWTkkHrW8z45h6eiC7 A9T+eYgpaF4kOK05h0IRm9lsd/JobQ22e80321Yef+GWZUc5Fg/oCBK4lXGK5ye8ryP5 P32riBK8YSUJL5+YBNDiaa0HcKk/bdTkNhpStU0kAYt+yyLhjXlKY+x4VvbQXUbw5gUT tugA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=H/U7v0Mxlb62Ky5S4Xe56sOhYGVMnYCNcLxgYeiIbGs=; fh=7F/hV/uBtIfgn7VgkzzxuX5/2Hz7JEkrYjmTOxErzMc=; b=kaAtUlovHKchITeIVS7M8/Fr5I5suV3Q1fMbSoFqoiqF85YZA927WRw53Wp45rN420 SKih0Rq33J2/pkDnlz847WfsurLq5xYpHftJxRVZJILWxtf7ZxQqk6hOF41iMqy3bwju oBIUQD2yKWuCSFhpw09EAWWWP+7hikxANrEicm8ef70rJZJZltxIlh7OdH8prTYdi81/ 24/MWXk/v6dIXpTUiIWMPP2pBmuadmwwKlLXW3TW8wCJE0+7Xuongqv0ayqhWBmpeTzl N6zWcfnCDjjZEd8j6uqJ6paxXhFoi60SksgcoTxcsC/5cURV7YiR2PAhKIAjZ6ZXY/op HwuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hoQqEAcx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id o127-20020a634185000000b00578b40703bcsi3861738pga.885.2023.10.04.11.41.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:41:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hoQqEAcx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 4622B8182396; Wed, 4 Oct 2023 11:41:35 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243510AbjJDSku (ORCPT + 19 others); Wed, 4 Oct 2023 14:40:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243683AbjJDSks (ORCPT ); Wed, 4 Oct 2023 14:40:48 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A7CEF98 for ; Wed, 4 Oct 2023 11:40:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444844; x=1727980844; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=kxZg7pM+ZgTIS+2pCslTI1nBxg1AM3SNhCsGF5a1yr8=; b=hoQqEAcx/83yGy0WXrMAhg5Gb3FgZh+FR/ie/nshv+Bn4OFKGweWGBcR yyKul2iWjO9jMwMHtGIoNhv+Qifab0GbYpkhmpMFrkKhfGo5Hp1vL0rWj qHYTJlss8NPO3Ll1OkwrqrjB3EAZxSyspirHFznrAxnDRI5MSvEY71nRq B77NIhmOX+Nw8GrJyTg6afJE5dRqkEg62rb60/17tuHuPBPPyVIOA/ACw LUfxRZCUQv1vGrPd7CFk1dox9DDCrQ2jSac8qBOXvPOHvxZP+6Cg1+ex1 5rRu445RHbgqZQ0icWzjo3QCW7OBgW4Eh2XxTdtj2b0IH9MBNszTElZTF g==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537675" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537675" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786625985" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786625985" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:41 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang , Sandipan Das , Ravi Bangoria , Athira Rajeev Subject: [PATCH V4 1/7] perf: Add branch stack counters Date: Wed, 4 Oct 2023 11:40:38 -0700 Message-Id: <20231004184044.3062788-1-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Spam-Status: No, score=2.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:41:35 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851413050850304 X-GMAIL-MSGID: 1778851413050850304 From: Kan Liang Currently, the additional information of a branch entry is stored in a u64 space. With more and more information added, the space is running out. For example, the information of occurrences of events will be added for each branch. Two places were suggested to append the counters. https://lore.kernel.org/lkml/20230802215814.GH231007@hirez.programming.kicks-ass.net/ One place is right after the flags of each branch entry. It changes the existing struct perf_branch_entry. The later ARCH specific implementation has to be really careful to consistently pick the right struct. The other place is right after the entire struct perf_branch_stack. The disadvantage is that the pointer of the extra space has to be recorded. The common interface perf_sample_save_brstack() has to be updated. The latter is much straightforward, and should be easily understood and maintained. It is implemented in the patch. Add a new branch sample type, PERF_SAMPLE_BRANCH_COUNTERS, to indicate the event which is recorded in the branch info. The "u64 counters" may store the occurrences of several events. The information regarding the number of events/counters and the width of each counter should be exposed via sysfs as a reference for the perf tool. Define the branch_counter_nr and branch_counter_width ABI here. The support will be implemented later in the Intel-specific patch. Suggested-by: Peter Zijlstra (Intel) Signed-off-by: Kan Liang Cc: Sandipan Das Cc: Ravi Bangoria Cc: Athira Rajeev --- Changes since V3: - Add a new branch sample type, PERF_SAMPLE_BRANCH_COUNTERS Drop the two branch sample type in V2. - Add the branch_counter_nr and branch_counter_width ABI .../testing/sysfs-bus-event_source-devices-caps | 6 ++++++ arch/powerpc/perf/core-book3s.c | 2 +- arch/x86/events/amd/core.c | 2 +- arch/x86/events/core.c | 2 +- arch/x86/events/intel/core.c | 2 +- arch/x86/events/intel/ds.c | 4 ++-- include/linux/perf_event.h | 17 ++++++++++++++++- include/uapi/linux/perf_event.h | 10 ++++++++++ kernel/events/core.c | 8 ++++++++ 9 files changed, 46 insertions(+), 7 deletions(-) diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-caps b/Documentation/ABI/testing/sysfs-bus-event_source-devices-caps index 8757dcf41c08..451f0c620aa7 100644 --- a/Documentation/ABI/testing/sysfs-bus-event_source-devices-caps +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-caps @@ -16,3 +16,9 @@ Description: Example output in powerpc: grep . /sys/bus/event_source/devices/cpu/caps/* /sys/bus/event_source/devices/cpu/caps/pmu_name:POWER9 + + The "branch_counter_nr" in the supported platform exposes the + maximum number of counters which can be shown in the u64 counters + of PERF_SAMPLE_BRANCH_COUNTERS, while the "branch_counter_width" + exposes the width of each counter. Both of them can be used by + the perf tool to parse the logged counters in each branch. diff --git a/arch/powerpc/perf/core-book3s.c b/arch/powerpc/perf/core-book3s.c index 8c1f7def596e..3c14596bbfaf 100644 --- a/arch/powerpc/perf/core-book3s.c +++ b/arch/powerpc/perf/core-book3s.c @@ -2313,7 +2313,7 @@ static void record_and_restart(struct perf_event *event, unsigned long val, struct cpu_hw_events *cpuhw; cpuhw = this_cpu_ptr(&cpu_hw_events); power_pmu_bhrb_read(event, cpuhw); - perf_sample_save_brstack(&data, event, &cpuhw->bhrb_stack); + perf_sample_save_brstack(&data, event, &cpuhw->bhrb_stack, NULL); } if (event->attr.sample_type & PERF_SAMPLE_DATA_SRC && diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index e24976593a29..4ee6390b45c9 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -940,7 +940,7 @@ static int amd_pmu_v2_handle_irq(struct pt_regs *regs) continue; if (has_branch_stack(event)) - perf_sample_save_brstack(&data, event, &cpuc->lbr_stack); + perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL); if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 40ad1425ffa2..40c9af124128 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -1702,7 +1702,7 @@ int x86_pmu_handle_irq(struct pt_regs *regs) perf_sample_data_init(&data, 0, event->hw.last_period); if (has_branch_stack(event)) - perf_sample_save_brstack(&data, event, &cpuc->lbr_stack); + perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL); if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a08f794a0e79..41a164764a84 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3047,7 +3047,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) perf_sample_data_init(&data, 0, event->hw.last_period); if (has_branch_stack(event)) - perf_sample_save_brstack(&data, event, &cpuc->lbr_stack); + perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL); if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index bf97ab904d40..cb3f329f8fa4 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1755,7 +1755,7 @@ static void setup_pebs_fixed_sample_data(struct perf_event *event, setup_pebs_time(event, data, pebs->tsc); if (has_branch_stack(event)) - perf_sample_save_brstack(data, event, &cpuc->lbr_stack); + perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); } static void adaptive_pebs_save_regs(struct pt_regs *regs, @@ -1912,7 +1912,7 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, if (has_branch_stack(event)) { intel_pmu_store_pebs_lbrs(lbr); - perf_sample_save_brstack(data, event, &cpuc->lbr_stack); + perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); } } diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index e85cd1c0eaf3..9ad79f8107cb 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1138,6 +1138,10 @@ static inline bool branch_sample_priv(const struct perf_event *event) return event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_PRIV_SAVE; } +static inline bool branch_sample_counters(const struct perf_event *event) +{ + return event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_COUNTERS; +} struct perf_sample_data { /* @@ -1172,6 +1176,7 @@ struct perf_sample_data { struct perf_callchain_entry *callchain; struct perf_raw_record *raw; struct perf_branch_stack *br_stack; + u64 *br_stack_cntr; union perf_sample_weight weight; union perf_mem_data_src data_src; u64 txn; @@ -1249,7 +1254,8 @@ static inline void perf_sample_save_raw_data(struct perf_sample_data *data, static inline void perf_sample_save_brstack(struct perf_sample_data *data, struct perf_event *event, - struct perf_branch_stack *brs) + struct perf_branch_stack *brs, + u64 *brs_cntr) { int size = sizeof(u64); /* nr */ @@ -1257,7 +1263,16 @@ static inline void perf_sample_save_brstack(struct perf_sample_data *data, size += sizeof(u64); size += brs->nr * sizeof(struct perf_branch_entry); + /* + * The extension space for counters is appended after the + * struct perf_branch_stack. It is used to store the occurrences + * of events of each branch. + */ + if (brs_cntr) + size += brs->nr * sizeof(u64); + data->br_stack = brs; + data->br_stack_cntr = brs_cntr; data->dyn_size += size; data->sample_flags |= PERF_SAMPLE_BRANCH_STACK; } diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h index 39c6a250dd1b..4461f380425b 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -204,6 +204,8 @@ enum perf_branch_sample_type_shift { PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ + PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, /* save occurrences of events on a branch */ + PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ }; @@ -235,6 +237,8 @@ enum perf_branch_sample_type { PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, + PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, + PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, }; @@ -982,6 +986,12 @@ enum perf_event_type { * { u64 nr; * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX * { u64 from, to, flags } lbr[nr]; + * # + * # The format of the counters is decided by the + * # "branch_counter_nr" and "branch_counter_width", + * # which are defined in the ABI. + * # + * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS * } && PERF_SAMPLE_BRANCH_STACK * * { u64 abi; # enum perf_sample_regs_abi diff --git a/kernel/events/core.c b/kernel/events/core.c index 41e28f64a4a9..56b08ffeed2f 100644 --- a/kernel/events/core.c +++ b/kernel/events/core.c @@ -7336,6 +7336,14 @@ void perf_output_sample(struct perf_output_handle *handle, if (branch_sample_hw_index(event)) perf_output_put(handle, data->br_stack->hw_idx); perf_output_copy(handle, data->br_stack->entries, size); + /* + * Add the extension space which is appended + * right after the struct perf_branch_stack. + */ + if (data->br_stack_cntr) { + size = data->br_stack->nr * sizeof(u64); + perf_output_copy(handle, data->br_stack_cntr, size); + } } else { /* * we always store at least the value of nr From patchwork Wed Oct 4 18:40:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148455 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333178vqb; Wed, 4 Oct 2023 11:41:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGkxyV65U1eIReBbYwEZcLQfndfLavlp6KSyppTqHD8EQq6QoxTSyZIojGdMUUi6SQ6Voo5 X-Received: by 2002:a17:90b:1e07:b0:268:535f:7c15 with SMTP id pg7-20020a17090b1e0700b00268535f7c15mr701389pjb.0.1696444896406; Wed, 04 Oct 2023 11:41:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444896; cv=none; d=google.com; s=arc-20160816; b=PHxDhT9Ls2Q4VD6MsB3M04699qqv1ZgkysYH0Z6cusUq+8eWz4slu0TumedJtZcd6i zbPz4Uh3pqwrFnDXxQJqPQnF/1Hj+2jqH94+d1rGNtH1W1wvUeGRvF38wnkf+S3JpfVG mrzfFjcownlWmYOqqCoAi41nV+eLk29oywiUx5fM4NBZJeKga7nQlxgtJUHCtYr8NE6d ZDOIhqhex8WbPjuHYk1if7p4zBSkBZrSGU/6wcfn1jlu8cSE6d1QVgQM5W9CLL0qcHc3 Qf6TIevZI1B2GvDMNutaCm8gLHt+Q3GecDxWBFcZSa6CdLUVCKVOsOP7EagMfuZcpWFe xIFw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mMcZSGLu/j2Cini1CoEPpPxC1vvQXzYd4WZZ5K1d8BM=; fh=PWMgxgslqMjOtye8I2qVy8I5pPekyJtpFTusQltnkEg=; b=I8uv5dVunmSjW5j/wdfRcZ0wiDoUR2jTFw+mQkmseezgR2S8hponOcwUJbEX7RwQ0h KRXfqTUQE0EaWmu8zj84WP6gLhnRyVIan5v+2ffhY3SX1XV1VPtHcrz2LqpR/BOxmrtG VCJLWbbt4MIjKxNYu+Ya3CO9LHe8Goq+PqqpWYjj7MOigOhRqH4Obb7EOoz3i9FBkLDO 4UbM5gU9pn0CF//Q6eoXqeHAED1quSVUYcmEfNUPqDG5tofp+JzBlSIxmKi7N9lJZnmH +XUJVkTkk21YN5rxHeRoCA18eSLJF5F7sSwKd2b0LMB+IZdXHHmozWT0jHoyBcuqBRz5 WUHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eU1D3wL8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id pj11-20020a17090b4f4b00b002791b62066csi2216244pjb.38.2023.10.04.11.41.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:41:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=eU1D3wL8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 2E7F88047645; Wed, 4 Oct 2023 11:41:03 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244471AbjJDSkx (ORCPT + 19 others); Wed, 4 Oct 2023 14:40:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233409AbjJDSks (ORCPT ); Wed, 4 Oct 2023 14:40:48 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B6D7EEC for ; Wed, 4 Oct 2023 11:40:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444843; x=1727980843; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jQgPOe5NH396br31I0Ovdo2DX5aYXqmioMy/hZgz9B0=; b=eU1D3wL8ur2DCFx0ESTw6V/dw8mQTumm/cLDOvo7So3O2rzdipF44e63 D98gv9IhbsnlLOmnla56wAdQuGte3JAv8VPafhBPzsSVRIZJjp/UyuoEK VWfCvyRbz65FOR2SDsi5hqaVbotqTb+F31ndNosb7OcAO6M7VKeTBKTp9 6fGeMRAfOdMy/Gp2FRdaFPgEBeFQgayF+52iKOU9pkd4oLeDPSUNbePgK jbDi7L7fl/cTVCPHVGy6c8BUGFQ2BKTiXtHfTQBUSAqUHWxvLJ/1tSI1i Eq6+6z2RcqBPF0h666cSG8a+slb6GE9neDwvXMNOUw53vnUpSZkaB8gG2 Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537681" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537681" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786625991" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786625991" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 2/7] perf/x86: Add PERF_X86_EVENT_NEEDS_BRANCH_STACK flag Date: Wed, 4 Oct 2023 11:40:39 -0700 Message-Id: <20231004184044.3062788-2-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:41:03 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851403638988146 X-GMAIL-MSGID: 1778851403638988146 From: Kan Liang Currently, branch_sample_type !=0 is used to check whether a branch stack setup is required. But it doesn't check the sample type, unnecessary branch stack setup may be done for a counting event. E.g., perf record -e "{branch-instructions,branch-misses}:S" -j any Also, the event only with the new PERF_SAMPLE_BRANCH_COUNTERS branch sample type may not require a branch stack setup either. Add a new flag NEEDS_BRANCH_STACK to indicate whether the event requires a branch stack setup. Replace the needs_branch_stack() by checking the new flag. The counting event check is implemented here. The later patch will take the new PERF_SAMPLE_BRANCH_COUNTERS into account. Signed-off-by: Kan Liang --- No changes since V3 arch/x86/events/intel/core.c | 14 +++++++++++--- arch/x86/events/perf_event_flags.h | 1 + 2 files changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 41a164764a84..a99449c0d77c 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2527,9 +2527,14 @@ static void intel_pmu_assign_event(struct perf_event *event, int idx) perf_report_aux_output_id(event, idx); } +static __always_inline bool intel_pmu_needs_branch_stack(struct perf_event *event) +{ + return event->hw.flags & PERF_X86_EVENT_NEEDS_BRANCH_STACK; +} + static void intel_pmu_del_event(struct perf_event *event) { - if (needs_branch_stack(event)) + if (intel_pmu_needs_branch_stack(event)) intel_pmu_lbr_del(event); if (event->attr.precise_ip) intel_pmu_pebs_del(event); @@ -2820,7 +2825,7 @@ static void intel_pmu_add_event(struct perf_event *event) { if (event->attr.precise_ip) intel_pmu_pebs_add(event); - if (needs_branch_stack(event)) + if (intel_pmu_needs_branch_stack(event)) intel_pmu_lbr_add(event); } @@ -3897,7 +3902,10 @@ static int intel_pmu_hw_config(struct perf_event *event) x86_pmu.pebs_aliases(event); } - if (needs_branch_stack(event)) { + if (needs_branch_stack(event) && is_sampling_event(event)) + event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; + + if (intel_pmu_needs_branch_stack(event)) { ret = intel_pmu_setup_lbr_filter(event); if (ret) return ret; diff --git a/arch/x86/events/perf_event_flags.h b/arch/x86/events/perf_event_flags.h index 1dc19b9b4426..a1685981c520 100644 --- a/arch/x86/events/perf_event_flags.h +++ b/arch/x86/events/perf_event_flags.h @@ -20,3 +20,4 @@ PERF_ARCH(TOPDOWN, 0x04000) /* Count Topdown slots/metrics events */ PERF_ARCH(PEBS_STLAT, 0x08000) /* st+stlat data address sampling */ PERF_ARCH(AMD_BRS, 0x10000) /* AMD Branch Sampling */ PERF_ARCH(PEBS_LAT_HYBRID, 0x20000) /* ld and st lat for hybrid */ +PERF_ARCH(NEEDS_BRANCH_STACK, 0x40000) /* require branch stack setup */ From patchwork Wed Oct 4 18:40:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148460 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333453vqb; Wed, 4 Oct 2023 11:42:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IERrUw28ZUiRPT/yviy6LoHbuJ0DkTjwlcpFbC2ZeK9xzroUD0KcEQXk60xRuByBXTI5fuz X-Received: by 2002:a05:6808:159c:b0:3a8:512a:41b8 with SMTP id t28-20020a056808159c00b003a8512a41b8mr4028322oiw.21.1696444929371; Wed, 04 Oct 2023 11:42:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444929; cv=none; d=google.com; s=arc-20160816; b=NL3f/nAJIWKv4tmDmU+WzXXjrFZVvHE4j2JAispG45eaac6zJd37KViB7X162Uo4hc 0t+IkDKzQIjphqFcm1ACmEYlHTI52X3o6j4gLGfAvUET/ZYx/REpsh8g88wfuI5MZxk5 bB3JCgvQdKB6l8Xm9FT7cFjGmU9z0AFhAQrKRIFFiguXQCu5oEfxUjFT1UQ5vTWUCmli 4d3+hXeQ1M9aH42OzOWWxBNqoZNJQLIXz39iPiVenBinOSRvPkTc7XWPOaRibIwR7Var v5koLmXyhxh5nX+xOaWs17jb76FIOdoU122HkVBfJWJatGdOmBI5y2+bixs1E833yGxw r6GA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eupAEjouBZFxJSyzCxrk/2JGtgQfWlao0fa+WaRSzN0=; fh=PWMgxgslqMjOtye8I2qVy8I5pPekyJtpFTusQltnkEg=; b=MAA0kXp0Ly0IJtqRAzuemISB55dSPUl3B423tkck9aDo7qFfhgn4caJj1T7BHzb6v0 VuJjJpQA1YwrZWgRmySP3sPwIlntWqrtjjDMby+/SuxGMJxZlds4ISP1aZCgzoSBOI+a HDgWGxr30hOnrRAEymNgMQzQyIcGnRxLv34e+2A27t9ib4Ne+eIcFiOgiTm0JqkiHXZE qyVyNqtAgprOB6AViL5zrRCziDGFoV8gbk5emLctSBw5aeKqxho6wqcPKPFXDcXB6sIn pTL6+hWupk2JPFdwP2mW61w3OOp/JqwRgO67YjLXvFtM3Q4Sc96FR7m9k7Rq4djdLE9I gkgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ril4Qlp3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id o15-20020a656a4f000000b005778df5647dsi4826186pgu.401.2023.10.04.11.42.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:42:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Ril4Qlp3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 9788881BAA60; Wed, 4 Oct 2023 11:42:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244534AbjJDSk7 (ORCPT + 19 others); Wed, 4 Oct 2023 14:40:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38392 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243780AbjJDSku (ORCPT ); Wed, 4 Oct 2023 14:40:50 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4B6B9C6 for ; Wed, 4 Oct 2023 11:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444846; x=1727980846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dXb7QKe6eBS32qydfKpLV9J0fiI9elfImuMMvPKmnxA=; b=Ril4Qlp3b4awbnLOPv3BrZQbzv/K/Up53x3S8/MtOhMRq8ZV7IvCZ7GV lg48U9gBsqaRB/7XYl+SjMq1I/cjmNehzJ/g3EV2uupgdjJDbUXo6VwEq 597aYitdH6m1jDL/e2Bu+LpC13Bnw1YNA+gxwvR3/Ddee+7W3uK9YZsaM PgDYj/3s0rLVKTYmC608Sogs0mMMcvlZ1vwkQeLhJDWZXKNd7wWIGUUGI evOo0SHNsr+9BkP93oasdQ1Yb+D7B4xsIXDZno0hC3ZloTzlDb18AcU46 jCM/e2qkx5V/X8fl6oqI/I8dsOT7x8pg0o3Niqh6Kz2F7tQbg0VMu346q g==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537687" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537687" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:42 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786625996" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786625996" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 3/7] perf: Add branch_sample_call_stack Date: Wed, 4 Oct 2023 11:40:40 -0700 Message-Id: <20231004184044.3062788-3-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:42:06 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851438315215508 X-GMAIL-MSGID: 1778851438315215508 From: Kan Liang Add a helper function to check call stack sample type. The later patch will invoke the function in several places. Signed-off-by: Kan Liang --- No changes since V3 arch/x86/events/core.c | 2 +- include/linux/perf_event.h | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 40c9af124128..09050641ce5d 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -601,7 +601,7 @@ int x86_pmu_hw_config(struct perf_event *event) } } - if (event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK) + if (branch_sample_call_stack(event)) event->attach_state |= PERF_ATTACH_TASK_DATA; /* diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h index 9ad79f8107cb..826d2d632184 100644 --- a/include/linux/perf_event.h +++ b/include/linux/perf_event.h @@ -1143,6 +1143,11 @@ static inline bool branch_sample_counters(const struct perf_event *event) return event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_COUNTERS; } +static inline bool branch_sample_call_stack(const struct perf_event *event) +{ + return event->attr.branch_sample_type & PERF_SAMPLE_BRANCH_CALL_STACK; +} + struct perf_sample_data { /* * Fields set by perf_sample_data_init() unconditionally, From patchwork Wed Oct 4 18:40:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148459 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333353vqb; Wed, 4 Oct 2023 11:41:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGRIbHKcsnAkdSSD3KwZdu2iYIjt7iaMpSiQZMpAmi+Kt5flnpHjVRGUZlp+bPTEbudyTn X-Received: by 2002:a17:90a:b888:b0:274:8a03:b546 with SMTP id o8-20020a17090ab88800b002748a03b546mr3092616pjr.23.1696444917982; Wed, 04 Oct 2023 11:41:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444917; cv=none; d=google.com; s=arc-20160816; b=ShXtr04PTe7zmVFc5r9R8IrXnqOWMDUBBAe8V9COBAxrBOnMED2e/UOhUAxIgkwkjl 2aJFFBabU2igggHIO6gX/1BccS0BcgC/UHggwXGbMUHu8rSUY/btVFKnE990eT3WJSQt xTinFjHRxTpt5q74BqvSKubYFMnDgEsAag+oDUm28BmZaqWKa+z/g3as/bXpOsMnO7tF s7fQOQqGEaNwcEk0hUvF1s3FreSkovtNJCWIiMAh7/1ygVWtD0wOvyuwvu/Ukvxa7yUU xWjYC6sleq9VSPKsPdQp2YlwvVbrlcqtHddeNQHds/7PMLvA2ORAkBVrvVzFPXWaQCjP 3ZfA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=NAmJlnSegEnG2dj4wNDvgbbat6zNhRJD7ZfiFD8DUag=; fh=PWMgxgslqMjOtye8I2qVy8I5pPekyJtpFTusQltnkEg=; b=lNDz2D4fowsjxSlIbGdTOCklzM0dbCMhjVJpAKtfib6yMKvuq8c+LDq4labSWGV0w+ waCmVCcjS/a0QEqkVjKG/eYQZq36/Nw25Z2kDIuo0YDa2ZUGoro2t+z+yTuEB0jfS7L8 n/D7N5fBprtuKrcU8gvU4JTty06nVPFGjAoTJuDJaXmBvQ7luYYFIT7GtgxWNbY0TTBb oqkuma01Cnj38vE1yGpSbxpcdLsUJNmxVj0PVCxUL5upw6tdbdukpKiaYilT3XBqydm1 Wmvr1ypRppBJ5zXqcbSOiyPA9juVpURSWmPhembFv0qszOgKewFRtBU9H7a11JORiaV0 WlBg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=k919QwiV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id iq12-20020a17090afb4c00b0027408bd8420si1948769pjb.13.2023.10.04.11.41.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:41:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=k919QwiV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 489AD83B6BD6; Wed, 4 Oct 2023 11:41:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244542AbjJDSlG (ORCPT + 19 others); Wed, 4 Oct 2023 14:41:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244378AbjJDSkv (ORCPT ); Wed, 4 Oct 2023 14:40:51 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5040AC9 for ; Wed, 4 Oct 2023 11:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444846; x=1727980846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9kTZ2eYX0hTXnP/lFrkhvSXCqog0yp47aGgGexFl6mU=; b=k919QwiVQhQvfdNwGvLj4E2MteC4M1dskIqR1TAvdfUpDHhe/0jfVn0k D5wGFXze+wbrCqDWzyr2vX7p0HQunmzLacHkhiibP3Gt3cH+dxpmB3YVH 8+mRvqf4+6GGNYFKFQzCGgaggxwmuTVLdmfBOn76kyhM7ORXig78cmZdd Ofuj2jSTk2j6BfQxm8UvEUB+/loUpKcHsVrGadNCa34f3M/dE2J2HA2Sg icHvwOXOQgKCdhhA7beBvoY9EPk+0yi+FVvLuGYRSBEYqMKRAX+LbBwOU 8kH9OaVwM0AAl3B/zk77Sv2JFs2IyWodn8mW0x/Eq1uL91eBcz88d+rtG Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537693" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537693" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786626007" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786626007" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 4/7] perf/x86/intel: Support LBR event logging Date: Wed, 4 Oct 2023 11:40:41 -0700 Message-Id: <20231004184044.3062788-4-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:41:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851426097450188 X-GMAIL-MSGID: 1778851426097450188 From: Kan Liang The LBR event logging introduces a per-counter indication of precise event occurrences in LBRs. It can provide a means to attribute exposed retirement latency to combinations of events across a block of instructions. It also provides a means of attributing Timed LBR latencies to events. The feature is first introduced on SRF/GRR. It is an enhancement of the ARCH LBR. It adds new fields in the LBR_INFO MSRs to log the occurrences of events on the GP counters. The information is displayed by the order of counters. The design proposed in this patch requires that the events which are logged must be in a group with the event that has LBR. If there are more than one LBR group, the event logging information only from the current group (overflowed) are stored for the perf tool, otherwise the perf tool cannot know which and when other groups are scheduled especially when multiplexing is triggered. The user can ensure it uses the maximum number of counters that support LBR info (4 by now) by making the group large enough. The HW only logs events by the order of counters. The order may be different from the order of enabling which the perf tool can understand. When parsing the information of each branch entry, convert the counter order to the enabled order, and store the enabled order in the extension space. Unconditionally reset LBRs for an LBR event group when it's deleted. The logged events' occurrences information is only valid for the current LBR group. If another LBR group is scheduled later, the information from the stale LBRs would be otherwise wrongly interpreted. Add a sanity check in intel_pmu_hw_config(). Disable the feature if other counter filters (inv, cmask, edge, in_tx) are set or LBR call stack mode is enabled. (For the LBR call stack mode, we cannot simply flush the LBR, since it will break the call stack. Also, there is no obvious usage with the call stack mode for now.) Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't require any branch stack setup. Expose the maximum number of supported counters and the width of the counters into the sysfs. The perf tool can use the information to parse the logged counters in each branch. Signed-off-by: Kan Liang --- Changes since V3 - Support the "branch_counter_nr" and "branch_counter_width" - Support the PERF_SAMPLE_BRANCH_COUNTERS arch/x86/events/intel/core.c | 91 +++++++++++++++++++++++++++-- arch/x86/events/intel/ds.c | 2 +- arch/x86/events/intel/lbr.c | 94 +++++++++++++++++++++++++++++- arch/x86/events/perf_event.h | 12 ++++ arch/x86/events/perf_event_flags.h | 1 + arch/x86/include/asm/msr-index.h | 2 + arch/x86/include/asm/perf_event.h | 4 ++ 7 files changed, 198 insertions(+), 8 deletions(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a99449c0d77c..5557310d430a 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -2792,6 +2792,7 @@ static void intel_pmu_enable_fixed(struct perf_event *event) static void intel_pmu_enable_event(struct perf_event *event) { + u64 enable_mask = ARCH_PERFMON_EVENTSEL_ENABLE; struct hw_perf_event *hwc = &event->hw; int idx = hwc->idx; @@ -2800,8 +2801,10 @@ static void intel_pmu_enable_event(struct perf_event *event) switch (idx) { case 0 ... INTEL_PMC_IDX_FIXED - 1: + if (branch_sample_counters(event)) + enable_mask |= ARCH_PERFMON_EVENTSEL_LBR_LOG; intel_set_masks(event, idx); - __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE); + __x86_pmu_enable_event(hwc, enable_mask); break; case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1: case INTEL_PMC_IDX_METRIC_BASE ... INTEL_PMC_IDX_METRIC_END: @@ -3052,7 +3055,7 @@ static int handle_pmi_common(struct pt_regs *regs, u64 status) perf_sample_data_init(&data, 0, event->hw.last_period); if (has_branch_stack(event)) - perf_sample_save_brstack(&data, event, &cpuc->lbr_stack, NULL); + intel_pmu_lbr_save_brstack(&data, cpuc, event); if (perf_event_overflow(event, &data, regs)) x86_pmu_stop(event, 0); @@ -3617,6 +3620,13 @@ intel_get_event_constraints(struct cpu_hw_events *cpuc, int idx, if (cpuc->excl_cntrs) return intel_get_excl_constraints(cpuc, event, idx, c2); + /* The LBR event logging may not be available for all counters. */ + if (branch_sample_counters(event)) { + c2 = dyn_constraint(cpuc, c2, idx); + c2->idxmsk64 &= x86_pmu.lbr_events; + c2->weight = hweight64(c2->idxmsk64); + } + return c2; } @@ -3905,6 +3915,44 @@ static int intel_pmu_hw_config(struct perf_event *event) if (needs_branch_stack(event) && is_sampling_event(event)) event->hw.flags |= PERF_X86_EVENT_NEEDS_BRANCH_STACK; + if (branch_sample_counters(event)) { + struct perf_event *leader, *sibling; + + if (!(x86_pmu.flags & PMU_FL_LBR_EVENT) || + (event->attr.config & ~INTEL_ARCH_EVENT_MASK)) + return -EINVAL; + + /* + * The event logging is not supported in the call stack mode + * yet, since we cannot simply flush the LBR during e.g., + * multiplexing. Also, there is no obvious usage with the call + * stack mode. Simply forbids it for now. + * + * If any events in the group enable the LBR event logging + * feature, the group is treated as a LBR event logging group, + * which requires the extra space to store the counters. + */ + leader = event->group_leader; + if (branch_sample_call_stack(leader)) + return -EINVAL; + leader->hw.flags |= PERF_X86_EVENT_BRANCH_COUNTERS; + + for_each_sibling_event(sibling, leader) { + if (branch_sample_call_stack(sibling)) + return -EINVAL; + } + + /* + * Only applying the PERF_SAMPLE_BRANCH_COUNTERS doesn't + * require any branch stack setup. + * Clear the bit to avoid unnecessary branch stack setup. + */ + if (0 == (event->attr.branch_sample_type & + ~(PERF_SAMPLE_BRANCH_PLM_ALL | + PERF_SAMPLE_BRANCH_COUNTERS))) + event->hw.flags &= ~PERF_X86_EVENT_NEEDS_BRANCH_STACK; + } + if (intel_pmu_needs_branch_stack(event)) { ret = intel_pmu_setup_lbr_filter(event); if (ret) @@ -4383,8 +4431,13 @@ cmt_get_event_constraints(struct cpu_hw_events *cpuc, int idx, */ if (event->attr.precise_ip == 3) { /* Force instruction:ppp on PMC0, 1 and Fixed counter 0 */ - if (constraint_match(&fixed0_constraint, event->hw.config)) - return &fixed0_counter0_1_constraint; + if (constraint_match(&fixed0_constraint, event->hw.config)) { + /* The fixed counter 0 doesn't support LBR event logging. */ + if (branch_sample_counters(event)) + return &counter0_1_constraint; + else + return &fixed0_counter0_1_constraint; + } switch (c->idxmsk64 & 0x3ull) { case 0x1: @@ -4563,7 +4616,7 @@ int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu) goto err; } - if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA)) { + if (x86_pmu.flags & (PMU_FL_EXCL_CNTRS | PMU_FL_TFA | PMU_FL_LBR_EVENT)) { size_t sz = X86_PMC_IDX_MAX * sizeof(struct event_constraint); cpuc->constraint_list = kzalloc_node(sz, GFP_KERNEL, cpu_to_node(cpu)); @@ -5535,8 +5588,30 @@ static ssize_t branches_show(struct device *cdev, static DEVICE_ATTR_RO(branches); +static ssize_t branch_counter_nr_show(struct device *cdev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "%d\n", fls(x86_pmu.lbr_events)); +} + +static DEVICE_ATTR_RO(branch_counter_nr); + +static ssize_t branch_counter_width_show(struct device *cdev, + struct device_attribute *attr, + char *buf) +{ + return snprintf(buf, PAGE_SIZE, "2\n"); +} + +static DEVICE_ATTR_RO(branch_counter_width); + + + static struct attribute *lbr_attrs[] = { &dev_attr_branches.attr, + &dev_attr_branch_counter_nr.attr, + &dev_attr_branch_counter_width.attr, NULL }; @@ -5590,7 +5665,11 @@ mem_is_visible(struct kobject *kobj, struct attribute *attr, int i) static umode_t lbr_is_visible(struct kobject *kobj, struct attribute *attr, int i) { - return x86_pmu.lbr_nr ? attr->mode : 0; + /* branches */ + if (i == 0) + return x86_pmu.lbr_nr ? attr->mode : 0; + + return (x86_pmu.flags & PMU_FL_LBR_EVENT) ? attr->mode : 0; } static umode_t diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index cb3f329f8fa4..d49d661ec0a7 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -1912,7 +1912,7 @@ static void setup_pebs_adaptive_sample_data(struct perf_event *event, if (has_branch_stack(event)) { intel_pmu_store_pebs_lbrs(lbr); - perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); + intel_pmu_lbr_save_brstack(data, cpuc, event); } } diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index c3b0d15a9841..1e80a551a4c2 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -676,6 +676,21 @@ void intel_pmu_lbr_del(struct perf_event *event) WARN_ON_ONCE(cpuc->lbr_users < 0); WARN_ON_ONCE(cpuc->lbr_pebs_users < 0); perf_sched_cb_dec(event->pmu); + + /* + * The logged occurrences information is only valid for the + * current LBR group. If another LBR group is scheduled in + * later, the information from the stale LBRs will be wrongly + * interpreted. Reset the LBRs here. + * For the context switch, the LBR will be unconditionally + * flushed when a new task is scheduled in. If both the new task + * and the old task are monitored by a LBR event group. The + * reset here is redundant. But the extra reset doesn't impact + * the functionality. It's hard to distinguish the above case. + * Keep the unconditionally reset for a LBR event group for now. + */ + if (is_branch_counters_group(event)) + intel_pmu_lbr_reset(); } static inline bool vlbr_exclude_host(void) @@ -866,6 +881,18 @@ static __always_inline u16 get_lbr_cycles(u64 info) return cycles; } +static __always_inline void get_lbr_events(struct cpu_hw_events *cpuc, + int i, u64 info) +{ + /* + * The later code will decide what content can be disclosed + * to the perf tool. It's no harmful to unconditionally update + * the cpuc->lbr_events. + * Pleae see intel_pmu_lbr_event_reorder() + */ + cpuc->lbr_events[i] = info & LBR_INFO_EVENTS; +} + static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc, struct lbr_entry *entries) { @@ -898,11 +925,70 @@ static void intel_pmu_store_lbr(struct cpu_hw_events *cpuc, e->abort = !!(info & LBR_INFO_ABORT); e->cycles = get_lbr_cycles(info); e->type = get_lbr_br_type(info); + + get_lbr_events(cpuc, i, info); } cpuc->lbr_stack.nr = i; } +#define ARCH_LBR_EVENT_LOG_WIDTH 2 +#define ARCH_LBR_EVENT_LOG_MASK 0x3 + +static __always_inline void intel_pmu_update_lbr_event(u64 *lbr_events, int idx, int pos) +{ + u64 logs = *lbr_events >> (LBR_INFO_EVENTS_OFFSET + + idx * ARCH_LBR_EVENT_LOG_WIDTH); + + logs &= ARCH_LBR_EVENT_LOG_MASK; + *lbr_events |= logs << (pos * ARCH_LBR_EVENT_LOG_WIDTH); +} + +/* + * The enabled order may be different from the counter order. + * Update the lbr_events with the enabled order. + */ +static void intel_pmu_lbr_event_reorder(struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + int i, j, pos = 0, enabled[X86_PMC_IDX_MAX]; + struct perf_event *leader, *sibling; + + leader = event->group_leader; + if (branch_sample_counters(leader)) + enabled[pos++] = leader->hw.idx; + + for_each_sibling_event(sibling, leader) { + if (!branch_sample_counters(sibling)) + continue; + enabled[pos++] = sibling->hw.idx; + } + + if (!pos) + return; + + for (i = 0; i < cpuc->lbr_stack.nr; i++) { + for (j = 0; j < pos; j++) + intel_pmu_update_lbr_event(&cpuc->lbr_events[i], enabled[j], j); + + /* Clear the original counter order */ + cpuc->lbr_events[i] &= ~LBR_INFO_EVENTS; + } +} + +void intel_pmu_lbr_save_brstack(struct perf_sample_data *data, + struct cpu_hw_events *cpuc, + struct perf_event *event) +{ + if (is_branch_counters_group(event)) { + intel_pmu_lbr_event_reorder(cpuc, event); + perf_sample_save_brstack(data, event, &cpuc->lbr_stack, cpuc->lbr_events); + return; + } + + perf_sample_save_brstack(data, event, &cpuc->lbr_stack, NULL); +} + static void intel_pmu_arch_lbr_read(struct cpu_hw_events *cpuc) { intel_pmu_store_lbr(cpuc, NULL); @@ -1173,8 +1259,10 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc) for (i = 0; i < cpuc->lbr_stack.nr; ) { if (!cpuc->lbr_entries[i].from) { j = i; - while (++j < cpuc->lbr_stack.nr) + while (++j < cpuc->lbr_stack.nr) { cpuc->lbr_entries[j-1] = cpuc->lbr_entries[j]; + cpuc->lbr_events[j-1] = cpuc->lbr_events[j]; + } cpuc->lbr_stack.nr--; if (!cpuc->lbr_entries[i].from) continue; @@ -1525,8 +1613,12 @@ void __init intel_pmu_arch_lbr_init(void) x86_pmu.lbr_mispred = ecx.split.lbr_mispred; x86_pmu.lbr_timed_lbr = ecx.split.lbr_timed_lbr; x86_pmu.lbr_br_type = ecx.split.lbr_br_type; + x86_pmu.lbr_events = ecx.split.lbr_events; x86_pmu.lbr_nr = lbr_nr; + if (!!x86_pmu.lbr_events) + x86_pmu.flags |= PMU_FL_LBR_EVENT; + if (x86_pmu.lbr_mispred) static_branch_enable(&x86_lbr_mispred); if (x86_pmu.lbr_timed_lbr) diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 53dd5d495ba6..4f0722a1be76 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -110,6 +110,11 @@ static inline bool is_topdown_event(struct perf_event *event) return is_metric_event(event) || is_slots_event(event); } +static inline bool is_branch_counters_group(struct perf_event *event) +{ + return event->group_leader->hw.flags & PERF_X86_EVENT_BRANCH_COUNTERS; +} + struct amd_nb { int nb_id; /* NorthBridge id */ int refcnt; /* reference count */ @@ -283,6 +288,7 @@ struct cpu_hw_events { int lbr_pebs_users; struct perf_branch_stack lbr_stack; struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES]; + u64 lbr_events[MAX_LBR_ENTRIES]; /* branch stack extra */ union { struct er_account *lbr_sel; struct er_account *lbr_ctl; @@ -888,6 +894,7 @@ struct x86_pmu { unsigned int lbr_mispred:1; unsigned int lbr_timed_lbr:1; unsigned int lbr_br_type:1; + unsigned int lbr_events:4; void (*lbr_reset)(void); void (*lbr_read)(struct cpu_hw_events *cpuc); @@ -1012,6 +1019,7 @@ do { \ #define PMU_FL_INSTR_LATENCY 0x80 /* Support Instruction Latency in PEBS Memory Info Record */ #define PMU_FL_MEM_LOADS_AUX 0x100 /* Require an auxiliary event for the complete memory info */ #define PMU_FL_RETIRE_LATENCY 0x200 /* Support Retire Latency in PEBS */ +#define PMU_FL_LBR_EVENT 0x400 /* Support LBR event logging */ #define EVENT_VAR(_id) event_attr_##_id #define EVENT_PTR(_id) &event_attr_##_id.attr.attr @@ -1552,6 +1560,10 @@ void intel_pmu_store_pebs_lbrs(struct lbr_entry *lbr); void intel_ds_init(void); +void intel_pmu_lbr_save_brstack(struct perf_sample_data *data, + struct cpu_hw_events *cpuc, + struct perf_event *event); + void intel_pmu_lbr_swap_task_ctx(struct perf_event_pmu_context *prev_epc, struct perf_event_pmu_context *next_epc); diff --git a/arch/x86/events/perf_event_flags.h b/arch/x86/events/perf_event_flags.h index a1685981c520..6c977c19f2cd 100644 --- a/arch/x86/events/perf_event_flags.h +++ b/arch/x86/events/perf_event_flags.h @@ -21,3 +21,4 @@ PERF_ARCH(PEBS_STLAT, 0x08000) /* st+stlat data address sampling */ PERF_ARCH(AMD_BRS, 0x10000) /* AMD Branch Sampling */ PERF_ARCH(PEBS_LAT_HYBRID, 0x20000) /* ld and st lat for hybrid */ PERF_ARCH(NEEDS_BRANCH_STACK, 0x40000) /* require branch stack setup */ +PERF_ARCH(BRANCH_COUNTERS, 0x80000) /* logs the counters in the extra space of each branch */ diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 1d111350197f..7306b70f21ac 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -236,6 +236,8 @@ #define LBR_INFO_CYCLES 0xffff #define LBR_INFO_BR_TYPE_OFFSET 56 #define LBR_INFO_BR_TYPE (0xfull << LBR_INFO_BR_TYPE_OFFSET) +#define LBR_INFO_EVENTS_OFFSET 32 +#define LBR_INFO_EVENTS (0xffull << LBR_INFO_EVENTS_OFFSET) #define MSR_ARCH_LBR_CTL 0x000014ce #define ARCH_LBR_CTL_LBREN BIT(0) diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h index 85a9fd5a3ec3..7677605a39ef 100644 --- a/arch/x86/include/asm/perf_event.h +++ b/arch/x86/include/asm/perf_event.h @@ -31,6 +31,7 @@ #define ARCH_PERFMON_EVENTSEL_ENABLE (1ULL << 22) #define ARCH_PERFMON_EVENTSEL_INV (1ULL << 23) #define ARCH_PERFMON_EVENTSEL_CMASK 0xFF000000ULL +#define ARCH_PERFMON_EVENTSEL_LBR_LOG (1ULL << 35) #define INTEL_FIXED_BITS_MASK 0xFULL #define INTEL_FIXED_BITS_STRIDE 4 @@ -216,6 +217,9 @@ union cpuid28_ecx { unsigned int lbr_timed_lbr:1; /* Branch Type Field Supported */ unsigned int lbr_br_type:1; + unsigned int reserved:13; + /* Event Logging Supported */ + unsigned int lbr_events:4; } split; unsigned int full; }; From patchwork Wed Oct 4 18:40:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148456 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333193vqb; Wed, 4 Oct 2023 11:41:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFduLdganxmtSGe/Fc8rnwpR5Juplu3c4dT54cDJDHpjy3OAnUzH9F2WJgb2H27UDjI4gqi X-Received: by 2002:a17:90b:4d88:b0:277:1bd8:abe1 with SMTP id oj8-20020a17090b4d8800b002771bd8abe1mr2858313pjb.30.1696444897703; Wed, 04 Oct 2023 11:41:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444897; cv=none; d=google.com; s=arc-20160816; b=ScBtxWY7pIVHCXKCxLPLoqhpyTs4Oq1TeyRpJSKRPB7Mtw7pHIqRXB8+91CaoPJzYL L+2KIUVzjMdbSUkmFtRaz558bl6U9DZArLKS0B1gDxQW3IpaAp0KOrCDAbgqBfWO8sVu 3g6xVQHyjw2CJEwTDKGtfSuo+W9OBe2CYPLTLw8IVgaNfGSVI00+RMzRFRtm1I5apeBq MZflE5T9cHNmjlzIhkmmMrlL95jrfSerdig/jhSEaUM1RBxX5o/GDvfwdrtvJn3HDTU7 4xFVdWcH6eBFVwocj1MSuVxoTPq92jTfjMiUhIawbm81wTL+YKApAFVi/flpDipw8mVB n2+Q== ARC-Message-Signature: i=1; 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[23.128.96.35]) by mx.google.com with ESMTPS id i34-20020a17090a3da500b0025c1d114af0si1961779pjc.93.2023.10.04.11.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:41:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=XZoHMN9m; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 9DF7F8062362; Wed, 4 Oct 2023 11:41:28 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243810AbjJDSk5 (ORCPT + 19 others); Wed, 4 Oct 2023 14:40:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243731AbjJDSku (ORCPT ); Wed, 4 Oct 2023 14:40:50 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DA880D8 for ; Wed, 4 Oct 2023 11:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444846; x=1727980846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Y7kvztODIA2R9OyWe64IJ0e/oXjqlzVTL79vhZqnyKg=; b=XZoHMN9mN+fXvk4PbKdvP/4g2ZMBgyHzOneclm01rRAOsLSPIvvEWnxv RneFT9HvO6Mz+jY3K/Mxds6AZvRQ+zwFYjntd/U5OgugX9UP/2B3Ob/zM TU/agsSc8WTJo9vQzGtrrlWQxjkq+t60Trtgc/eNdoW22r8tOM88GYPnU KthNC9pcdJtCttSdUjvL9+QICb7dRnTUXLPJMKKwVTeW2yqssQgYIeZ5I Alw6bC0qPxmDEs39Ru11/Ds76s3EE1pLpiYEjb+mN72shMRwrNj5WQlEo b9BN70e2zNB2UgLZKafiq/iZOrrqOPYL2gyROrdaIHsjd7lIhviDyEpDd g==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537702" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537702" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786626017" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786626017" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:42 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 5/7] tools headers UAPI: Sync include/uapi/linux/perf_event.h header with the kernel Date: Wed, 4 Oct 2023 11:40:42 -0700 Message-Id: <20231004184044.3062788-5-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:41:28 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851404840148951 X-GMAIL-MSGID: 1778851404840148951 From: Kan Liang Sync the new sample type for the branch counters feature. Signed-off-by: Kan Liang --- Changes since V3: - Support PERF_SAMPLE_BRANCH_COUNTERS tools/include/uapi/linux/perf_event.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h index 39c6a250dd1b..4461f380425b 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -204,6 +204,8 @@ enum perf_branch_sample_type_shift { PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT = 18, /* save privilege mode */ + PERF_SAMPLE_BRANCH_COUNTERS_SHIFT = 19, /* save occurrences of events on a branch */ + PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ }; @@ -235,6 +237,8 @@ enum perf_branch_sample_type { PERF_SAMPLE_BRANCH_PRIV_SAVE = 1U << PERF_SAMPLE_BRANCH_PRIV_SAVE_SHIFT, + PERF_SAMPLE_BRANCH_COUNTERS = 1U << PERF_SAMPLE_BRANCH_COUNTERS_SHIFT, + PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, }; @@ -982,6 +986,12 @@ enum perf_event_type { * { u64 nr; * { u64 hw_idx; } && PERF_SAMPLE_BRANCH_HW_INDEX * { u64 from, to, flags } lbr[nr]; + * # + * # The format of the counters is decided by the + * # "branch_counter_nr" and "branch_counter_width", + * # which are defined in the ABI. + * # + * { u64 counters; } cntr[nr] && PERF_SAMPLE_BRANCH_COUNTERS * } && PERF_SAMPLE_BRANCH_STACK * * { u64 abi; # enum perf_sample_regs_abi From patchwork Wed Oct 4 18:40:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148457 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp333199vqb; Wed, 4 Oct 2023 11:41:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEGL3WOplJddypXu6iYQTQV3X/kX0KKvmEF3N/J9trTXY+WSvvvwlgqY8Avakbdi3+0ZjI6 X-Received: by 2002:a05:6358:2491:b0:143:a15f:65d4 with SMTP id m17-20020a056358249100b00143a15f65d4mr2841800rwc.26.1696444897982; Wed, 04 Oct 2023 11:41:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444897; cv=none; d=google.com; s=arc-20160816; b=i5iXpT6LVTSiXk7uqQ8VUQY3Izol9HiITqQC1eel1k4YxUrUwqhV7/xmSV8vXMCL+4 /r38s9Qj6O4hBOKTb/Ga/a+SZxXTp3U1RLj0NVPhS5qLe12951DKC2oklgRhyNqhYVba XaU6p3CnnBeFToBxnUjkT2VBOrsEWDhUd7z4kK+sNI1PkeBMtUqmVktELCFj6Pt8lxdQ tTT5nafxJOzIegsaU4FSJ66XraBkTpCjre4faBmFi2AdlV7TevySplg4EMHSiiYvkDAh 36qDQZboLGGHBsw28smA3/8tKYk++YzFCLUtk/aljPTYL5o+d98eTF+PINGJmPX4RLOW 459g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eWja4n16K9F7kZzu7jWGaflBHS2cF+iWQNmqqM+YUkw=; fh=PWMgxgslqMjOtye8I2qVy8I5pPekyJtpFTusQltnkEg=; b=LTfwZ2Nj4HkahPRAL+TOmLt2QLU26gsNQ4R1tVp+R59Fil81obmuaNQsvuBJUFyQ/v 240MUYuaQV9m+UkH4OqNHHb3Y94MaU95llGcfkIu52Qsjc+aWj4qDuN0b7FACPlHaqgr emGyz89NxxXlyQ3kxy2hcxHQ0PCNDSamr7adBGuK1Zv+0bBiZRo9aG5OmaSqKVTCrhrS X+UtPaXUi7ifF2Z92E9t7ywJZICXQ5g95ZWuAzmQiTDplILv02M+rZWRrendN4h/0HSR 8Ps2zlYgFs4BTMqd3wl9LEhJitOd7/3MMzZoMuTjA0OT0I0Og2qFAg6JDIRzF1X6yvlp ywGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dFugwkXK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id y37-20020a634965000000b00564b99f128dsi4334336pgk.656.2023.10.04.11.41.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:41:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=dFugwkXK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 6DE23802E6ED; Wed, 4 Oct 2023 11:41:17 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244541AbjJDSlD (ORCPT + 19 others); Wed, 4 Oct 2023 14:41:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38406 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244424AbjJDSkv (ORCPT ); Wed, 4 Oct 2023 14:40:51 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE1AEAB for ; Wed, 4 Oct 2023 11:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444847; x=1727980847; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9ryFIqRU8d+k5vrrd/DhvLkz8QtLNCGDdpOoAexf0NM=; b=dFugwkXKFJhBS9nUHccxCylXTkyphj3ZagShiJRVTZd4eOU9mm1cCIhB 3MkrKT0j86wuURnvFwoV7gqxdFH/YqBW8KEVlQLKnouv0hiBiR/LSNWEk WB83CQ57nhcaB3ZmqfjpBxpGAhH6crM5WoiKI/ZmPFKq/SDcT2pqq+4Uq c6/GQYSV6YRjXB0Hxz0ttXnk8oa3/vS+lyGi5IrTtHWtHOye1Lppa/K/N F82+csyhMicOiTBLVgzmYVb6GttyEqYP+I6rlTxLT9Kytm9HqUlhCnnT4 V8Kj8VFskLT3XWL8n0D8/c8VJOtu4rXHfeGh1mFhfLjtnS+/JofIOydNo g==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537709" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537709" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786626031" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786626031" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:43 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 6/7] perf header: Support num and width of branch counters Date: Wed, 4 Oct 2023 11:40:43 -0700 Message-Id: <20231004184044.3062788-6-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:41:17 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851405254025198 X-GMAIL-MSGID: 1778851405254025198 From: Kan Liang To support the branch counters feature, the information of the maximum number of supported counters and the width of the counters is exposed in the sysfs caps folder. The perf tool can use the information to parse the logged counters in each branch. Store the information in the perf_env for later usage. Signed-off-by: Kan Liang --- New patch tools/perf/util/env.h | 5 +++++ tools/perf/util/header.c | 18 +++++++++++++++--- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/tools/perf/util/env.h b/tools/perf/util/env.h index 4566c51f2fd9..48d7f8759a2a 100644 --- a/tools/perf/util/env.h +++ b/tools/perf/util/env.h @@ -46,6 +46,9 @@ struct hybrid_node { struct pmu_caps { int nr_caps; unsigned int max_branches; + unsigned int br_cntr_nr; + unsigned int br_cntr_width; + char **caps; char *pmu_name; }; @@ -62,6 +65,8 @@ struct perf_env { unsigned long long total_mem; unsigned int msr_pmu_type; unsigned int max_branches; + unsigned int br_cntr_nr; + unsigned int br_cntr_width; int kernel_is_64_bit; int nr_cmdline; diff --git a/tools/perf/util/header.c b/tools/perf/util/header.c index d812e1e371a7..9664062ba835 100644 --- a/tools/perf/util/header.c +++ b/tools/perf/util/header.c @@ -3256,7 +3256,9 @@ static int process_compressed(struct feat_fd *ff, } static int __process_pmu_caps(struct feat_fd *ff, int *nr_caps, - char ***caps, unsigned int *max_branches) + char ***caps, unsigned int *max_branches, + unsigned int *br_cntr_nr, + unsigned int *br_cntr_width) { char *name, *value, *ptr; u32 nr_pmu_caps, i; @@ -3291,6 +3293,12 @@ static int __process_pmu_caps(struct feat_fd *ff, int *nr_caps, if (!strcmp(name, "branches")) *max_branches = atoi(value); + if (!strcmp(name, "branch_counter_nr")) + *br_cntr_nr = atoi(value); + + if (!strcmp(name, "branch_counter_width")) + *br_cntr_width = atoi(value); + free(value); free(name); } @@ -3315,7 +3323,9 @@ static int process_cpu_pmu_caps(struct feat_fd *ff, { int ret = __process_pmu_caps(ff, &ff->ph->env.nr_cpu_pmu_caps, &ff->ph->env.cpu_pmu_caps, - &ff->ph->env.max_branches); + &ff->ph->env.max_branches, + &ff->ph->env.br_cntr_nr, + &ff->ph->env.br_cntr_width); if (!ret && !ff->ph->env.cpu_pmu_caps) pr_debug("cpu pmu capabilities not available\n"); @@ -3344,7 +3354,9 @@ static int process_pmu_caps(struct feat_fd *ff, void *data __maybe_unused) for (i = 0; i < nr_pmu; i++) { ret = __process_pmu_caps(ff, &pmu_caps[i].nr_caps, &pmu_caps[i].caps, - &pmu_caps[i].max_branches); + &pmu_caps[i].max_branches, + &pmu_caps[i].br_cntr_nr, + &pmu_caps[i].br_cntr_width); if (ret) goto err; From patchwork Wed Oct 4 18:40:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Liang, Kan" X-Patchwork-Id: 148461 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp334030vqb; Wed, 4 Oct 2023 11:43:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQObE7BUS8GoJHYE7jP41p+lnCiuwqeRnQMpKGa8e4UPO/2UPF8Qqv0ZDlRssBeiAfsM1w X-Received: by 2002:a05:6a00:a18:b0:693:3e55:59b4 with SMTP id p24-20020a056a000a1800b006933e5559b4mr2972061pfh.8.1696444997533; Wed, 04 Oct 2023 11:43:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696444997; cv=none; d=google.com; s=arc-20160816; b=i4M8+4DfIsXoGZOgU7+550QME5oA7HHVWXgwHVEQwoRZso/H/hvXVQ+YbUzgWfJ9hV s7BZ1/5xNdn6O/LFoTg1vyofyOSCxFMuz9Wft2UuWrJXfpbcIBFZbJSTkWZR8ra/quQH cXq8LYmOL4/h/h7KIoy4Z87tQerI8vim1EXVjSFjW5FPmdbKrk8KH17o6Qqua97ongOG vusX8NRN473+QQHWY+DuYomU0guw52V7t5u0pT9gLZk4oBNoNL9FC4PGh2c4zdd1qDiK o3jojgEEYgBD8XXVdjAS21CTF3oIh/KDf0BbDiU7vIB360IU2uyjy0BbIe51alz1JI98 wYSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=E8Zd08wHZVy4JLRn4kBLTx3vtNHmby0zxiMCiyHojIs=; fh=PWMgxgslqMjOtye8I2qVy8I5pPekyJtpFTusQltnkEg=; b=qkkW3RY9WFDts2kXZIkd+eI9hGpS64aVX97Z5VJfYhGPFc436VVxpxOtYhXgO59QVC RhVfBpmBSddcAz/cFF8xHFPrAmVIZsG5EL8aOQja5QlEMy3Yve3JN8lWHPniBzAp57oV CoYowKHxmh0CMdYy1+gHcp9gyTv4f2P37F6Oi14Kw9KKGTrRtO+LyjZzb7ryEsPt5pXn qJCPFP8y7WJR081y/uF8Q8ZaJxqyiMujo5gP2YAmHGU0PU+EZ9vAtfhR27sETtlorjil xg5WW8dS5q5o7KdSQuLL7tkNk5/0R0y28h3KpnpECc8bHxnmIq5vjr/Igjasql7onJkF 3pww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="aHgtyEw/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id e70-20020a636949000000b005855ea4b519si4263383pgc.145.2023.10.04.11.43.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 11:43:17 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="aHgtyEw/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 9901C8130FAF; Wed, 4 Oct 2023 11:43:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S244565AbjJDSlK (ORCPT + 19 others); Wed, 4 Oct 2023 14:41:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S244436AbjJDSkw (ORCPT ); Wed, 4 Oct 2023 14:40:52 -0400 Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E6469AD for ; Wed, 4 Oct 2023 11:40:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1696444848; x=1727980848; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YPCb3UVxzQi3LOX5bsn01xtni3WlRDWfQuY+rkCih3E=; b=aHgtyEw/rIcKFCJhkmjOXwr2T/Q4SZH0nvgKByeWV4SErY+P12JOS1H7 dk9Cw74UOGIH2BU+atPEwpqgKl5cmv56FJ0gvfOFcV7czIOlDsJMaL5ld /IN+Rdz8d8TrCSbVQizrLq8Uq66gd7LUbG5PlNAS/oEOoazsKeg5tePtE SRVB6DWybMZkUA/eF4A8JBBhCiHo5ToCun3XUKQ69wWRu8LagIBCq69YC W5r/EDQn4nsqRWqFo9kjVYj7a+cFYxzTfZK8F8VmRrKofY1gpG5Vth0bK PIJIMf97Lqy4w0TIEaJhDpmM0Bg90ks3wKuNpPa6uiTbQntnMA8SJv6oX Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="469537715" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="469537715" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Oct 2023 11:40:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10853"; a="786626048" X-IronPort-AV: E=Sophos;i="6.03,201,1694761200"; d="scan'208";a="786626048" Received: from kanliang-dev.jf.intel.com ([10.165.154.102]) by orsmga001.jf.intel.com with ESMTP; 04 Oct 2023 11:40:43 -0700 From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@redhat.com, acme@kernel.org, linux-kernel@vger.kernel.org Cc: mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@kernel.org, namhyung@kernel.org, irogers@google.com, adrian.hunter@intel.com, ak@linux.intel.com, eranian@google.com, alexey.v.bayduraev@linux.intel.com, tinghao.zhang@intel.com, Kan Liang Subject: [PATCH V4 7/7] perf tools: Add branch counter knob Date: Wed, 4 Oct 2023 11:40:44 -0700 Message-Id: <20231004184044.3062788-7-kan.liang@linux.intel.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20231004184044.3062788-1-kan.liang@linux.intel.com> References: <20231004184044.3062788-1-kan.liang@linux.intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.8 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 04 Oct 2023 11:43:06 -0700 (PDT) X-Spam-Level: ** X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778851509457793954 X-GMAIL-MSGID: 1778851509457793954 From: Kan Liang Add a new branch filter, "counter", for the branch counter option. It is used to mark the events which should be logged in the branch. If it is applied with the -j option, the counters of all the events should be logged in the branch. If the legacy kernel doesn't support the new branch sample type, switching off the branch counter filter. The stored counter values in each branch are displayed right after the regular branch stack information via perf report -D. Usage examples: perf record -e "{branch-instructions,branch-misses}:S" -j any,counter Only the first event, branch-instructions, collect the LBR. Both branch-instructions and branch-misses are marked as logged events. The occurrences information of them can be found in the branch stack extension space of each branch. perf record -e "{cpu/branch-instructions,branch_type=any/, cpu/branch-misses,branch_type=counter/}" Only the first event, branch-instructions, collect the LBR. Only the branch-misses event is marked as a logged event. Signed-off-by: Kan Liang --- Changes since V3: - Rename the filter name to "counter". - Dump the "branch_counter_nr" and "branch_counter_width" in perf report - Support PERF_SAMPLE_BRANCH_COUNTERS tools/perf/Documentation/perf-record.txt | 4 +++ tools/perf/util/evsel.c | 31 ++++++++++++++++++++++- tools/perf/util/evsel.h | 1 + tools/perf/util/parse-branch-options.c | 1 + tools/perf/util/perf_event_attr_fprintf.c | 1 + tools/perf/util/sample.h | 1 + tools/perf/util/session.c | 15 +++++++++-- 7 files changed, 51 insertions(+), 3 deletions(-) diff --git a/tools/perf/Documentation/perf-record.txt b/tools/perf/Documentation/perf-record.txt index d5217be012d7..b6afe7cc948d 100644 --- a/tools/perf/Documentation/perf-record.txt +++ b/tools/perf/Documentation/perf-record.txt @@ -442,6 +442,10 @@ following filters are defined: 4th-Gen Xeon+ server), the save branch type is unconditionally enabled when the taken branch stack sampling is enabled. - priv: save privilege state during sampling in case binary is not available later + - counter: save occurrences of the event since the last branch entry. Currently, the + feature is only supported by a newer CPU, e.g., Intel Sierra Forest and + later platforms. An error out is expected if it's used on the unsupported + kernel or CPUs. + The option requires at least one branch type among any, any_call, any_ret, ind_call, cond. diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c index a8a5ff87cc1f..58a9b8c82790 100644 --- a/tools/perf/util/evsel.c +++ b/tools/perf/util/evsel.c @@ -1831,6 +1831,8 @@ static int __evsel__prepare_open(struct evsel *evsel, struct perf_cpu_map *cpus, static void evsel__disable_missing_features(struct evsel *evsel) { + if (perf_missing_features.branch_counters) + evsel->core.attr.branch_sample_type &= ~PERF_SAMPLE_BRANCH_COUNTERS; if (perf_missing_features.read_lost) evsel->core.attr.read_format &= ~PERF_FORMAT_LOST; if (perf_missing_features.weight_struct) { @@ -1884,7 +1886,12 @@ bool evsel__detect_missing_features(struct evsel *evsel) * Must probe features in the order they were added to the * perf_event_attr interface. */ - if (!perf_missing_features.read_lost && + if (!perf_missing_features.branch_counters && + (evsel->core.attr.branch_sample_type & PERF_SAMPLE_BRANCH_COUNTERS)) { + perf_missing_features.branch_counters = true; + pr_debug2("switching off branch counters support\n"); + return true; + } else if (!perf_missing_features.read_lost && (evsel->core.attr.read_format & PERF_FORMAT_LOST)) { perf_missing_features.read_lost = true; pr_debug2("switching off PERF_FORMAT_LOST support\n"); @@ -2344,6 +2351,18 @@ u64 evsel__bitfield_swap_branch_flags(u64 value) return new_val; } +static inline bool evsel__has_branch_counters(const struct evsel *evsel) +{ + struct evsel *cur, *leader = evsel__leader(evsel); + + evlist__for_each_entry(evsel->evlist, cur) { + if ((leader == evsel__leader(cur)) && + (cur->core.attr.branch_sample_type & PERF_SAMPLE_BRANCH_COUNTERS)) + return true; + } + return false; +} + int evsel__parse_sample(struct evsel *evsel, union perf_event *event, struct perf_sample *data) { @@ -2577,6 +2596,16 @@ int evsel__parse_sample(struct evsel *evsel, union perf_event *event, OVERFLOW_CHECK(array, sz, max_size); array = (void *)array + sz; + + if (evsel__has_branch_counters(evsel)) { + OVERFLOW_CHECK_u64(array); + + data->branch_stack_cntr = (u64 *)array; + sz = data->branch_stack->nr * sizeof(u64); + + OVERFLOW_CHECK(array, sz, max_size); + array = (void *)array + sz; + } } if (type & PERF_SAMPLE_REGS_USER) { diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h index 848534ec74fa..85f24c986392 100644 --- a/tools/perf/util/evsel.h +++ b/tools/perf/util/evsel.h @@ -191,6 +191,7 @@ struct perf_missing_features { bool code_page_size; bool weight_struct; bool read_lost; + bool branch_counters; }; extern struct perf_missing_features perf_missing_features; diff --git a/tools/perf/util/parse-branch-options.c b/tools/perf/util/parse-branch-options.c index fd67d204d720..f7f7aff3d85a 100644 --- a/tools/perf/util/parse-branch-options.c +++ b/tools/perf/util/parse-branch-options.c @@ -36,6 +36,7 @@ static const struct branch_mode branch_modes[] = { BRANCH_OPT("stack", PERF_SAMPLE_BRANCH_CALL_STACK), BRANCH_OPT("hw_index", PERF_SAMPLE_BRANCH_HW_INDEX), BRANCH_OPT("priv", PERF_SAMPLE_BRANCH_PRIV_SAVE), + BRANCH_OPT("counter", PERF_SAMPLE_BRANCH_COUNTERS), BRANCH_END }; diff --git a/tools/perf/util/perf_event_attr_fprintf.c b/tools/perf/util/perf_event_attr_fprintf.c index 2247991451f3..8f04d3b7f3ec 100644 --- a/tools/perf/util/perf_event_attr_fprintf.c +++ b/tools/perf/util/perf_event_attr_fprintf.c @@ -55,6 +55,7 @@ static void __p_branch_sample_type(char *buf, size_t size, u64 value) bit_name(COND), bit_name(CALL_STACK), bit_name(IND_JUMP), bit_name(CALL), bit_name(NO_FLAGS), bit_name(NO_CYCLES), bit_name(TYPE_SAVE), bit_name(HW_INDEX), bit_name(PRIV_SAVE), + bit_name(COUNTERS), { .name = NULL, } }; #undef bit_name diff --git a/tools/perf/util/sample.h b/tools/perf/util/sample.h index c92ad0f51ecd..70b2c3135555 100644 --- a/tools/perf/util/sample.h +++ b/tools/perf/util/sample.h @@ -113,6 +113,7 @@ struct perf_sample { void *raw_data; struct ip_callchain *callchain; struct branch_stack *branch_stack; + u64 *branch_stack_cntr; struct regs_dump user_regs; struct regs_dump intr_regs; struct stack_dump user_stack; diff --git a/tools/perf/util/session.c b/tools/perf/util/session.c index 1e9aa8ed15b6..4a094ab0362b 100644 --- a/tools/perf/util/session.c +++ b/tools/perf/util/session.c @@ -1150,9 +1150,13 @@ static void callchain__printf(struct evsel *evsel, i, callchain->ips[i]); } -static void branch_stack__printf(struct perf_sample *sample, bool callstack) +static void branch_stack__printf(struct perf_sample *sample, + struct evsel *evsel) { struct branch_entry *entries = perf_sample__branch_entries(sample); + bool callstack = evsel__has_branch_callstack(evsel); + u64 *branch_stack_cntr = sample->branch_stack_cntr; + struct perf_env *env = evsel__env(evsel); uint64_t i; if (!callstack) { @@ -1194,6 +1198,13 @@ static void branch_stack__printf(struct perf_sample *sample, bool callstack) } } } + + if (branch_stack_cntr) { + printf("... branch stack counters: nr:%" PRIu64 " (counter width: %u max counter nr:%u)\n", + sample->branch_stack->nr, env->br_cntr_width, env->br_cntr_nr); + for (i = 0; i < sample->branch_stack->nr; i++) + printf("..... %2"PRIu64": %016" PRIx64 "\n", i, branch_stack_cntr[i]); + } } static void regs_dump__printf(u64 mask, u64 *regs, const char *arch) @@ -1355,7 +1366,7 @@ static void dump_sample(struct evsel *evsel, union perf_event *event, callchain__printf(evsel, sample); if (evsel__has_br_stack(evsel)) - branch_stack__printf(sample, evsel__has_branch_callstack(evsel)); + branch_stack__printf(sample, evsel); if (sample_type & PERF_SAMPLE_REGS_USER) regs_user__printf(sample, arch);