From patchwork Wed Oct 4 15:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148356 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204256vqb; Wed, 4 Oct 2023 08:14:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGrwLePQIJulEaDlnPYZEEakSKWJLjJJ/4Ev6c20L2D8SvsbDEeoZOvoIfYBP1oYxgLBTOc X-Received: by 2002:a17:90a:540e:b0:279:104e:1779 with SMTP id z14-20020a17090a540e00b00279104e1779mr2500009pjh.16.1696432473861; Wed, 04 Oct 2023 08:14:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432473; cv=none; d=google.com; s=arc-20160816; b=Yo3WIgX9OnFr7PvaFbSKMLxnhbTwdtDU03bdXCCOJ1ybUwl6SLQTfCEEaE/aaa1mSi VqLM/KRWHKZx1srWvWJlH0OsdbtscIXvi9qeEWhomYn8fnYZin7uetrR+6NWqb8IPwA9 kMZqpPlMRz5//nyPMz00OEDSirZA1GiKbIqN9WAHgTsZSeCHoooOHdXUrX1LidaPQmF7 u1xtpdR4hk8e18ZGYZ2rWn7u2BfTDaSdaXk87ng+VrENWhF2DjW98zTcCzclObGcqoXP RbHGEHFdDo3iVQyBMNS1Yk4xSzuxiv5CxWlxGNIgaUO0M3Cw95fEe9bO0Rd5xuCpUxzK MzVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=v7cbbMj+E5ZBlob6bJSyN7OfL5gwM5MZRfPIQhkQ9FM=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=TfNDKht2I4A2wb926wkY6ZSa9i51DWv5jIuwTrVfAsTFmmwRWIBX72bjedD4JpLONa 6QXkviAuae+0256O4tN14ZYoWgFk5GchWr3PV3q69YbVnbhgQOjgsHLy2M1Fvp7TrDIb /ZibOQBNH46br1SIjRBCtiXSR9G9rCd12DtbqBFum6z2ExyoPZXbgwUVgIulIDZL+dUY UoKomNJ03qVsLUnPn//L8BF61ORwdtYHUZ7Fip37bljrRt27JEBWsnh3OkeMQi8np+v4 iKVTI3uylBfAa1X3i1U1Kyt0xt74UCpePA2UElLnyjCyRrwkZbugimOSy4pD5N0aGA66 4HJw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=XtVYV0xP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id mz3-20020a17090b378300b002776794a75csi1631222pjb.171.2023.10.04.08.14.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=XtVYV0xP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 32EF282224EF; Wed, 4 Oct 2023 08:14:33 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243119AbjJDPOb (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38520 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233475AbjJDPO3 (ORCPT ); Wed, 4 Oct 2023 11:14:29 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C82ABF for ; Wed, 4 Oct 2023 08:14:25 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-4064e3c7c07so3944325e9.1 for ; Wed, 04 Oct 2023 08:14:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432464; x=1697037264; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=v7cbbMj+E5ZBlob6bJSyN7OfL5gwM5MZRfPIQhkQ9FM=; b=XtVYV0xPiweJ42RdqZW5z23CDvkwCSO1o5sL7FQxS9vwUzsCc+B19wYL/40j3qYfwT LJaiNknfeNFOYgpO2/D3nfaC7u3+mpBnTcmUVNYYOvzMnUO4qqSDnAB5XUkpXLxhS7US xoxQeKvqVkFCS0k/lcWO1yxFvAUe7YXm42CXokxPZEicb2nqZKchRnNBVlM5rdgjz8F0 NtQ5X1nuYruN2QtmqdGfJQfM0KtYZQzOdfj/U4WU6rVLoEP2p/2iWH9hUZgfAhOaBqXU 0IbsX2f+UxIPZ/FcKr9+qPF3dDV9pHP3I52OUZhjRNcnm1I2tTI4WuyEUyAoVJZHrhhh ti1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432464; x=1697037264; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=v7cbbMj+E5ZBlob6bJSyN7OfL5gwM5MZRfPIQhkQ9FM=; b=r43ciMF4Dar/kwoR/CZsHNul9c3sUTlkz3j8MlR18cKvi4mEkS5Lge5calmKpu+t/U bCEHVxXJHmq5iXhN4ziAOtaTvsuqS8kmG+HVeq87A1OZQAF+/voXkjOOkTkIfsW8aKCG wjkAPlAwzxZnwBUGDAd/P6jbM7GpK4ssvRVvJmTNLZQ5ttPrdJlmlexd/kO5QvuD68Xs rcmue2gp0a/PxeOArhz8Jefnm5bQXCjnWnT3LKDTq1ggmBKAPmxWSkNKLzP7gkUPnyRV xIfhHRAy15oo1SLIvNu83gtZrmGA7MsGGwjBZ7auRvtE0caevytmxTmxr5uQCTH6grtS 7NcQ== X-Gm-Message-State: AOJu0YzCYOkLbB9uTZ8QQMf4vymZ1FnccbhZXnD7FAaegZ0xzQPDZZmI ZL4pQ6fkuIKEe8SOhBQC9kCndA== X-Received: by 2002:a05:600c:510b:b0:404:75cc:62e6 with SMTP id o11-20020a05600c510b00b0040475cc62e6mr2495282wms.3.1696432464039; Wed, 04 Oct 2023 08:14:24 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:23 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 1/8] riscv: remove unused functions in traps_misaligned.c Date: Wed, 4 Oct 2023 17:13:58 +0200 Message-ID: <20231004151405.521596-2-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838377453058809 X-GMAIL-MSGID: 1778838377453058809 Replace macros by the only two function calls that are done from this file, store_u8() and load_u8(). Signed-off-by: Clément Léger --- arch/riscv/kernel/traps_misaligned.c | 46 +++++----------------------- 1 file changed, 7 insertions(+), 39 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 378f5b151443..e7bfb33089c1 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -151,51 +151,19 @@ #define PRECISION_S 0 #define PRECISION_D 1 -#define DECLARE_UNPRIVILEGED_LOAD_FUNCTION(type, insn) \ -static inline type load_##type(const type *addr) \ -{ \ - type val; \ - asm (#insn " %0, %1" \ - : "=&r" (val) : "m" (*addr)); \ - return val; \ -} +static inline u8 load_u8(const u8 *addr) +{ + u8 val; -#define DECLARE_UNPRIVILEGED_STORE_FUNCTION(type, insn) \ -static inline void store_##type(type *addr, type val) \ -{ \ - asm volatile (#insn " %0, %1\n" \ - : : "r" (val), "m" (*addr)); \ -} + asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr)); -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u8, lbu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u16, lhu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s8, lb) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s16, lh) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(s32, lw) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u8, sb) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u16, sh) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u32, sw) -#if defined(CONFIG_64BIT) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lwu) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u64, ld) -DECLARE_UNPRIVILEGED_STORE_FUNCTION(u64, sd) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, ld) -#else -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(u32, lw) -DECLARE_UNPRIVILEGED_LOAD_FUNCTION(ulong, lw) - -static inline u64 load_u64(const u64 *addr) -{ - return load_u32((u32 *)addr) - + ((u64)load_u32((u32 *)addr + 1) << 32); + return val; } -static inline void store_u64(u64 *addr, u64 val) +static inline void store_u8(u8 *addr, u8 val) { - store_u32((u32 *)addr, val); - store_u32((u32 *)addr + 1, val >> 32); + asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); } -#endif static inline ulong get_insn(ulong mepc) { From patchwork Wed Oct 4 15:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148362 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp205263vqb; Wed, 4 Oct 2023 08:15:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGec7pRs2nOTFYjhlFmXTBCZuEfFthaLLeZdBb14gO/WnVzZrJ7PY6fEw50dHAbFzK1EEkf X-Received: by 2002:a17:903:32cb:b0:1c5:ea60:85c5 with SMTP id i11-20020a17090332cb00b001c5ea6085c5mr2936924plr.2.1696432549864; Wed, 04 Oct 2023 08:15:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432549; cv=none; d=google.com; s=arc-20160816; b=fDBC4xYs83TJRdaVH3g1vPZJHvUtkfa0r2G7v3mMu2Mm+5tBvcLfvXal9ip3wTCL7Z D+vNWvETuMntPp+WrqjfXWZOFk9hdEBF5LS36ekn8nxSWWJwJXeJ5bdzOUIiJw7HYiLT jrod6bsa0NtpgsW2ExBwuO0hu0T43dk0HjLSUFOYFSqrorWTzSLkjvCtShIZKqiGkEHS QipTT1BIVl3sI7N//UVUUYfJzkmZgMqMnuStM4swrB1PgJyQGNGLZtjTxyxYDgOfzqyd TsShSDaJ509CfXToh+TJQgHf9ouUjTK/onMfYOUnqU/M9F8S818gCyWl2UvjkqfjOeZF jt+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=H1p2iCt2/GYKYHhTcUS5xXMpXi+9mCsK1NUx+ndGvU8=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=YH3rcSPLZX+obFp169/nVghw0It1gABDgzCCVkOiGtdWIsj8INyj+JO7+6U8nKECxY KKI1Dza7g/0hhp7nQHgT2NMhb7NZN+jPCh/zA62WLZblJMypV/X/HAyzArXgV5J228QE fM6DA6VY/v2T1r6ZlYHHG6MgDT8xZ1FdwZXX6II6Jh5RiXOK1wIDs91KDXDnyiGDUDKn BqqkYd07HvLNkV9R7VAYxTd84Ko1bBeVFiIReg8bHkybgBZwYZyqOmU6IpyyPf5SOGMt As8MMJLkMWcZ/I9M5vVHO4hKjOMJ/q9akMVL7nMqlubTFXCx/dssHtfARxrlqbJvjYt4 l38w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=tTVlpor7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id d10-20020a170902654a00b001c5f5153e41si3761789pln.535.2023.10.04.08.15.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:15:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=tTVlpor7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 8454B81A0587; Wed, 4 Oct 2023 08:14:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243114AbjJDPOe (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243117AbjJDPOb (ORCPT ); Wed, 4 Oct 2023 11:14:31 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 908C9C1 for ; Wed, 4 Oct 2023 08:14:26 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-406553f6976so5071355e9.1 for ; Wed, 04 Oct 2023 08:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432465; x=1697037265; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H1p2iCt2/GYKYHhTcUS5xXMpXi+9mCsK1NUx+ndGvU8=; b=tTVlpor7EJV43VmFSuEcBU6nOke2BticJbENRLmlCZ6mT1O+HBIAzY1z5gJ2oEQUN4 PxkY+dqIosMPgFx36Q13I761mcCOIz+ANh6eQ45SItNucEwyj05LevhS8yt3xqxd1yIi bF06KPin5LajWfkepTzP7JrHv7op2ZZZNeEOmiYnRf/2etSFRMoQQ7eUdUXyIJk9x1Va uNtiEHFXexgFg8u/XK+8dfqaMhwzIdT1RHh9EVLxa8oFURXBNVQMUXo7It1ii0WCvRzq 8vG3L1MJiSHebaW5EqSsSjTuDPD6EElfLDpi/jg/vd5gt30TsrfF6jGeYv5evywpfb9+ hvNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432465; x=1697037265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H1p2iCt2/GYKYHhTcUS5xXMpXi+9mCsK1NUx+ndGvU8=; b=olMq3g6QxSwP/9xLgAH1uIEDPjLqCwLSt+7VUVTpgeaGDZxeypT/G1XNO/PMbhySbm p4PnaLeqqZXHh9xdoDhiT797sHMZPFljZjGDJN6eIR7sbWLicg3EQgy0OmUl5nYTp+ve HIZ4Td3vbYfr8rOAXBxbMxyLq6t48Qrr8RGDG18aYpU15DiUygRn1hHQ8zIn1jRzjK3P a2TVF4Kc+J3MfWWFs3GGObXOzxz0atHqgUYAd6XnvlzlTaMjKipbbfHQxCWqly+SOnVW 7CvLXbi/9eFal5SHbdQvVXtbnjFa0qaNGAsCsJl9ZzPvoEmiuBbQ6A05sZ4S2enuuGyT PRcA== X-Gm-Message-State: AOJu0YzRlGb6MJ1IPSDR51IPh4ZEBVMAwNCyBQBHPdXX0VeKM1sgsrg3 I1VLu17Y0gN0aVKd5EPy3q/uTw== X-Received: by 2002:a05:600c:5114:b0:405:4127:f471 with SMTP id o20-20020a05600c511400b004054127f471mr2631811wms.1.1696432465062; Wed, 04 Oct 2023 08:14:25 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:24 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 2/8] riscv: add support for misaligned trap handling in S-mode Date: Wed, 4 Oct 2023 17:13:59 +0200 Message-ID: <20231004151405.521596-3-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838457221796401 X-GMAIL-MSGID: 1778838457221796401 Misalignment trap handling is only supported for M-mode and uses direct accesses to user memory. In S-mode, when handling usermode fault, this requires to use the get_user()/put_user() accessors. Implement load_u8(), store_u8() and get_insn() using these accessors for userspace and direct text access for kernel. Signed-off-by: Clément Léger Reviewed-by: Björn Töpel --- arch/riscv/Kconfig | 8 ++ arch/riscv/include/asm/entry-common.h | 14 +++ arch/riscv/kernel/Makefile | 2 +- arch/riscv/kernel/traps.c | 9 -- arch/riscv/kernel/traps_misaligned.c | 119 +++++++++++++++++++++++--- 5 files changed, 129 insertions(+), 23 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..6e167358a897 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -636,6 +636,14 @@ config THREAD_SIZE_ORDER Specify the Pages of thread stack size (from 4KB to 64KB), which also affects irq stack size, which is equal to thread stack size. +config RISCV_MISALIGNED + bool "Support misaligned load/store traps for kernel and userspace" + default y + help + Say Y here if you want the kernel to embed support for misaligned + load/store for both kernel and userspace. When disable, misaligned + accesses will generate SIGBUS in userspace and panic in kernel. + endmenu # "Platform type" menu "Kernel features" diff --git a/arch/riscv/include/asm/entry-common.h b/arch/riscv/include/asm/entry-common.h index 6e4dee49d84b..7ab5e34318c8 100644 --- a/arch/riscv/include/asm/entry-common.h +++ b/arch/riscv/include/asm/entry-common.h @@ -8,4 +8,18 @@ void handle_page_fault(struct pt_regs *regs); void handle_break(struct pt_regs *regs); +#ifdef CONFIG_RISCV_MISALIGNED +int handle_misaligned_load(struct pt_regs *regs); +int handle_misaligned_store(struct pt_regs *regs); +#else +static inline int handle_misaligned_load(struct pt_regs *regs) +{ + return -1; +} +static inline int handle_misaligned_store(struct pt_regs *regs) +{ + return -1; +} +#endif + #endif /* _ASM_RISCV_ENTRY_COMMON_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index 95cf25d48405..0d874fb24b51 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -59,7 +59,7 @@ obj-y += patch.o obj-y += probes/ obj-$(CONFIG_MMU) += vdso.o vdso/ -obj-$(CONFIG_RISCV_M_MODE) += traps_misaligned.o +obj-$(CONFIG_RISCV_MISALIGNED) += traps_misaligned.o obj-$(CONFIG_FPU) += fpu.o obj-$(CONFIG_RISCV_ISA_V) += vector.o obj-$(CONFIG_SMP) += smpboot.o diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 19807c4d3805..d69779e4b967 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -179,14 +179,6 @@ asmlinkage __visible __trap_section void do_trap_insn_illegal(struct pt_regs *re DO_ERROR_INFO(do_trap_load_fault, SIGSEGV, SEGV_ACCERR, "load access fault"); -#ifndef CONFIG_RISCV_M_MODE -DO_ERROR_INFO(do_trap_load_misaligned, - SIGBUS, BUS_ADRALN, "Oops - load address misaligned"); -DO_ERROR_INFO(do_trap_store_misaligned, - SIGBUS, BUS_ADRALN, "Oops - store (or AMO) address misaligned"); -#else -int handle_misaligned_load(struct pt_regs *regs); -int handle_misaligned_store(struct pt_regs *regs); asmlinkage __visible __trap_section void do_trap_load_misaligned(struct pt_regs *regs) { @@ -229,7 +221,6 @@ asmlinkage __visible __trap_section void do_trap_store_misaligned(struct pt_regs irqentry_nmi_exit(regs, state); } } -#endif DO_ERROR_INFO(do_trap_store_fault, SIGSEGV, SEGV_ACCERR, "store (or AMO) access fault"); DO_ERROR_INFO(do_trap_ecall_s, diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index e7bfb33089c1..9daed7d756ae 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -12,6 +12,7 @@ #include #include #include +#include #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -151,21 +152,25 @@ #define PRECISION_S 0 #define PRECISION_D 1 -static inline u8 load_u8(const u8 *addr) +#ifdef CONFIG_RISCV_M_MODE +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { u8 val; asm volatile("lbu %0, %1" : "=&r" (val) : "m" (*addr)); + *r_val = val; - return val; + return 0; } -static inline void store_u8(u8 *addr, u8 val) +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) { asm volatile ("sb %0, %1\n" : : "r" (val), "m" (*addr)); + + return 0; } -static inline ulong get_insn(ulong mepc) +static inline int get_insn(struct pt_regs *regs, ulong mepc, ulong *r_insn) { register ulong __mepc asm ("a2") = mepc; ulong val, rvc_mask = 3, tmp; @@ -194,9 +199,87 @@ static inline ulong get_insn(ulong mepc) : [addr] "r" (__mepc), [rvc_mask] "r" (rvc_mask), [xlen_minus_16] "i" (XLEN_MINUS_16)); - return val; + *r_insn = val; + + return 0; +} +#else +static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) +{ + if (user_mode(regs)) { + return __get_user(*r_val, addr); + } else { + *r_val = *addr; + return 0; + } } +static inline int store_u8(struct pt_regs *regs, u8 *addr, u8 val) +{ + if (user_mode(regs)) { + return __put_user(val, addr); + } else { + *addr = val; + return 0; + } +} + +#define __read_insn(regs, insn, insn_addr) \ +({ \ + int __ret; \ + \ + if (user_mode(regs)) { \ + __ret = __get_user(insn, insn_addr); \ + } else { \ + insn = *insn_addr; \ + __ret = 0; \ + } \ + \ + __ret; \ +}) + +static inline int get_insn(struct pt_regs *regs, ulong epc, ulong *r_insn) +{ + ulong insn = 0; + + if (epc & 0x2) { + ulong tmp = 0; + u16 __user *insn_addr = (u16 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + /* __get_user() uses regular "lw" which sign extend the loaded + * value make sure to clear higher order bits in case we "or" it + * below with the upper 16 bits half. + */ + insn &= GENMASK(15, 0); + if ((insn & __INSN_LENGTH_MASK) != __INSN_LENGTH_32) { + *r_insn = insn; + return 0; + } + insn_addr++; + if (__read_insn(regs, tmp, insn_addr)) + return -EFAULT; + *r_insn = (tmp << 16) | insn; + + return 0; + } else { + u32 __user *insn_addr = (u32 __user *)epc; + + if (__read_insn(regs, insn, insn_addr)) + return -EFAULT; + if ((insn & __INSN_LENGTH_MASK) == __INSN_LENGTH_32) { + *r_insn = insn; + return 0; + } + insn &= GENMASK(15, 0); + *r_insn = insn; + + return 0; + } +} +#endif + union reg_data { u8 data_bytes[8]; ulong data_ulong; @@ -207,10 +290,13 @@ int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; unsigned long epc = regs->epc; - unsigned long insn = get_insn(epc); - unsigned long addr = csr_read(mtval); + unsigned long insn; + unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + if (get_insn(regs, epc, &insn)) + return -1; + regs->epc = 0; if ((insn & INSN_MASK_LW) == INSN_MATCH_LW) { @@ -274,8 +360,10 @@ int handle_misaligned_load(struct pt_regs *regs) } val.data_u64 = 0; - for (i = 0; i < len; i++) - val.data_bytes[i] = load_u8((void *)(addr + i)); + for (i = 0; i < len; i++) { + if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) + return -1; + } if (fp) return -1; @@ -290,10 +378,13 @@ int handle_misaligned_store(struct pt_regs *regs) { union reg_data val; unsigned long epc = regs->epc; - unsigned long insn = get_insn(epc); - unsigned long addr = csr_read(mtval); + unsigned long insn; + unsigned long addr = regs->badaddr; int i, len = 0; + if (get_insn(regs, epc, &insn)) + return -1; + regs->epc = 0; val.data_ulong = GET_RS2(insn, regs); @@ -327,8 +418,10 @@ int handle_misaligned_store(struct pt_regs *regs) return -1; } - for (i = 0; i < len; i++) - store_u8((void *)(addr + i), val.data_bytes[i]); + for (i = 0; i < len; i++) { + if (store_u8(regs, (void *)(addr + i), val.data_bytes[i])) + return -1; + } regs->epc = epc + INSN_LEN(insn); From patchwork Wed Oct 4 15:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148357 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204365vqb; Wed, 4 Oct 2023 08:14:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFZgvVv7+aSSNOxp0wk74N9V/7MgcC6wrJnZnuygO6lzXojaGRRHRPv2fpPgnYBin/LLxJ1 X-Received: by 2002:a17:903:1245:b0:1c4:4dbc:92bc with SMTP id u5-20020a170903124500b001c44dbc92bcmr3066521plh.16.1696432482646; Wed, 04 Oct 2023 08:14:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432482; cv=none; d=google.com; s=arc-20160816; b=Nb+d4WfnqOxc4ejY9C23DuRnWpu8bmVcBcpCc/JCczkC0d8dpT6cQA0buNA0z5hPK1 cedfc1bkjKvdOAJP9h3rLofCztL27AD1Y+nWBYcXRxYdp7flWPvgYTAEQuJlpYNBoCZ6 b+KwWSUYoU+J1uYUwNl7lBG7J+2gbnQZOdJ779vl4dyDDdJzcqQRQq19V3HmJcidm+qG ufjvrCvW9uk4yj/Gya17+Q3Wu/LmeRvIIn6fvVo+b+XAhS1MM5A174HwITtXL0tRphnF D0FSjzmdFIei3q0NmXgcF0mxdJxC1nHpCNA0KT3ieP6wZFzPZWjuOuuTVyMJIqJFn+JL yysw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=A29BZTVXLOLIyIz1ohc6hcIwjz2FYyV3nDH2JWKPVDg=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=0JLLJ449AeRSWWs1einjzbh0YFTvOEVKYcIxOyqUytZSx2CjpZdCuHIYyRQSpU9O5B VlYYgEu3WBlPRDumdqJXdXZaccKOj6vvfGDbgO6mHsK14PbdJh0r7rUmJL8s7lMX2XeE V5htutJS/ODpoViMRue2Vz4qfzbHN3ZL8gmiuS17vnxIdVWo7uCgkHuC8NLDwFEbygnT cncYVatXoAR7HsrVyAR81iV4/+I4Zq9+FF1hwZpc1ig0gFEPXfrDwpyJHgX4AIk3Ya83 DDUn/rYu1cgKFNLkqAmt39tfXglwTsmfQQx1e47qWCIAoDFOpHpntK6M/Nah5PZsdObT gJnA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=038fOEJ7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id j21-20020a170902c3d500b001b3bd85f54bsi3759576plj.35.2023.10.04.08.14.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=038fOEJ7; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id D39D8836E5D5; Wed, 4 Oct 2023 08:14:41 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243141AbjJDPOh (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38572 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243103AbjJDPOb (ORCPT ); Wed, 4 Oct 2023 11:14:31 -0400 Received: from mail-wm1-x32a.google.com (mail-wm1-x32a.google.com [IPv6:2a00:1450:4864:20::32a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F06BBF for ; Wed, 4 Oct 2023 08:14:27 -0700 (PDT) Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-40651b22977so4786545e9.1 for ; Wed, 04 Oct 2023 08:14:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432466; x=1697037266; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=A29BZTVXLOLIyIz1ohc6hcIwjz2FYyV3nDH2JWKPVDg=; b=038fOEJ7sMKpTNos3DP4JF9BjrQ0B1hvj3xVwgi210QNblv0DcTlVsUii8uxv7sw8u PoGZ/QiffIshotB255I0FB8ncOZbx73LVaM73MLfrArkam3vK79CJjatl+xLzwyLSwgv Fz+GGNEYh+IXyey6noexJEx27YXvqi4NfcQ3/jS4nIuokAM163tJoM93WiURJX2GT0ku +VuwvpPH/7PYmYLz+5JoAikFweIOKYCRBNg5QQYSub5RaLd3YJBDkUstxXprK3T9oJl+ QvWUYnOP2F3/yHSo1QiOCWu2hat4+E48gwqJ280EW8eMjmr4AwY4S2l9OQtiXR3yDBf5 OAqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432466; x=1697037266; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=A29BZTVXLOLIyIz1ohc6hcIwjz2FYyV3nDH2JWKPVDg=; b=XjpwtYIJjDl3ewq6ro9z2n59B05Iq2N9KkdK2j4Ys6yfktKs8Y/A2uTtrpT7Lmyhl9 1kBYrfQ6eNSKtOH2jniVNFc1eeAYLMKoHpB1/ph8xXvHvkD3ItxvAii+pHnv3rEBPT+v Q7OgoX1Y3fkuHAovfkZRjn32aNHoo2MF/RxvQkpMsR4GtI/3mA/cV0PptNj7ZkUvIjfH OaNBQCw1AWiy3qHksUWE/7FnzE7O/99eDiAnpi/kcSUmqtc1jE3MO0iAJgRduDzYCTWL HTtHEZh986PlZMSCu9rjIuAA2fGD1UtsrN/3XeAmZMldgiC+WFAkEBUQtC5eVNhKQ4Lb z/Xg== X-Gm-Message-State: AOJu0YzBjVguGZdiKBy+EWD5Vt/xItXDI//WI8SDNciyaNYRtN0Z5wSg rFR0LPM6ygTExqYPWoQGsmTOzw== X-Received: by 2002:a05:600c:3c96:b0:403:334:fb0d with SMTP id bg22-20020a05600c3c9600b004030334fb0dmr2534922wmb.4.1696432466012; Wed, 04 Oct 2023 08:14:26 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:25 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 3/8] riscv: report perf event for misaligned fault Date: Wed, 4 Oct 2023 17:14:00 +0200 Message-ID: <20231004151405.521596-4-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:41 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838386696330652 X-GMAIL-MSGID: 1778838386696330652 Add missing calls to account for misaligned fault event using perf_sw_event(). Signed-off-by: Clément Léger Reviewed-by: Björn Töpel --- arch/riscv/kernel/traps_misaligned.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 9daed7d756ae..804f6c5e0e44 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, fp = 0, shift = 0, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; @@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long addr = regs->badaddr; int i, len = 0; + perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (get_insn(regs, epc, &insn)) return -1; From patchwork Wed Oct 4 15:14:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148358 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204425vqb; Wed, 4 Oct 2023 08:14:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH5nhxwARqAfw3qgWDxfdf8aLDNM/bTpqq4kW+zagLb6jBaOdW1rUKZQxDqg8jr7TaeEcFX X-Received: by 2002:a05:6a21:a592:b0:151:35ad:f331 with SMTP id gd18-20020a056a21a59200b0015135adf331mr3927230pzc.14.1696432487405; Wed, 04 Oct 2023 08:14:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432487; cv=none; d=google.com; s=arc-20160816; b=cILbj3d+7XGls/+7Qn5lHFLnvLT4X0fZON0k+tzpUpoFFL8uaiqgioRG08uqGlI4Q6 CFsOyNtA7CC6YJIJ3IY/b+Sp6OEnoytiHw6IJa3YreE9il43Bpe50sfk1WFSGEcXVAsW Ib2XxLWr3jJZTJ4MAwyqw/lrJx2QJA1iKuMeFH/OAiqSmwVdCzY6uRgGBmYMaVzxbzJZ phlnF/SkTCKGbkIohsiMp14US6TDGdd2PV9O7PMoXTU3zfDNznjOvwXGx1EKtVG4rh81 enbbB5x4jYgDqAueW8aJOX7RB3U1KSh3zKpfxXNFhpWCG1G1wRH71aTN+gpoFAgpTEXa lXQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=9TwKTwL0wrE/m4MYxnp0A1rNn2Nx0VOs6dVs63l3gfI=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=IqkR/0aw5cyiZgmkTAzOwPSUclnJYGED2Qmonu+KEFNuPA3bzg2T7KmL+DLjtaqG4H TdU5XEZ7CPNJQUhaHlxvzFdRb4vLnApF4M/vHbOdCIxj/uGKf5A98AZyKn7pIRa9GsLv PSiGxGBt8LhUgFcfVqlUZZA/O1oPz/oqeCnKO1HD2xp7p/UvBed0wS71R+68i5tJG2N7 LE3lgb9O7z5Niz6tf2bjfrXTMA65upANvGGHLP+FgXw6HkDvB1rSgKU+NI5cAhzh/f7+ GLZkKDRFg67hidl0fbnxzhl7yL1adtniBhm98CFPd0pDfLesCCEyMJCAb3ySkaXVTeyB 3Erw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=SXyVfnec; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id a18-20020a056a000c9200b0069347c30c86si4115994pfv.253.2023.10.04.08.14.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=SXyVfnec; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 4CC6A822CE1C; Wed, 4 Oct 2023 08:14:46 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243173AbjJDPOk (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233475AbjJDPOd (ORCPT ); Wed, 4 Oct 2023 11:14:33 -0400 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [IPv6:2a00:1450:4864:20::32f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6195593 for ; Wed, 4 Oct 2023 08:14:29 -0700 (PDT) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-406532c49dcso5077035e9.0 for ; Wed, 04 Oct 2023 08:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432468; x=1697037268; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9TwKTwL0wrE/m4MYxnp0A1rNn2Nx0VOs6dVs63l3gfI=; b=SXyVfnecvsoPTJjVsHDLlvkUCHELyiVimiU37h0b5GbTefXjpur9cXvcG9zt4tTUs2 t0XTkLCY8B6D7sQx8eos8u/XGC3UHqmk7p3yIgVlAuuMYy2F1/ixgmpSXhS2Hqmv2H45 7Sntu5ivSkmHAyPQlliMTMXZIWYsPEQaeWndhNAexPfAiq8KpqBE9K7vnaOzyDO7tgfz 7sm8z4Kam/PWWIfh4X8b0AkEr8m8GqGy4aVi11j3pf/qjLQwy9hWXUiSJSaFbI8GvihI 22MuwuO5jZ5V1NKMb0ejOKPwB90GfJ5X3RvqVxueLfcgG0sr3WPRRFQBihlaBnK6pSrY 27iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432468; x=1697037268; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9TwKTwL0wrE/m4MYxnp0A1rNn2Nx0VOs6dVs63l3gfI=; b=rvXfi3CDpMUcZC6Oi9eD2mG0asAxvEBCniao2+OqB1lKmHNXuVfogib/YKWeHbUkzs XcnaFeHd27+xUK57700wH6g88TETAw3U3Ql4WN4ySfRsvcuZav9Ayj+PxwiVjRUqb1dh bARmeksEnaPujRqdozZeKBjYwqF3o+6D8hZA2B+/yAkw7yD5TbRDcJcYHdunyZdZ7bnO 9sICC5b1o3BB8ySrpU5+TFsiEPWxXEa84O+lD9kBZ50N7WMnKxvyMJq4qTmju3L4z9Tj eDwyELm4LV/u3ekPxPQfYk108rLfgKyLAPhUCGvpJk2pZ+QAzbTeDGxbM9ljPpgJlWNI EYBA== X-Gm-Message-State: AOJu0YyuXjjZ+1Mw2Y1i8qfmZAHEY1zsZP6PNjQueE27RYxg+Q6RTIry Ft2iroC5x2nn3Zyz1S2ciLGSsw== X-Received: by 2002:a7b:ca59:0:b0:3fe:d637:7b25 with SMTP id m25-20020a7bca59000000b003fed6377b25mr2665689wml.0.1696432466983; Wed, 04 Oct 2023 08:14:26 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:26 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 4/8] riscv: add floating point insn support to misaligned access emulation Date: Wed, 4 Oct 2023 17:14:01 +0200 Message-ID: <20231004151405.521596-5-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838391473865869 X-GMAIL-MSGID: 1778838391473865869 This support is partially based of openSBI misaligned emulation floating point instruction support. It provides support for the existing floating point instructions (both for 32/64 bits as well as compressed ones). Since floating point registers are not part of the pt_regs struct, we need to modify them directly using some assembly. We also dirty the pt_regs status in case we modify them to be sure context switch will save FP state. With this support, Linux is on par with openSBI support. Signed-off-by: Clément Léger --- arch/riscv/kernel/fpu.S | 121 +++++++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 152 ++++++++++++++++++++++++++- 2 files changed, 269 insertions(+), 4 deletions(-) diff --git a/arch/riscv/kernel/fpu.S b/arch/riscv/kernel/fpu.S index dd2205473de7..5dd3161a4dac 100644 --- a/arch/riscv/kernel/fpu.S +++ b/arch/riscv/kernel/fpu.S @@ -104,3 +104,124 @@ ENTRY(__fstate_restore) csrc CSR_STATUS, t1 ret ENDPROC(__fstate_restore) + +#define get_f32(which) fmv.x.s a0, which; j 2f +#define put_f32(which) fmv.s.x which, a1; j 2f +#if __riscv_xlen == 64 +# define get_f64(which) fmv.x.d a0, which; j 2f +# define put_f64(which) fmv.d.x which, a1; j 2f +#else +# define get_f64(which) fsd which, 0(a1); j 2f +# define put_f64(which) fld which, 0(a1); j 2f +#endif + +.macro fp_access_prologue + /* + * Compute jump offset to store the correct FP register since we don't + * have indirect FP register access + */ + sll t0, a0, 3 + la t2, 1f + add t0, t0, t2 + li t1, SR_FS + csrs CSR_STATUS, t1 + jr t0 +1: +.endm + +.macro fp_access_epilogue +2: + csrc CSR_STATUS, t1 + ret +.endm + +#define fp_access_body(__access_func) \ + __access_func(f0); \ + __access_func(f1); \ + __access_func(f2); \ + __access_func(f3); \ + __access_func(f4); \ + __access_func(f5); \ + __access_func(f6); \ + __access_func(f7); \ + __access_func(f8); \ + __access_func(f9); \ + __access_func(f10); \ + __access_func(f11); \ + __access_func(f12); \ + __access_func(f13); \ + __access_func(f14); \ + __access_func(f15); \ + __access_func(f16); \ + __access_func(f17); \ + __access_func(f18); \ + __access_func(f19); \ + __access_func(f20); \ + __access_func(f21); \ + __access_func(f22); \ + __access_func(f23); \ + __access_func(f24); \ + __access_func(f25); \ + __access_func(f26); \ + __access_func(f27); \ + __access_func(f28); \ + __access_func(f29); \ + __access_func(f30); \ + __access_func(f31) + + +#ifdef CONFIG_RISCV_MISALIGNED + +/* + * Disable compressed instructions set to keep a constant offset between FP + * load/store/move instructions + */ +.option norvc +/* + * put_f32_reg - Set a FP register from a register containing the value + * a0 = FP register index to be set + * a1 = value to be loaded in the FP register + */ +SYM_FUNC_START(put_f32_reg) + fp_access_prologue + fp_access_body(put_f32) + fp_access_epilogue +SYM_FUNC_END(put_f32_reg) + +/* + * get_f32_reg - Get a FP register value and return it + * a0 = FP register index to be retrieved + */ +SYM_FUNC_START(get_f32_reg) + fp_access_prologue + fp_access_body(get_f32) + fp_access_epilogue +SYM_FUNC_END(get_f32_reg) + +/* + * put_f64_reg - Set a 64 bits FP register from a value or a pointer. + * a0 = FP register index to be set + * a1 = value/pointer to be loaded in the FP register (when xlen == 32 bits, we + * load the value to a pointer). + */ +SYM_FUNC_START(put_f64_reg) + fp_access_prologue + fp_access_body(put_f64) + fp_access_epilogue +SYM_FUNC_END(put_f64_reg) + +/* + * put_f64_reg - Get a 64 bits FP register value and returned it or store it to + * a pointer. + * a0 = FP register index to be retrieved + * a1 = If xlen == 32, pointer which should be loaded with the FP register value + * or unused if xlen == 64. In which case the FP register value is returned + * through a0 + */ +SYM_FUNC_START(get_f64_reg) + fp_access_prologue + fp_access_body(get_f64) + fp_access_epilogue +SYM_FUNC_END(get_f64_reg) + +#endif /* CONFIG_RISCV_MISALIGNED */ diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 804f6c5e0e44..041fd2dbd955 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -153,6 +153,115 @@ #define PRECISION_S 0 #define PRECISION_D 1 +#ifdef CONFIG_FPU + +#define FP_GET_RD(insn) (insn >> 7 & 0x1F) + +extern void put_f32_reg(unsigned long fp_reg, unsigned long value); + +static int set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) +{ + unsigned long fp_reg = FP_GET_RD(insn); + + put_f32_reg(fp_reg, val); + regs->status |= SR_FS_DIRTY; + + return 0; +} + +extern void put_f64_reg(unsigned long fp_reg, unsigned long value); + +static int set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) +{ + unsigned long fp_reg = FP_GET_RD(insn); + unsigned long value; + +#if __riscv_xlen == 32 + value = (unsigned long) &val; +#else + value = val; +#endif + put_f64_reg(fp_reg, value); + regs->status |= SR_FS_DIRTY; + + return 0; +} + +#if __riscv_xlen == 32 +extern void get_f64_reg(unsigned long fp_reg, u64 *value); + +static u64 get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + u64 val; + + get_f64_reg(fp_reg, &val); + regs->status |= SR_FS_DIRTY; + + return val; +} +#else + +extern unsigned long get_f64_reg(unsigned long fp_reg); + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val = get_f64_reg(fp_reg); + regs->status |= SR_FS_DIRTY; + + return val; +} + +#endif + +extern unsigned long get_f32_reg(unsigned long fp_reg); + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + unsigned long fp_reg = (insn >> fp_reg_offset) & 0x1F; + unsigned long val; + + val = get_f32_reg(fp_reg); + regs->status |= SR_FS_DIRTY; + + return val; +} + +#else /* CONFIG_FPU */ +static void set_f32_rd(unsigned long insn, struct pt_regs *regs, + unsigned long val) {} + +static void set_f64_rd(unsigned long insn, struct pt_regs *regs, u64 val) {} + +static unsigned long get_f64_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +static unsigned long get_f32_rs(unsigned long insn, u8 fp_reg_offset, + struct pt_regs *regs) +{ + return 0; +} + +#endif + +#define GET_F64_RS2(insn, regs) (get_f64_rs(insn, 20, regs)) +#define GET_F64_RS2C(insn, regs) (get_f64_rs(insn, 2, regs)) +#define GET_F64_RS2S(insn, regs) (get_f64_rs(RVC_RS2S(insn), 0, regs)) + +#define GET_F32_RS2(insn, regs) (get_f32_rs(insn, 20, regs)) +#define GET_F32_RS2C(insn, regs) (get_f32_rs(insn, 2, regs)) +#define GET_F32_RS2S(insn, regs) (get_f32_rs(RVC_RS2S(insn), 0, regs)) + #ifdef CONFIG_RISCV_M_MODE static inline int load_u8(struct pt_regs *regs, const u8 *addr, u8 *r_val) { @@ -362,15 +471,21 @@ int handle_misaligned_load(struct pt_regs *regs) return -1; } + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + val.data_u64 = 0; for (i = 0; i < len; i++) { if (load_u8(regs, (void *)(addr + i), &val.data_bytes[i])) return -1; } - if (fp) - return -1; - SET_RD(insn, regs, val.data_ulong << shift >> shift); + if (!fp) + SET_RD(insn, regs, val.data_ulong << shift >> shift); + else if (len == 8) + set_f64_rd(insn, regs, val.data_u64); + else + set_f32_rd(insn, regs, val.data_ulong); regs->epc = epc + INSN_LEN(insn); @@ -383,7 +498,7 @@ int handle_misaligned_store(struct pt_regs *regs) unsigned long epc = regs->epc; unsigned long insn; unsigned long addr = regs->badaddr; - int i, len = 0; + int i, len = 0, fp = 0; perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); @@ -400,6 +515,14 @@ int handle_misaligned_store(struct pt_regs *regs) } else if ((insn & INSN_MASK_SD) == INSN_MATCH_SD) { len = 8; #endif + } else if ((insn & INSN_MASK_FSD) == INSN_MATCH_FSD) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2(insn, regs); + } else if ((insn & INSN_MASK_FSW) == INSN_MATCH_FSW) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2(insn, regs); } else if ((insn & INSN_MASK_SH) == INSN_MATCH_SH) { len = 2; #if defined(CONFIG_64BIT) @@ -418,11 +541,32 @@ int handle_misaligned_store(struct pt_regs *regs) ((insn >> SH_RD) & 0x1f)) { len = 4; val.data_ulong = GET_RS2C(insn, regs); + } else if ((insn & INSN_MASK_C_FSD) == INSN_MATCH_C_FSD) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSDSP) == INSN_MATCH_C_FSDSP) { + fp = 1; + len = 8; + val.data_u64 = GET_F64_RS2C(insn, regs); +#if !defined(CONFIG_64BIT) + } else if ((insn & INSN_MASK_C_FSW) == INSN_MATCH_C_FSW) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2S(insn, regs); + } else if ((insn & INSN_MASK_C_FSWSP) == INSN_MATCH_C_FSWSP) { + fp = 1; + len = 4; + val.data_ulong = GET_F32_RS2C(insn, regs); +#endif } else { regs->epc = epc; return -1; } + if (!IS_ENABLED(CONFIG_FPU) && fp) + return -EOPNOTSUPP; + for (i = 0; i < len; i++) { if (store_u8(regs, (void *)(addr + i), val.data_bytes[i])) return -1; From patchwork Wed Oct 4 15:14:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148359 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204521vqb; Wed, 4 Oct 2023 08:14:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGUlvJEdvyOT0q06AsfbvjNPkRc6C2G7dPAxOqfiKXHdwfkgqEb61LPGkzC+wXuQ96XMsse X-Received: by 2002:a05:6a20:2446:b0:14c:e8d4:fb3e with SMTP id t6-20020a056a20244600b0014ce8d4fb3emr2848470pzc.43.1696432493915; Wed, 04 Oct 2023 08:14:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432493; cv=none; d=google.com; s=arc-20160816; b=HTzfIOH12nL6yr4UTTHkIehIb4e5WL20io8cDaYoUFYrD7kyoo7nFefOY2reoYlRAc oSsWJktORs8b8p3SYanlESIPncMkGKpl8Upjs0eK+2zxlvZN4MGEzaYvcry+jSeHq5p3 hXz3AgcRpMqA4mXibZ5SDft+qTkz8sZo9ywj3gOXhvPzOpdVryDjKbU6puojUEXarAHX nRrzv55njte1A8dQH+4t2YkstrzfKVcUu4vYlJT9gElaaX3iodNwF8nzBK66jFnpa1DC SPp5uaaLy2xUcdGEacA530mznr2n37sV8m8gkNTWsktr7TkWI83jPSrZwm9GiX7IDXFk BUVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rcEUkxfHErwG8tq/zMZua9Au/w+pS7+db1U/fyhODns=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=vuRVhfhhnRlOfa7EXnd/t6zrj/UUj6MO4lAiht1n6ma/HPJs3Vu7SUhHmaXEWhoLFg Eb5OPJzFzWGpJTg3sO05dNS/SojwZVgBOMOxANECZX0t1gPpeeCYz0zcJX0OlTezbOUR crzM3mPPYuylR74+0WWidUm7BUB5GlcM02HFG+htNVjRjPsGrRymFa/oL9p0TY5blwRH DzhsQu86k2QQMoKNsOv87acBggFamSUFmAhysd/KbG3xr3oVknOMoib5u0iZ8FZeFx+k p1jXcXG/Sc6KtJyauxjkVh0m9RyXax0JxTG6UrYiR4cVm1r5Z8lInQHS3hH+ozkK/Q5p ORKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=GPEE5tKW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id z3-20020a63ac43000000b00585a45417absi3850267pgn.267.2023.10.04.08.14.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=GPEE5tKW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 9C038836E5ED; Wed, 4 Oct 2023 08:14:52 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243180AbjJDPOm (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38590 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243123AbjJDPOd (ORCPT ); Wed, 4 Oct 2023 11:14:33 -0400 Received: from mail-wm1-x32b.google.com (mail-wm1-x32b.google.com [IPv6:2a00:1450:4864:20::32b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64BF9C4 for ; Wed, 4 Oct 2023 08:14:30 -0700 (PDT) Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-40651b22977so4786685e9.1 for ; Wed, 04 Oct 2023 08:14:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432469; x=1697037269; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rcEUkxfHErwG8tq/zMZua9Au/w+pS7+db1U/fyhODns=; b=GPEE5tKW/8Ms2NiF9y39KuR2HdmLb3no++VZaOwGz7y63NGjQEOCVudFne3yhB/HsK Pkmy9BpRApNtyOe305uADn5PhTJzRKpQa5GMnVpOcpMA77WA9stvBaVgv6562yutpIaT BfWbNq6Yx+ULq6YiACVOZaDofdeOMGhe9kh2AQdhzHtudE/AmR54qGPp1ZdCLWnkGZ6L AhRLouD9LNKWdb8/1pIcRwnnMnx4PacLY3kggulunoR3Hf+2hig5nELR6VpM9BLA+G9P J2ecPLsfJTZ5RfIJ6P7T+6qs/3fpl65HT5Z0aQlzqsBPE6ZcL+J6mzG7cF9QAWf5WSbQ zvqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432469; x=1697037269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rcEUkxfHErwG8tq/zMZua9Au/w+pS7+db1U/fyhODns=; b=sxSOb4dgHnyO8vqdAA9Z+jTAmQhbWpboHgDdOkVnPJhRuIflpBLtg9mdT6vq7rqseX XoLCmSoY8AEfemt4Zz3LlQ7Y2KzJaBuIxJGbDkAghPseA+Q/62A1I1tuBL02es7j/ADz wrwB5/+CPDHgn1PovA5SC2MGhkM/sexfxeozNnObA5NNDmhhxrXGqZ5CQZAB7riHauCi S25gycymCbE/mw56AeOxh87R9b0se//rv+94pF2G/ij6pyrPUuOHfgrp327mWSgydlpg /IYdFXdtJcn5En9vEgd7L0UxPYVYPiihHw7Oi6+X5DoW0XnLiOpmBverYx+/pC7yFIpx HQRw== X-Gm-Message-State: AOJu0YzCmBdLwRoTR1a7g6x975Zs/faynSO7yYIFgkIdeLruJvr2KzsQ wQS1Z739VgvqxW1V0g3LtHTp4g== X-Received: by 2002:a05:600c:1d18:b0:404:72f9:d59a with SMTP id l24-20020a05600c1d1800b0040472f9d59amr2613227wms.0.1696432468784; Wed, 04 Oct 2023 08:14:28 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:28 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 5/8] riscv: add support for sysctl unaligned_enabled control Date: Wed, 4 Oct 2023 17:14:02 +0200 Message-ID: <20231004151405.521596-6-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838398399780266 X-GMAIL-MSGID: 1778838398399780266 This sysctl tuning option allows the user to disable misaligned access handling globally on the system. This will also be used by misaligned detection code to temporarily disable misaligned access handling. Signed-off-by: Clément Léger Reviewed-by: Björn Töpel --- arch/riscv/Kconfig | 1 + arch/riscv/kernel/traps_misaligned.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 6e167358a897..1313f83bb0cb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -638,6 +638,7 @@ config THREAD_SIZE_ORDER config RISCV_MISALIGNED bool "Support misaligned load/store traps for kernel and userspace" + select SYSCTL_ARCH_UNALIGN_ALLOW default y help Say Y here if you want the kernel to embed support for misaligned diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index 041fd2dbd955..b5fb1ff078e3 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -396,6 +396,9 @@ union reg_data { u64 data_u64; }; +/* sysctl hooks */ +int unaligned_enabled __read_mostly = 1; /* Enabled by default */ + int handle_misaligned_load(struct pt_regs *regs) { union reg_data val; @@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; @@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + if (!unaligned_enabled) + return -1; + if (get_insn(regs, epc, &insn)) return -1; From patchwork Wed Oct 4 15:14:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148360 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204537vqb; Wed, 4 Oct 2023 08:14:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFV+TtFsCERk5dPCv6GRzZb6tT4JvFimAcAWC7kASb+T2nBLfw2cV8qVyB6aYLjuFJHnxzs X-Received: by 2002:a05:6a00:a18:b0:693:3e55:59b4 with SMTP id p24-20020a056a000a1800b006933e5559b4mr2453572pfh.8.1696432494862; Wed, 04 Oct 2023 08:14:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432494; cv=none; d=google.com; s=arc-20160816; b=YsqSykpelZoFAZj+8kC059xZcPXfm5B23Yun7qhMOnpCl3CZ9eAKnWoPa2pUEl/xa4 gPp/larXnmu3KlPgnaUNGo3I8srDislwgLtYZJgfJzcx1aGuH1+d3ONVSsI8rzpajWUL tlRAPcb1t0LJzWXinFCH/VVbfqz7XZAF90ve3mUwWokftzoqFpirHbgbP4awwh0FV16B s0wLZhZyaFSqyuIYkXFIW7R0EArdxb9ekeoxvGRt3nqBmGb9YyohPDiZgdJptwj09Iap fzqlRlrlIS7kWf3jvwT79V8o98CK9EJ8ac8g6TDdNg7SGjsYmobK+Zd66n/b89TXMxMv tbeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2XZchuQuCBpXHMvu1aRqXWCThK6+yA7m0aHqniG2w4Y=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=D5adGj/17xkHGeTN5FP4+sKW+r24NzOluZpZQKVmcZnkvnRfbZJbY/k2Eg7pRuh1Ec LfiBQ++rjuq2qkVmHZjhpW2u4kxYL9xT4JM1jHw6E1n4G8GZjUjf8G7Uv8CxawH9cq5/ M1LoxuiZ+9TgMCosrVoc+sXga4+9WTDtK9QEJKg7mFtrJWilbjFvgc6OsUKBkQVs34tZ W/mh/Mmmc4tMmydwuHyp/s9Y36Ax878vMtv5enh2HUm+g+VIavyamJ6Ws/MBCxgfKE4s EF7guG8By/v+bsBZl5ow4rAShNqQoAtFw4tkDCobAH/e9rwISM2O0ncgI3ZVBDgUuYv1 09dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=AVQg2khA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id ck13-20020a056a00328d00b0069338feae40si3824950pfb.149.2023.10.04.08.14.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=AVQg2khA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D5E2F822CE3B; Wed, 4 Oct 2023 08:14:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243165AbjJDPOq (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243130AbjJDPOf (ORCPT ); Wed, 4 Oct 2023 11:14:35 -0400 Received: from mail-wm1-x333.google.com (mail-wm1-x333.google.com [IPv6:2a00:1450:4864:20::333]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F503BD for ; Wed, 4 Oct 2023 08:14:31 -0700 (PDT) Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-406553f6976so5071545e9.1 for ; Wed, 04 Oct 2023 08:14:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432469; x=1697037269; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2XZchuQuCBpXHMvu1aRqXWCThK6+yA7m0aHqniG2w4Y=; b=AVQg2khABC/Xvydb92TsrAVy365xGerutucR3ODh63RyfSat3Ue7Dz8ftA3Ba/Q2Xl 9+KwaxnQjBsCBXp0c69x/hJSVcA3ZgJwm/HgU2F1KbbyaOvgxB13sN1QDtFIwiUl/nvH fel2WiY4oHeXCB3GNifmj+vDZsy/mc2CW7xGzRvKOe/YNA62jgF8m2mmUUkddFUEeoVv /2lETf7Mbgzouvtz2MjgX24FQYRWpG8SZDvPeNAlPS5cOBUOG7z8QIeIa9OnMuGkeppM JHx8NL5yTM73lWnPi+MUEO5aFaEiIuJPq9s7DZig2EsKPVVE0+NTsGcoNLAEohGv2ucf LUug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432469; x=1697037269; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2XZchuQuCBpXHMvu1aRqXWCThK6+yA7m0aHqniG2w4Y=; b=kU1uXbRH90uRXDcn+2qeewEo/gt0nOHZlf/KierBomM/cRcw0oLd7Dj8Nh75UibHbf NGycUJkV13tvlfUB8BEuvpfhyHDQ6aXAgoIt803zL2QGQTfdr5L6dWlVpP5/gZ5OS59V BJVFJrFK4CejhnFT/Wn1Jf5oKh+Ny01fyTPFIPCilGP0kJLi2a0fwB+uBwmZOcn1B6/A lovSIKCT1Fcbp7G7jouwpT4ZDUWz4jI50E61wnvGbgaJcy05PSgv1FomadGz/Md7hrCr VDU3ImnV4f7kAkCNA4eJa2+8lkEilhR+JiA2Oh1xH8YntsDM4mliu3LdOdRs6Guylihn KF9Q== X-Gm-Message-State: AOJu0YyKY1ixXqtWtdqGspt5u1JDqVncEZ3UOZRvZsC0wAenOsFxzOK2 Lc6C1Hy+UXqMRbal5qBxAAPMkw== X-Received: by 2002:a05:600c:1d03:b0:404:7606:a871 with SMTP id l3-20020a05600c1d0300b004047606a871mr2610672wms.2.1696432469747; Wed, 04 Oct 2023 08:14:29 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:29 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 6/8] riscv: annotate check_unaligned_access_boot_cpu() with __init Date: Wed, 4 Oct 2023 17:14:03 +0200 Message-ID: <20231004151405.521596-7-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838399872527610 X-GMAIL-MSGID: 1778838399872527610 This function is solely called as an initcall, thus annotate it with __init. Signed-off-by: Clément Léger Reviewed-by: Evan Green --- arch/riscv/kernel/cpufeature.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1cfbba65d11a..356e5677eeb1 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -645,7 +645,7 @@ void check_unaligned_access(int cpu) __free_pages(page, get_order(MISALIGNED_BUFFER_SIZE)); } -static int check_unaligned_access_boot_cpu(void) +static int __init check_unaligned_access_boot_cpu(void) { check_unaligned_access(0); return 0; From patchwork Wed Oct 4 15:14:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148361 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp204570vqb; Wed, 4 Oct 2023 08:14:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIUYT+wPY7/td1AWuda9UpWem4mDKSOjRQwQjHogNvhHic8mqwkUbNDzsaXQJNXQJphGkP X-Received: by 2002:a17:902:9885:b0:1c6:16d3:1783 with SMTP id s5-20020a170902988500b001c616d31783mr2454414plp.58.1696432496370; Wed, 04 Oct 2023 08:14:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432496; cv=none; d=google.com; s=arc-20160816; b=ZYdjQv+ArGTY1W30qhnUurrmXjrd0OSi8PsX0H44Ha6Jh9smSgSLxwzbq0QzgznMXw n004nbLzr3tu5hQCOfIOKTZkQwCzdnBbvXNq3GN5WW3gmD6yRg3Vpnry18M5yxpFTcDn trXzYdua4r4U1KXIZxCNW1WrcZQOkjgEorkuofCSoXgY5fNmIQb0154k1g1ucbvTCp2I iG40nqpAFqf/O6Py+5+kchm7ULSjKWuzgitS3fBLQnx9qLko5T7latW2IwutQj4Afik7 /gnQR2lQcu0P+hNYWE7hD2+46D8IkBAZzmo3C4CngaKcVIRVux4u4vaexHlD5WobcrAD Ip8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=7hHT3aIZuw8Lkm84JjKEOwJDf1f+gUckXFbeev3RO+4=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=qUNeICLGLwHwis12e7Ojkn3NnXd9gUBuaa/esqw8TtAcUGslCnSJ7Igz3FtKWRnkhK OsPyxtAuhM8QAEy3786nBSDXu2E3yXKlyis+lETxotHdkR1/oQX7uyNICzAgvh1uYyd3 xCqhDVPFGGczauJXPfzHhTJBYK/jCeOsI1+UsQ1mmBSTclRco30sunU1WojqM7eduh2S PRJSyfrzUduSs5FHiJePasrhwuNKzTvkAgbCKzg5aIkPhtkdHQiJrF+FrFStyuT/6LGQ mM5a18pJ2Npjp0im2u/c4i/XEcYhDyaHCzQaONp6i4lR1wJFc5t5bxgozZgd3be9aPdm XBVQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=RQmVcm56; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id n1-20020a170903404100b001c76a1aa6basi3468390pla.27.2023.10.04.08.14.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:56 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=RQmVcm56; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id C42D58370D85; Wed, 4 Oct 2023 08:14:54 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243206AbjJDPOu (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243131AbjJDPOg (ORCPT ); Wed, 4 Oct 2023 11:14:36 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 323DDC1 for ; Wed, 4 Oct 2023 08:14:32 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-4064e3c7c07so3944685e9.1 for ; Wed, 04 Oct 2023 08:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432470; x=1697037270; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7hHT3aIZuw8Lkm84JjKEOwJDf1f+gUckXFbeev3RO+4=; b=RQmVcm56mq3BNJ9ABwbqJ4e0fbojI0FXUVr0s8AwYYNbUuNoJlKghI/U0HQrq8nsO/ VB9hKdjA55UgATs+tMoG7Oe3QfMI3Y7l2sosFgQMpByBNxts5hclVT3JtrGpgIyBBFxp M2mkSdXQTSKMb7Kvn12qTGT6fJYXzoKVIr2vng5a2M1smyEEZjhFjP6nrmFIRVpeaZbl 4XXV+jdRN3sWevZdA9RA+7cy5COSSH6DvA/c5d4TcSdkPAz55bPCBWZzqzEHHDTh7/Zl QCe2MfDLUGDo+pMhx9qxb933pl0eV6qSeBsS0HAp0rUFa+mGcXR36juQ7WDOsPWJHHzn C4vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432470; x=1697037270; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7hHT3aIZuw8Lkm84JjKEOwJDf1f+gUckXFbeev3RO+4=; b=UzdI5gu+j7a6bHD4dSvz9jvvwIvbTC7hD1gtGXBqRtfpqF5mPRAfwC14lGkfHPIhB/ c9HjqvQhIz7CxAX4rGyl9r0b5lMeQQ9SditLtUPCldeTPYpFcyrOtAUxNE5RhuLcoJG8 hK8eIhiNgoBdRF8KEE8Qj+K990Ky4PsJrJCazsQIVnpDPk2gzX/GLbw3oPj0B1sHYRhF 7P6XMeE+NS44Bhsk3Fbq88CkOYf8EHyy8oMrb0QuScuB3+q4GZ9Xpy2SDXfeAAFlN2JG ofBBnWa604snR02Yf/ziTMYqW71K6Vgd9zoC+TZQr55FQsYucFOYdiEKb9nOukSkTS2e Ax6A== X-Gm-Message-State: AOJu0YwPvagPzgCMQpgXJdatkfEG3M07cdeQ843LzO+gHMkreTj/yYMJ GYMf4G36QIw5/uacRSJvuHy3+Q== X-Received: by 2002:a05:600c:5192:b0:405:1ba2:4fcf with SMTP id fa18-20020a05600c519200b004051ba24fcfmr2488327wmb.4.1696432470736; Wed, 04 Oct 2023 08:14:30 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:30 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 7/8] riscv: report misaligned accesses emulation to hwprobe Date: Wed, 4 Oct 2023 17:14:04 +0200 Message-ID: <20231004151405.521596-8-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:14:54 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838401129335116 X-GMAIL-MSGID: 1778838401129335116 hwprobe provides a way to report if misaligned access are emulated. In order to correctly populate that feature, we can check if it actually traps when doing a misaligned access. This can be checked using an exception table entry which will actually be used when a misaligned access is done from kernel mode. Signed-off-by: Clément Léger --- arch/riscv/include/asm/cpufeature.h | 18 +++++++++ arch/riscv/kernel/cpufeature.c | 4 ++ arch/riscv/kernel/smpboot.c | 2 +- arch/riscv/kernel/traps_misaligned.c | 56 ++++++++++++++++++++++++++++ 4 files changed, 79 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h index d0345bd659c9..e4ae6af51876 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -32,4 +32,22 @@ extern struct riscv_isainfo hart_isa[NR_CPUS]; void check_unaligned_access(int cpu); +#ifdef CONFIG_RISCV_MISALIGNED +bool unaligned_ctl_available(void); +bool check_unaligned_access_emulated(int cpu); +void unaligned_emulation_finish(void); +#else +static inline bool unaligned_ctl_available(void) +{ + return false; +} + +static inline bool check_unaligned_access_emulated(int cpu) +{ + return false; +} + +static inline void unaligned_emulation_finish(void) {} +#endif + #endif diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 356e5677eeb1..fbbde800bc21 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -568,6 +568,9 @@ void check_unaligned_access(int cpu) void *src; long speed = RISCV_HWPROBE_MISALIGNED_SLOW; + if (check_unaligned_access_emulated(cpu)) + return; + page = alloc_pages(GFP_NOWAIT, get_order(MISALIGNED_BUFFER_SIZE)); if (!page) { pr_warn("Can't alloc pages to measure memcpy performance"); @@ -648,6 +651,7 @@ void check_unaligned_access(int cpu) static int __init check_unaligned_access_boot_cpu(void) { check_unaligned_access(0); + unaligned_emulation_finish(); return 0; } diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 1b8da4e40a4d..5d9858d6ad26 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -245,8 +245,8 @@ asmlinkage __visible void smp_callin(void) riscv_ipi_enable(); numa_add_cpu(curr_cpuid); - set_cpu_online(curr_cpuid, 1); check_unaligned_access(curr_cpuid); + set_cpu_online(curr_cpuid, 1); if (has_vector()) { if (riscv_v_setup_vsize()) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index b5fb1ff078e3..d99b95084b6c 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -14,6 +14,8 @@ #include #include #include +#include +#include #define INSN_MATCH_LB 0x3 #define INSN_MASK_LB 0x707f @@ -396,6 +398,8 @@ union reg_data { u64 data_u64; }; +static bool unaligned_ctl __read_mostly; + /* sysctl hooks */ int unaligned_enabled __read_mostly = 1; /* Enabled by default */ @@ -409,6 +413,8 @@ int handle_misaligned_load(struct pt_regs *regs) perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr); + *this_cpu_ptr(&misaligned_access_speed) = RISCV_HWPROBE_MISALIGNED_EMULATED; + if (!unaligned_enabled) return -1; @@ -585,3 +591,53 @@ int handle_misaligned_store(struct pt_regs *regs) return 0; } + +bool check_unaligned_access_emulated(int cpu) +{ + long *mas_ptr = per_cpu_ptr(&misaligned_access_speed, cpu); + unsigned long tmp_var, tmp_val; + bool misaligned_emu_detected; + + *mas_ptr = RISCV_HWPROBE_MISALIGNED_UNKNOWN; + + __asm__ __volatile__ ( + " "REG_L" %[tmp], 1(%[ptr])\n" + : [tmp] "=r" (tmp_val) : [ptr] "r" (&tmp_var) : "memory"); + + misaligned_emu_detected = (*mas_ptr == RISCV_HWPROBE_MISALIGNED_EMULATED); + /* + * If unaligned_ctl is already set, this means that we detected that all + * CPUS uses emulated misaligned access at boot time. If that changed + * when hotplugging the new cpu, this is something we don't handle. + */ + if (unlikely(unaligned_ctl && !misaligned_emu_detected)) { + pr_crit("CPU misaligned accesses non homogeneous (expected all emulated)\n"); + while (true) + cpu_relax(); + } + + return misaligned_emu_detected; +} + +void __init unaligned_emulation_finish(void) +{ + int cpu; + + /* + * We can only support PR_UNALIGN controls if all CPUs have misaligned + * accesses emulated since tasks requesting such control can run on any + * CPU. + */ + for_each_present_cpu(cpu) { + if (per_cpu(misaligned_access_speed, cpu) != + RISCV_HWPROBE_MISALIGNED_EMULATED) { + return; + } + } + unaligned_ctl = true; +} + +bool unaligned_ctl_available(void) +{ + return unaligned_ctl; +} From patchwork Wed Oct 4 15:14:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= X-Patchwork-Id: 148363 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:254a:b0:403:3b70:6f57 with SMTP id hf10csp205461vqb; Wed, 4 Oct 2023 08:16:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGiiZ/2k84mBwzV5Vb0r1c5ebmVYF2OXsxHzzx485V6C9kwTDk725zhiH8BhRyIno5wtm7n X-Received: by 2002:a17:903:1208:b0:1c3:92de:1b23 with SMTP id l8-20020a170903120800b001c392de1b23mr3294999plh.59.1696432566850; Wed, 04 Oct 2023 08:16:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696432566; cv=none; d=google.com; s=arc-20160816; b=vnLaOQUJXXWG0WOBhuAs0jaaNfsc+NXeTg6WWiWgRdeG/vlWL9EB51fRRVDkiE/Uxz 7+LFMA+vNSyUkZbVGyracZY2WINQSAHtODUTQj+i6S2fEDGvU21XLVI6V5ZdkS5kXj7V AXjGAq9uM4zMrkDM9AtdH3wXsI7bQUtREbPV6lbippkqpmjTTbFPyC8tvWmTJ5YGm0Em oWt6BHTjdR8YQjNuP1AGP6vmijkFy2hAt2d8EKAXdYlbAdQhd3PhE9UK6Y+WBBvEITfb ypBkdzToEjGjc9rnBHzsX+tLFuhPIAJiMSd4AY/k/gqhJVtshj45Fq1+9OzxVYvOEw4J qqKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mgvk3biMyb3dWXWlkLQojD9wXEb7N0NOjcs65taIzUI=; fh=M3IaBqctF22KRVIxHueWSzMXaLjWPJa1aCUZDNwNn2A=; b=JpGGrJMcAc4p/OFh7AkKkFmHvgDxIqTvDSYEfq5R3WEFjHM/FYoM34oKsL7bFgard8 T2eVqtCjo6eBlirZCrHCnpnjhgOFDvysZVdWlakM9MqrIzQnFY6DLirrloHfM+SehBZF pS6GM+OBaxb/Ab2EkTkBIou3PxrEmmGIpPr3+sjSHVD5IIfKq1E9kh9SznHKgKoPSpQs fAWz9yuVsMe91aXQXUvgR6xnVnEMLdOVtejIzCMoH4iAZXH/lWNhCEfJjGTBMR7DOuL9 YXTOlnOVQcrSbMOLM6OUMoc2qQNWpg/ejmGeWp/iKx7HU6PdAF7OtNmXpw+9tkHoxolc 0HWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=nUeW6T6p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id a15-20020a170902710f00b001c770264989si3645261pll.618.2023.10.04.08.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:16:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@rivosinc-com.20230601.gappssmtp.com header.s=20230601 header.b=nUeW6T6p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 69F6C80F6691; Wed, 4 Oct 2023 08:16:04 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243215AbjJDPOw (ORCPT + 18 others); Wed, 4 Oct 2023 11:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51856 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243147AbjJDPOj (ORCPT ); Wed, 4 Oct 2023 11:14:39 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33E24CE for ; Wed, 4 Oct 2023 08:14:33 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-4064e3c7c07so3944735e9.1 for ; Wed, 04 Oct 2023 08:14:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1696432471; x=1697037271; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mgvk3biMyb3dWXWlkLQojD9wXEb7N0NOjcs65taIzUI=; b=nUeW6T6pTJRYIOYabrcMy7S4fkvdDOWVf5fOP5TrBvUZzdn6BedDcai/Gs1PVuwkRw LuDmxohXQq2cN1XGUDGCbRCMUcn5jFqCkkIa83rYiOCxswXKf1FNQB7ssZPfgla+j4Ib xNjaEN280Y7mCrh6aRjz6lUMh5lMXxBuS90a59/LkKVZt7Llk4uhzWj5g/a4Kj5Tjeu1 IrzS6hQMmKGqqDifEsTRYb8ctZtd0smJYTTeEoiU87bbVyIWTxElkPHULNWfIh2qZnd/ taEIeUd1Wn3Plgo/R4lOmrZ/Z74qenyIR6/lnsIArf3+KVzSWARMC138dVV1WnJJaKGu EMdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696432471; x=1697037271; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mgvk3biMyb3dWXWlkLQojD9wXEb7N0NOjcs65taIzUI=; b=Tm/EJKs8pKDpvzxd2rqyBvOHoNDZJARpdoUitP8mw2/V+GsIWUnN1Mf2LzC6oQYiIV JuWHIN9uuOzF8RjeF/Ep24H386ENCSL/tCH65XRngey7KxVVZJSd2oy6vGE7s9pb+dJ1 S0twostrSluVp4Fa7cnUGtLnCgB0elc2vIiWNk/l6WwsvKsZ8ZBffX6FEWZj0acyD/UV 2jeVlwf9lKNMpq9w5q5UzULQvRTkdqiRe684YFTEtxfXiHEtxUmjPaHe3gUavq7Zx8On LEj25TTXDKVl5hFtr4faE3tKXPipI2+CKasyuUR/qoCSLy51Ju0P5su+uxFNcL0SLD1q 4foQ== X-Gm-Message-State: AOJu0Yy5/5k7iRBAAfMGPpEB+FlLE37RgZWP8qjVQyCelRBIhTNoX+bp YYgmftPJDLH/r4g4wqhMYGP4Dg== X-Received: by 2002:a05:600c:5192:b0:405:1ba2:4fcf with SMTP id fa18-20020a05600c519200b004051ba24fcfmr2488360wmb.4.1696432471665; Wed, 04 Oct 2023 08:14:31 -0700 (PDT) Received: from carbon-x1.. ([2a01:e0a:999:a3a0:9474:8d75:5115:42cb]) by smtp.gmail.com with ESMTPSA id i2-20020a05600c290200b00402f7b50517sm1768764wmd.40.2023.10.04.08.14.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 08:14:31 -0700 (PDT) From: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= To: Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: =?utf-8?b?Q2zDqW1lbnQgTMOpZ2Vy?= , Atish Patra , Andrew Jones , Evan Green , =?utf-8?q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski , Conor Dooley Subject: [PATCH v2 8/8] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Date: Wed, 4 Oct 2023 17:14:05 +0200 Message-ID: <20231004151405.521596-9-cleger@rivosinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com> References: <20231004151405.521596-1-cleger@rivosinc.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 04 Oct 2023 08:16:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778838475338142968 X-GMAIL-MSGID: 1778838475338142968 Now that trap support is ready to handle misalignment errors in S-mode, allow the user to control the behavior of misaligned accesses using prctl(PR_SET_UNALIGN). Add an align_ctl flag in thread_struct which will be used to determine if we should SIGBUS the process or not on such fault. Signed-off-by: Clément Léger Reviewed-by: Björn Töpel --- arch/riscv/include/asm/processor.h | 9 +++++++++ arch/riscv/kernel/process.c | 18 ++++++++++++++++++ arch/riscv/kernel/traps_misaligned.c | 6 ++++++ 3 files changed, 33 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 3e23e1786d05..adbe520d07c5 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -8,6 +8,7 @@ #include #include +#include #include @@ -82,6 +83,7 @@ struct thread_struct { unsigned long bad_cause; unsigned long vstate_ctrl; struct __riscv_v_ext_state vstate; + unsigned long align_ctl; }; /* Whitelist the fstate from the task_struct for hardened usercopy */ @@ -94,6 +96,7 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset, #define INIT_THREAD { \ .sp = sizeof(init_stack) + (long)&init_stack, \ + .align_ctl = PR_UNALIGN_NOPRINT, \ } #define task_pt_regs(tsk) \ @@ -134,6 +137,12 @@ extern long riscv_v_vstate_ctrl_set_current(unsigned long arg); extern long riscv_v_vstate_ctrl_get_current(void); #endif /* CONFIG_RISCV_ISA_V */ +extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr); +extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val); + +#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr)) +#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val)) + #endif /* __ASSEMBLY__ */ #endif /* _ASM_RISCV_PROCESSOR_H */ diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e32d737e039f..4f21d970a129 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -25,6 +25,7 @@ #include #include #include +#include register unsigned long gp_in_global __asm__("gp"); @@ -41,6 +42,23 @@ void arch_cpu_idle(void) cpu_do_idle(); } +int set_unalign_ctl(struct task_struct *tsk, unsigned int val) +{ + if (!unaligned_ctl_available()) + return -EINVAL; + + tsk->thread.align_ctl = val; + return 0; +} + +int get_unalign_ctl(struct task_struct *tsk, unsigned long adr) +{ + if (!unaligned_ctl_available()) + return -EINVAL; + + return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr); +} + void __show_regs(struct pt_regs *regs) { show_regs_print_info(KERN_DEFAULT); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c index d99b95084b6c..bba301b5194d 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -418,6 +418,9 @@ int handle_misaligned_load(struct pt_regs *regs) if (!unaligned_enabled) return -1; + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1; @@ -517,6 +520,9 @@ int handle_misaligned_store(struct pt_regs *regs) if (!unaligned_enabled) return -1; + if (user_mode(regs) && (current->thread.align_ctl & PR_UNALIGN_SIGBUS)) + return -1; + if (get_insn(regs, epc, &insn)) return -1;