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[2620:137:e000::3:4]) by mx.google.com with ESMTPS id y11-20020a170903010b00b001bdd35033efsi3188475plc.374.2023.10.04.02.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 02:16:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=jtg6xYav; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 79F7E80F4E01; Wed, 4 Oct 2023 02:16:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242003AbjJDJQp (ORCPT + 18 others); Wed, 4 Oct 2023 05:16:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51636 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242065AbjJDJQi (ORCPT ); Wed, 4 Oct 2023 05:16:38 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1F4EA7; Wed, 4 Oct 2023 02:16:33 -0700 (PDT) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 39459iVV029811; Wed, 4 Oct 2023 11:16:00 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=JVqHuVV3JttG4RzBiSL1T8HY6o/rE8x5S05xc9coNhs=; b=jt g6xYavJeialzxMOd+Flg7pf3IXHsF07kL6N1/9jJPcj0vSz+XyUruNm/EgVEgau+ JbG+nu0aLBYXJvmv+JkNuzh9eocv8KWrQMttnfuBEBVQGEDJfpWrmGReG0T0YNCH 7f/B8GQaouSeamK293iLYI0mAIIGnUM0N0074IwiCoDFZytld+1JOM03XlTxNICM mqQxCexZHbV3wQnvzf7PJV0FMe3Yvf4WpLqcXMtZ/IxmMmEaioFkoN7sgVgg/8FQ QGuVDXS2h46NlEBsFwYTpt7nhEDRIiTzSQAcnFwR+2XjUI31pZ9N7ZVkJbif7N61 hDwCfPXu0MociQg+PSJw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tew80nsd6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Oct 2023 11:16:00 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id A300A100057; Wed, 4 Oct 2023 11:15:59 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9A47C22A6DE; Wed, 4 Oct 2023 11:15:59 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 11:15:59 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Andrzej Pietrasiewicz Subject: [PATCH 1/7] dt-bindings: media: Document STM32MP25 VDEC video decoder Date: Wed, 4 Oct 2023 11:15:46 +0200 Message-ID: <20231004091552.3531659-2-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> References: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_01,2023-10-02_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 04 Oct 2023 02:16:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778815879174484156 X-GMAIL-MSGID: 1778815879174484156 Add STM32MP25 VDEC video decoder bindings. Signed-off-by: Hugues Fruchet --- .../bindings/media/st,stm32mp25-vdec.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32mp25-vdec.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-vdec.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-vdec.yaml new file mode 100644 index 000000000000..cf41f704113f --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-vdec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-vdec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VDEC video decoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VDEC video hardware decoder + peripheral based on Verisilicon VC8000NanoD IP (former Hantro G1). + +properties: + compatible: + const: st,stm32mp25-vdec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + vdec: vdec@580d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x580d0000 0x3c8>; + interrupts = ; + interrupt-names = "vdec"; + clocks = <&ck_icn_p_vdec>; + clock-names = "vdec-clk"; + }; From patchwork Wed Oct 4 09:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 148191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp2487975rwb; Wed, 4 Oct 2023 02:16:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGRmlNtZ35K+lyGG5Ir+GHvz+tP3lmbVOKDviRMQn3LFjPQxy0cdny+xyLrLnPyGclM3OWZ X-Received: by 2002:a17:90a:ca86:b0:274:8951:b5ed with SMTP id y6-20020a17090aca8600b002748951b5edmr2659562pjt.20.1696411001769; Wed, 04 Oct 2023 02:16:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696411001; cv=none; d=google.com; s=arc-20160816; b=DmlCPPtAdUR7ufcG8GnF6UHc6RTCkFIGhffHd4bdFRNQW5IUJ6BnYQyrC6BcGq4FwD Z/yNSy1Ed0vT0DjW82WjiKRXVFoW053fCcvqLkA1iprBJxqSAEf/jEnHIF+sBawRFGy3 4K/iW+frWy8ZK3qtsrY1nN2Qr3i0/apB4kBaZwYY0cdZN/R/LRrRjYRP/MXeXAKVTIRH 0qddzry/sb1Gx90xgK1hlKh/k4TCbeMoTEmZrZgA8BlsBqCOvteJgE67JOGCv6VZCMWi 51hZYnfmjOLom2/jUS8mwqY1khEZOeYZxWezqOOackg9ZxYG2eRVdbvSw1MVp3B4HFqS 5AgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JSXv5uBlf7Nq7B8f/KA47gP5JBCzVC46AOMucC11/d4=; fh=ItXiUQa06G5NtzfQ6MBP/cGHELTOauPzcHi5SmTT7Sw=; b=F1TxrWlRdMTEipNc1DaPVQty0p2UPj+pla/loNN/0/N+1PfQZOKzTuO1Df4Ql3gbPW Gxv/jvFXKOuIJgrKw5DomuF1Ow64RLAoRlX9oClTckxbqx3IDaKpKKP0cRfHD7QqfXGT EqMB66Ps5eM/dP3CCYFzGf86Q5zm4J8aO+bUAgIPJ5eEYWehLzVOj3lV46OpQmzWjVl5 LBNZLm+Fqqslik43vntDVPbAWRyJs321ZOAQkj+N/Il35Ag2XxwvonRB4TjDqDRmw4ma FaxWzxwdf05ekQaU2pI+B+iyhchUKqhlzC5wM9DLPgf2iCzpt5R8x8n9aYN1VxLbq4vV z05g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=PfYwpTPA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from snail.vger.email (snail.vger.email. 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H264/VP8 decoding up to 4080x4080. No post-processor support. VDEC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet --- drivers/media/platform/verisilicon/Kconfig | 14 ++- drivers/media/platform/verisilicon/Makefile | 3 + .../media/platform/verisilicon/hantro_drv.c | 3 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_vdec_hw.c | 92 +++++++++++++++++++ 5 files changed, 110 insertions(+), 3 deletions(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c diff --git a/drivers/media/platform/verisilicon/Kconfig b/drivers/media/platform/verisilicon/Kconfig index e65b836b9d78..7642ff9cf96c 100644 --- a/drivers/media/platform/verisilicon/Kconfig +++ b/drivers/media/platform/verisilicon/Kconfig @@ -4,7 +4,7 @@ comment "Verisilicon media platform drivers" config VIDEO_HANTRO tristate "Hantro VPU driver" - depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || COMPILE_TEST + depends on ARCH_MXC || ARCH_ROCKCHIP || ARCH_AT91 || ARCH_SUNXI || ARCH_STM32 || COMPILE_TEST depends on V4L_MEM2MEM_DRIVERS depends on VIDEO_DEV select MEDIA_CONTROLLER @@ -16,8 +16,8 @@ config VIDEO_HANTRO select V4L2_VP9 help Support for the Hantro IP based Video Processing Units present on - Rockchip and NXP i.MX8M SoCs, which accelerate video and image - encoding and decoding. + Rockchip, NXP i.MX8M and STM32MP25 SoCs, which accelerate video + and image encoding and decoding. To compile this driver as a module, choose M here: the module will be called hantro-vpu. @@ -52,3 +52,11 @@ config VIDEO_HANTRO_SUNXI default y help Enable support for H6 SoC. + +config VIDEO_HANTRO_STM32MP25 + bool "Hantro STM32MP25 support" + depends on VIDEO_HANTRO + depends on ARCH_STM32 || COMPILE_TEST + default y + help + Enable support for STM32MP25 SoCs. diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index 6ad2ef885920..5854e0f0dd32 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -39,3 +39,6 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_ROCKCHIP) += \ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ sunxi_vpu_hw.o + +hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \ + stm32mp25_vdec_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 423fc85d79ee..8c6e0c66f0cd 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -732,6 +732,9 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_SUNXI { .compatible = "allwinner,sun50i-h6-vpu-g2", .data = &sunxi_vpu_variant, }, +#endif +#ifdef CONFIG_VIDEO_HANTRO_STM32MP25 + { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index 7f33f7b07ce4..b7eccc1a96fc 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -406,6 +406,7 @@ extern const struct hantro_variant rk3568_vpu_variant; extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; +extern const struct hantro_variant stm32mp25_vdec_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c b/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c new file mode 100644 index 000000000000..c9f107bc09db --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_vdec_hw.c @@ -0,0 +1,92 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VDEC video decoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include "hantro.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_vdec_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_NV12, + .codec_mode = HANTRO_MODE_NONE, + .frmsize = { + .min_width = 96, + .max_width = 4080, + .step_width = MB_DIM, + .min_height = 96, + .max_height = 4080, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_VP8_FRAME, + .codec_mode = HANTRO_MODE_VP8_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 96, + .max_width = 4080, + .step_width = MB_DIM, + .min_height = 96, + .max_height = 4080, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .codec_mode = HANTRO_MODE_H264_DEC, + .max_depth = 2, + .frmsize = { + .min_width = 96, + .max_width = 4080, + .step_width = MB_DIM, + .min_height = 96, + .max_height = 4080, + .step_height = MB_DIM, + }, + }, +}; + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_vdec_codec_ops[] = { + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .reset = hantro_g1_reset, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .reset = hantro_g1_reset, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + +static const struct hantro_irq stm32mp25_irqs[] = { + { "vdec", hantro_g1_irq }, +}; + +static const char * const stm32mp25_clk_names[] = { "vdec-clk" }; + +const struct hantro_variant stm32mp25_vdec_variant = { + .dec_fmts = stm32mp25_vdec_fmts, + .num_dec_fmts = ARRAY_SIZE(stm32mp25_vdec_fmts), + .codec = HANTRO_VP8_DECODER | HANTRO_H264_DECODER, + .codec_ops = stm32mp25_vdec_codec_ops, + .irqs = stm32mp25_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_irqs), + .clk_names = stm32mp25_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_clk_names), +}; From patchwork Wed Oct 4 09:15:48 2023 Content-Type: text/plain; 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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id f1-20020a170902ce8100b001c75540d9fesi3614553plg.587.2023.10.04.02.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 02:17:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=OOsEZgJ9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 46B4281F3328; Wed, 4 Oct 2023 02:16:55 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241982AbjJDJQf (ORCPT + 18 others); Wed, 4 Oct 2023 05:16:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242065AbjJDJQc (ORCPT ); Wed, 4 Oct 2023 05:16:32 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EDF2698; Wed, 4 Oct 2023 02:16:28 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3945aC2J021867; Wed, 4 Oct 2023 11:16:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=tN8WihHZ8UtI7rsXlOoBMNAknU2jMb2LP7lJZaLwYH8=; b=OO sEZgJ9bL5gYQUKt35WoI2CeLx0DyXR46fGkH6nM8/uc5Y4xWaU5KC/GHE/mGCtTG XUR/sIwBMq0R+dw4nKqQ//Py2ewHi1H/e4Z7r2vrhaRzHS42dOCw1Y29CwJupKyY xGJzrgDuqi6TF87eo4u3boz8cLz4EdNLmfTtlq+ZUvvbjXDosRAZHW1j00neT3+5 C/4jsUHZC8aLpiAKvy5eS0m/3XJj6NaZtudXELFeNXGVwemvuhxUM3ROoREvHtMR /GV/BZrfuwGR9o98Q1lYAXX1Ryna+/FUHhxtTo3D1DvYN3VJkcxR6U1JFH03mscu 6urohqVTzpUfYCs5lUKQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3texmj5utb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Oct 2023 11:16:01 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 487CE100063; Wed, 4 Oct 2023 11:16:01 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 40F4E22A6DD; Wed, 4 Oct 2023 11:16:01 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 11:16:00 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Andrzej Pietrasiewicz Subject: [PATCH 3/7] dt-bindings: media: Document STM32MP25 VENC video encoder Date: Wed, 4 Oct 2023 11:15:48 +0200 Message-ID: <20231004091552.3531659-4-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> References: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_01,2023-10-02_01,2023-05-22_02 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 04 Oct 2023 02:16:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778815891170037758 X-GMAIL-MSGID: 1778815891170037758 Add STM32MP25 VENC video encoder bindings. Signed-off-by: Hugues Fruchet --- .../bindings/media/st,stm32mp25-venc.yaml | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/st,stm32mp25-venc.yaml diff --git a/Documentation/devicetree/bindings/media/st,stm32mp25-venc.yaml b/Documentation/devicetree/bindings/media/st,stm32mp25-venc.yaml new file mode 100644 index 000000000000..c69e0a34f675 --- /dev/null +++ b/Documentation/devicetree/bindings/media/st,stm32mp25-venc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/st,stm32mp25-venc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 VENC video encoder + +maintainers: + - Hugues Fruchet + +description: + The STMicroelectronics STM32MP25 SOCs embeds a VENC video hardware encoder + peripheral based on Verisilicon VC8000NanoE IP (former Hantro H1). + +properties: + compatible: + const: st,stm32mp25-venc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-names: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + venc: venc@580e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x580e0000 0x800>; + interrupts = ; + interrupt-names = "venc"; + clocks = <&ck_icn_p_venc>; + clock-names = "venc-clk"; + }; From patchwork Wed Oct 4 09:15:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 148192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp2488022rwb; Wed, 4 Oct 2023 02:16:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFbZavVCNckZkBymCgq+HnZxbd+h3nFX0wE9sBQAKMxdggqc5L32wcwZFpUJT3bPa6eyiY/ X-Received: by 2002:a05:6a20:dd9a:b0:167:af7d:9e8c with SMTP id kw26-20020a056a20dd9a00b00167af7d9e8cmr397445pzb.56.1696411010507; Wed, 04 Oct 2023 02:16:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696411010; cv=none; d=google.com; s=arc-20160816; b=p93OLAZWjtBP0rSCcNqnVFvWPKz7Z5tzSsX0Y/S5hdIRTxEDhH+XkRRlkJGyDseUgl zCUB1tYQPLv1Tgqtg/0HM1a9Z7YEzAr7c9Hq+oOLV3+tb8mSaHisRpYlD7F2XRJT0Jpn 2c4TRJY7zKdv1w64Q5n3qWDoMyl/J9qnRdyGLjCaP047gy1NHGXrHNh9oX5JLcdAtNN7 De+VIgDHD5fnRr88ceU8dqZZSGd0cslpBhQLjiaeIc132wMRna89iixU84LH7amcoWpK mh7xpUrKen1GFjhnyZ0XdtJ7ulLtHl9NVfhjZVT7eLWoFIjoa9KtKlXhWYdbynvhLCci H6hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=nQ/JKD64BrKYpkSs5vabcoG9YjS37VBoaLyDwbg3SCI=; fh=ItXiUQa06G5NtzfQ6MBP/cGHELTOauPzcHi5SmTT7Sw=; b=o8Rv8/beIZRuYfiYTYo6mn6Q2D6jA7nrwAnOFF/9G/ErGcGd0UhJ543wJ6UkIgw8MX ee87NbJKqteocbI/Q5E31CdrnKDDJD32Z0BA+7K3Fij1eJ/jDhHolpqCB+7TNCm1irzT +aFTB1bhCn0bVeHDdZHWnJWrj3nhKGpy+fhzEUpq5ofrobt2IANsH4BiyWXDWoCE2O1b caHVk+c+u1fGS+gsYc50IEII5oRAJbqMmNmaldvcCJNJSTpqhNr0ewx8/dohYUrUTx2W 47GekrT8f8G+u227c6ff4KOot30HwVLTz6MmbS1L1z4oe7TRU70hJEnaQMwwVm4nfMV4 8AXg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=AqERI8CW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id l63-20020a638842000000b00578c3b7af9fsi3298970pgd.184.2023.10.04.02.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 02:16:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=AqERI8CW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id A1F3881E9A72; Wed, 4 Oct 2023 02:16:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S242017AbjJDJQn (ORCPT + 18 others); Wed, 4 Oct 2023 05:16:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242003AbjJDJQi (ORCPT ); Wed, 4 Oct 2023 05:16:38 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 77360A6; Wed, 4 Oct 2023 02:16:33 -0700 (PDT) Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 39450HtP026784; Wed, 4 Oct 2023 11:16:03 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=nQ/JKD64BrKYpkSs5vabcoG9YjS37VBoaLyDwbg3SCI=; b=Aq ERI8CW9nwn0lcENfjD6kmthnUa/pim+JrNfoRJrLFUhbMy8WTpmcdyjZLHfdRHhG qHaLaxUjTLJ14kPXe9hSzynWjk8rpD6XSy+qz2ZMd+6BIed8aSDarKi6oMSFTJSh PiVvMYMqNLaPsjNW9pxWORiCOFX2FCVfXmyMhFNWhUSx8yhuvmAGmaZzpMTezfpU ApodSgahWD5YIOL44OquepmGaCOF7j1IYwo+Tly+uAt8tnA6zfFPhMLN2AFfhOAb dclwoxi68lC9bLg9aUU2wJiR/cYBc+Ggnhb71bhQ1M6LG91UiuaZUOJYo3qlmUKG gJl5VVYJaop/giBXBn/Q== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tew80nsdg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Oct 2023 11:16:03 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 23FE6100053; Wed, 4 Oct 2023 11:16:02 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 17F5B22A6DD; Wed, 4 Oct 2023 11:16:02 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 11:16:01 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Andrzej Pietrasiewicz Subject: [PATCH 4/7] media: hantro: add support for STM32MP25 VENC Date: Wed, 4 Oct 2023 11:15:49 +0200 Message-ID: <20231004091552.3531659-5-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> References: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_01,2023-10-02_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 04 Oct 2023 02:16:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778815871468325764 X-GMAIL-MSGID: 1778815871468325764 Add support for STM32MP25 VENC video hardware encoder. JPEG encoding up to 8176x8176. VENC has its own reset/clock/irq. Signed-off-by: Hugues Fruchet --- drivers/media/platform/verisilicon/Makefile | 3 +- .../media/platform/verisilicon/hantro_drv.c | 1 + .../media/platform/verisilicon/hantro_hw.h | 1 + .../platform/verisilicon/stm32mp25_venc_hw.c | 147 ++++++++++++++++++ 4 files changed, 151 insertions(+), 1 deletion(-) create mode 100644 drivers/media/platform/verisilicon/stm32mp25_venc_hw.c diff --git a/drivers/media/platform/verisilicon/Makefile b/drivers/media/platform/verisilicon/Makefile index 5854e0f0dd32..3bf43fdbedc1 100644 --- a/drivers/media/platform/verisilicon/Makefile +++ b/drivers/media/platform/verisilicon/Makefile @@ -41,4 +41,5 @@ hantro-vpu-$(CONFIG_VIDEO_HANTRO_SUNXI) += \ sunxi_vpu_hw.o hantro-vpu-$(CONFIG_VIDEO_HANTRO_STM32MP25) += \ - stm32mp25_vdec_hw.o + stm32mp25_vdec_hw.o \ + stm32mp25_venc_hw.o diff --git a/drivers/media/platform/verisilicon/hantro_drv.c b/drivers/media/platform/verisilicon/hantro_drv.c index 8c6e0c66f0cd..3156aff50eb5 100644 --- a/drivers/media/platform/verisilicon/hantro_drv.c +++ b/drivers/media/platform/verisilicon/hantro_drv.c @@ -735,6 +735,7 @@ static const struct of_device_id of_hantro_match[] = { #endif #ifdef CONFIG_VIDEO_HANTRO_STM32MP25 { .compatible = "st,stm32mp25-vdec", .data = &stm32mp25_vdec_variant, }, + { .compatible = "st,stm32mp25-venc", .data = &stm32mp25_venc_variant, }, #endif { /* sentinel */ } }; diff --git a/drivers/media/platform/verisilicon/hantro_hw.h b/drivers/media/platform/verisilicon/hantro_hw.h index b7eccc1a96fc..70c72e9d11d5 100644 --- a/drivers/media/platform/verisilicon/hantro_hw.h +++ b/drivers/media/platform/verisilicon/hantro_hw.h @@ -407,6 +407,7 @@ extern const struct hantro_variant rk3588_vpu981_variant; extern const struct hantro_variant sama5d4_vdec_variant; extern const struct hantro_variant sunxi_vpu_variant; extern const struct hantro_variant stm32mp25_vdec_variant; +extern const struct hantro_variant stm32mp25_venc_variant; extern const struct hantro_postproc_ops hantro_g1_postproc_ops; extern const struct hantro_postproc_ops hantro_g2_postproc_ops; diff --git a/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c new file mode 100644 index 000000000000..0aac33afcadc --- /dev/null +++ b/drivers/media/platform/verisilicon/stm32mp25_venc_hw.c @@ -0,0 +1,147 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * STM32MP25 VENC video encoder driver + * + * Copyright (C) STMicroelectronics SA 2022 + * Authors: Hugues Fruchet + * for STMicroelectronics. + * + */ + +#include +#include +#include + +#include "hantro.h" +#include "hantro_jpeg.h" +#include "hantro_h1_regs.h" + +/* + * Supported formats. + */ + +static const struct hantro_fmt stm32mp25_venc_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_YUV420M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420P, + .frmsize = { + .min_width = 96, + .max_width = 8176, + .step_width = MB_DIM, + .min_height = 32, + .max_height = 8176, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_NV12M, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUV420SP, + .frmsize = { + .min_width = 96, + .max_width = 8176, + .step_width = MB_DIM, + .min_height = 32, + .max_height = 8176, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_YUYV, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_YUYV422, + .frmsize = { + .min_width = 96, + .max_width = 8176, + .step_width = MB_DIM, + .min_height = 32, + .max_height = 8176, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_UYVY, + .codec_mode = HANTRO_MODE_NONE, + .enc_fmt = ROCKCHIP_VPU_ENC_FMT_UYVY422, + .frmsize = { + .min_width = 96, + .max_width = 8176, + .step_width = MB_DIM, + .min_height = 32, + .max_height = 8176, + .step_height = MB_DIM, + }, + }, + { + .fourcc = V4L2_PIX_FMT_JPEG, + .codec_mode = HANTRO_MODE_JPEG_ENC, + .max_depth = 2, + .header_size = JPEG_HEADER_SIZE, + .frmsize = { + .min_width = 96, + .max_width = 8176, + .step_width = MB_DIM, + .min_height = 32, + .max_height = 8176, + .step_height = MB_DIM, + }, + }, +}; + +static irqreturn_t stm32mp25_venc_irq(int irq, void *dev_id) +{ + struct hantro_dev *vpu = dev_id; + enum vb2_buffer_state state; + u32 status; + + status = vepu_read(vpu, H1_REG_INTERRUPT); + state = (status & H1_REG_INTERRUPT_FRAME_RDY) ? + VB2_BUF_STATE_DONE : VB2_BUF_STATE_ERROR; + + vepu_write(vpu, H1_REG_INTERRUPT_BIT, H1_REG_INTERRUPT); + + hantro_irq_done(vpu, state); + + return IRQ_HANDLED; +} + +static void stm32mp25_venc_reset(struct hantro_ctx *ctx) +{ +} + +/* + * Supported codec ops. + */ + +static const struct hantro_codec_ops stm32mp25_venc_codec_ops[] = { + [HANTRO_MODE_JPEG_ENC] = { + .run = hantro_h1_jpeg_enc_run, + .reset = stm32mp25_venc_reset, + .done = hantro_h1_jpeg_enc_done, + }, +}; + +/* + * Variants. + */ + +static const struct hantro_irq stm32mp25_venc_irqs[] = { + { "venc", stm32mp25_venc_irq }, +}; + +static const char * const stm32mp25_venc_clk_names[] = { + "venc-clk" +}; + +const struct hantro_variant stm32mp25_venc_variant = { + .enc_fmts = stm32mp25_venc_fmts, + .num_enc_fmts = ARRAY_SIZE(stm32mp25_venc_fmts), + .codec = HANTRO_JPEG_ENCODER, + .codec_ops = stm32mp25_venc_codec_ops, + .irqs = stm32mp25_venc_irqs, + .num_irqs = ARRAY_SIZE(stm32mp25_venc_irqs), + .clk_names = stm32mp25_venc_clk_names, + .num_clocks = ARRAY_SIZE(stm32mp25_venc_clk_names) +}; + From patchwork Wed Oct 4 09:15:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 148195 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp2488541rwb; Wed, 4 Oct 2023 02:17:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHWHWMv4k9+uHF39zlTocxqP8vpprEYrWOrbVLpaNaZHtHmArKTkbkoW1tYDcz0Y2pyhL6 X-Received: by 2002:a05:6a20:12c1:b0:154:e7e6:85bd with SMTP id v1-20020a056a2012c100b00154e7e685bdmr2030680pzg.20.1696411071470; Wed, 04 Oct 2023 02:17:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696411071; cv=none; d=google.com; s=arc-20160816; b=bVAhqvwOH09qBgm0jqE08pciXMjhru7GETWIrhlZHr3mJrQXIylSuL9rKBN92w54cY duHmFiXlCjFokS5PRKVB0t7giedBOO3X4vZ79p4hQCkOz21nrAKIjSUbkzF2X2ByjPDk JRFHlkRnKiFD6hspW12wurLVdYVx53o4MNWs4TzMleCx88585ThHb5bw+Mb7G73cRtIc zzWXk7ZFZGa1FD+DOlE8wtM+fo199VKDDXMxaFaG96RVMSqn2TggU7s1wbf8eQOFEzC0 qsG+Ux0DTHiCxHRBVUTqWL3LK6uXvKneO8tm64IZx47zpe0Pbz/la6nUO9JlFxRLV+C0 QreQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ARYkfXru3c0brXdWWVkjAnyorxVN8gvB3OLYyG5N4N8=; fh=ItXiUQa06G5NtzfQ6MBP/cGHELTOauPzcHi5SmTT7Sw=; b=uGnUuFV7eee2LtU5ne/GsYIldmbTOQaPtL9oJrcnEf08RbxDN/fxA4U4AKuVYN7DnO 2hystMLA1FCYI1OrE3snGhu1lTOoEJsnLtJ3Mw/fcpFY0V8zq9vMpOFde2eiCDdbc9Qi uHosm4GCkV05To80Ng8lJnalaHhwoBUOFLKov+sMRUNBJWVJIpoEKqC7jYoZEyS2xELD Zgtem/A83/9LKgiAk6So8sbZgGZ+t3QzDC+11GpSJ8O7xjDkWcCQKolOgTp+Kzno1ni0 1sm1EQhHec0VzhcOgidlSWbDgIEG0we3q+F7n3MXzyrkYe/ZepGaF6Jf1JoEGu+f+FfM XmTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=CZeuqvPc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from lipwig.vger.email (lipwig.vger.email. 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Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index e6fa596211f5..4f2b224fe077 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,4 +6,8 @@ #include "stm32mp253.dtsi" / { + soc@0 { + rifsc: rifsc-bus@42080000 { + }; + }; }; From patchwork Wed Oct 4 09:15:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 148197 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp2488660rwb; Wed, 4 Oct 2023 02:18:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE3SEV4cS3GzI/RvWFk1d6DyMmGDrAKI41K7tVp6zWZ0NrteCdWBd7lUzPi2+wdcJc6XqSZ X-Received: by 2002:a05:6808:f8f:b0:3a7:8e9a:e984 with SMTP id o15-20020a0568080f8f00b003a78e9ae984mr2054081oiw.57.1696411087189; Wed, 04 Oct 2023 02:18:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696411087; cv=none; d=google.com; s=arc-20160816; b=AvIzvmCuXiToY6ZMbcIwckMGeapwiulLJvp9F6EAhlXByVaOuBMEhUAQhOjZf3bsa9 Bdr+bWQx92eQr6NVaBkmyFtfbASpkM8jdSUCFeicFV4UeFj9wtwjoLd3qKm+WEXXDajt N/kN+Yh4tJDVH6rrQ5Y8TePurD7/H40M/9Xq1OECBGunKpxMReKKO4j/1YEUpWqvfgVY Y5Y/z/IM/+wNwng2bchShhyJw+ALBafxP8VERh5ag3xOJZ7iG7r3i8HLQ/qqdXX+zSRh B98KIsrGayPBQicMMnje11tK4f3J2EmZZ+58VbKdrqpTal1QrLFhQTlGuCcWo3hMtlj4 2yag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ea5OiJ9ON12vBbfkNy54tXC0IDhxfzZ9TFeWkUVfTzY=; fh=ItXiUQa06G5NtzfQ6MBP/cGHELTOauPzcHi5SmTT7Sw=; b=fi5D+YFJ65R1nPYEuI9oRiiFR8J/Cw9oxjjHIr4vMIO/Oqr6jNWFCBM6iUK79sqTWP mIhUlHaPz5pbnvSL22zdaauTlEmj5/Z8hh4SmeXkglWmSdldM6FAoCoD6G5gUIjXkxW8 zeR0sSb+Ek97pgIZEPYn7fFFYf5y7QIViTkSewKosn0NNvqayJPeu8yQeZ8YLGmA/YTz JHnvvuk/5cuDdrij1IzNtxlP10tjumbCzPH5Kaoya2dSXdx4sKv7Ft4UOS32Up/i5EZ8 NvgF+CvqU9PI7KA+bjMr1yYynOxnDxXPtB4pcwtRr8tRYKh0aveWxWFDkYS++3GwKi3f I4ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=BpCeNshx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id r27-20020a638f5b000000b005775a0cd009si3424527pgn.331.2023.10.04.02.18.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 02:18:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=BpCeNshx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 57FED81F3330; Wed, 4 Oct 2023 02:18:05 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241908AbjJDJRV (ORCPT + 18 others); Wed, 4 Oct 2023 05:17:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232862AbjJDJRU (ORCPT ); Wed, 4 Oct 2023 05:17:20 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D24CEAF; Wed, 4 Oct 2023 02:17:16 -0700 (PDT) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3945iOOM022001; Wed, 4 Oct 2023 11:17:04 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=ea5OiJ9ON12vBbfkNy54tXC0IDhxfzZ9TFeWkUVfTzY=; b=Bp CeNshxTmQXJ+TECc/X+BSOla0/oT8MMmHcSQoDxxa41X1nMVukezWhetPHT1FyB3 ZGInwCsWdXgyMnBAqi2OaXOEImaHtDNYPeBzvyskwaf9v6Uo+BRnlNIruXbZQ1lH cLL0y6cAS++ETKoxA2LZBkDyeXnbTBeRs0e6PSe9w7F8HWc8oID00hDLAHIbZT+r ZkwiNK2HY+KEzp/4yF8jtPzwBURDEZvF81AXgfPOKCB2RpmsF9bdcKGF+XDRjo8d zn/Ri4z992i6xkcote6BUc16vS4x/ImPe0GTHs7ds1JR8HanSO6pCu+Jn7/CqTuf KrC444TxsVwUE9n3aUmw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3teajd04xf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Oct 2023 11:17:04 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 9C2CC100057; Wed, 4 Oct 2023 11:17:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 945FF22A6DF; Wed, 4 Oct 2023 11:17:03 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 11:17:03 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Andrzej Pietrasiewicz Subject: [PATCH 6/7] arm64: dts: st: add video decoder support to stm32mp255 Date: Wed, 4 Oct 2023 11:15:51 +0200 Message-ID: <20231004091552.3531659-7-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> References: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_01,2023-10-02_01,2023-05-22_02 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 04 Oct 2023 02:18:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778815951852679496 X-GMAIL-MSGID: 1778815951852679496 Add VDEC hardware video decoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 8 ++++++++ 2 files changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 5268a4321841..0ca421ede0ae 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -46,6 +46,12 @@ ck_icn_ls_mcu: ck-icn-ls-mcu { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_vdec: ck-icn-p-vdec { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 4f2b224fe077..105ef2d71c77 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -8,6 +8,14 @@ / { soc@0 { rifsc: rifsc-bus@42080000 { + vdec: vdec@480d0000 { + compatible = "st,stm32mp25-vdec"; + reg = <0x480d0000 0x3c8>; + interrupts = ; + interrupt-names = "vdec"; + clocks = <&ck_icn_p_vdec>; + clock-names = "vdec-clk"; + }; }; }; }; From patchwork Wed Oct 4 09:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues Fruchet X-Patchwork-Id: 148196 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6359:6f87:b0:13f:353d:d1ed with SMTP id tl7csp2488571rwb; Wed, 4 Oct 2023 02:17:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFAHZoman/R0KIlqZr3gRNZPlDx7X03vTEybnAfVQTA8Xyg4ez3cSRGB5tQn7TC2IOKSFua X-Received: by 2002:a05:6a21:778b:b0:164:1ad3:4325 with SMTP id bd11-20020a056a21778b00b001641ad34325mr1732110pzc.44.1696411075348; Wed, 04 Oct 2023 02:17:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696411075; cv=none; d=google.com; s=arc-20160816; b=d+KoYXiIqAgECfUqcoJy9KKL+zyYgpBN7oiqSLv3Xx75KZbmcJNUfjexq3qHM179aj NjciNr+Bg1V3jI3V6BRvE2YN25ep8anrC8b7/BS3WvyIGDGrXRDb9Fx6TJ2Prj4w+Z5E yzs9st9+Uw8FBnoqTQdfotKV6UoUg/SAqaokXhQv1CsLUoAHlasJqbsJVhhUnOKft8p6 WulApWqnPh6kuoN1gL81HSHcauCTYy8GYTEpRu5dHBjr0MWPWoEzdgdmCEuwN8uY5sXr V79+1D9oWz1izonD5Sojzf1QRv67mS0BPOKxbJPmEOWLPIvCeV1xWrhKLvLh66hsZ87V GuqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zPxEJTuK+kiMe3ysiXBDz8ownZu5ZyU8DDfCrL1/OG8=; fh=ItXiUQa06G5NtzfQ6MBP/cGHELTOauPzcHi5SmTT7Sw=; b=KeVXthCeTaTABuYJnai/CSFu795y4vf0ILtkokz13FgiYWNKD9DIWJMN2N5MIP1Omx XEjF5Od34VKNBlMG0zPR+B84D8dVJICcDwKw7/wqfk8XoNz3JQzzjMCDhITy2gYvUYdx F/HSJ7MMisuRdB/EqNiFrkSDnKSiBodxkBrQ1z2YJJkROF3j92g67SSA/WosqDBeOcvH rJDSAymjPZgRb5dQayvNXfkx28M3Z9TkfPMHQ1BrevAlS8uKi3MIzCnmXoj+ojSd6h2b QLSq+DPYt61BlylqFFpAbmUBbZId+KEeRlv8ThL9+hC39KOnMJwO+Lki66fZoUbw2pF7 nDMQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=S7icmURj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id ea13-20020a056a004c0d00b00691004e7db0si3209093pfb.170.2023.10.04.02.17.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Oct 2023 02:17:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=S7icmURj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 73CAA825ED8C; Wed, 4 Oct 2023 02:17:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241966AbjJDJRf (ORCPT + 18 others); Wed, 4 Oct 2023 05:17:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52664 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242085AbjJDJRb (ORCPT ); Wed, 4 Oct 2023 05:17:31 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA33DC; Wed, 4 Oct 2023 02:17:27 -0700 (PDT) Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 3944WErR012638; Wed, 4 Oct 2023 11:17:05 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=zPxEJTuK+kiMe3ysiXBDz8ownZu5ZyU8DDfCrL1/OG8=; b=S7 icmURj4QWaplVShDhVaxxQ2uDPz6RNSvoC+otwwTGqml9itSRn259wdynQLrGa8J 7vP/T5zo/pB8vSQgbmSHceUgNWAvhkonszlhi4U4kl0KIfpioCKaWHYxjoZyJvVA IcgUBCQcUv/xw4Qp+cAsO9OEMt6/rzCNpfwSqSjOJYNUQ0vetSIDM404/Tq3tblA WbtStsiAQ/j5UsYMRJR8cVNcUJ1hFjLW8X7JQc3IA14VDOZ0Q60z+FA5mjU3uIZ6 /DEMaYpUiKzfij8mcpVrGpfc5yg0qTUdfKvhX0vYNb2sGbAcG36dZ+anM9N+nwdv 3CkW9JSCE9+3S9wv6QUg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3te93g08jv-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 04 Oct 2023 11:17:05 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 4C607100053; Wed, 4 Oct 2023 11:17:04 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 4381022A6DA; Wed, 4 Oct 2023 11:17:04 +0200 (CEST) Received: from localhost (10.201.20.120) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Wed, 4 Oct 2023 11:17:04 +0200 From: Hugues Fruchet To: Ezequiel Garcia , Philipp Zabel , Mauro Carvalho Chehab , Hans Verkuil , , Maxime Coquelin , Alexandre Torgue , , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , CC: Hugues Fruchet , Andrzej Pietrasiewicz Subject: [PATCH 7/7] arm64: dts: st: add video encoder support to stm32mp255 Date: Wed, 4 Oct 2023 11:15:52 +0200 Message-ID: <20231004091552.3531659-8-hugues.fruchet@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> References: <20231004091552.3531659-1-hugues.fruchet@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.20.120] X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-04_01,2023-10-02_01,2023-05-22_02 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 04 Oct 2023 02:17:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778815939764891936 X-GMAIL-MSGID: 1778815939764891936 Add VENC hardware video encoder support to STM32MP255. Signed-off-by: Hugues Fruchet --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi index 0ca421ede0ae..2aff746968f5 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ ck_icn_p_vdec: ck-icn-p-vdec { compatible = "fixed-clock"; clock-frequency = <200000000>; }; + + ck_icn_p_venc: ck-icn-p-venc { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; }; firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi index 105ef2d71c77..0035fbf5e17d 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -16,6 +16,15 @@ vdec: vdec@480d0000 { clocks = <&ck_icn_p_vdec>; clock-names = "vdec-clk"; }; + + venc: venc@480e0000 { + compatible = "st,stm32mp25-venc"; + reg = <0x480e0000 0x800>; + interrupt-names = "venc"; + interrupts = ; + clock-names = "venc-clk"; + clocks = <&ck_icn_ls_mcu>; + }; }; }; };