From patchwork Wed Oct 4 06:35:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 148156 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp2562407vqb; Tue, 3 Oct 2023 23:37:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFZoRWMSuK0Tkxj+/a7MPitRf0TtznrU8ejD+nLqUsM/fWnCLU5PYxppmh/g6ctO+Q7jxvz X-Received: by 2002:a9d:6a50:0:b0:6c4:f91d:2d9c with SMTP id h16-20020a9d6a50000000b006c4f91d2d9cmr1324091otn.23.1696401465610; Tue, 03 Oct 2023 23:37:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696401465; cv=none; d=google.com; s=arc-20160816; b=Aidz1/58pj3cBJNFdu3ltgyHlqysUi7f5CRFVJyboGyjJbmGMAVZSRG/B50sNx+PT4 PCIgvrdonSfJH0zvXVmE/Q7+izQfwVNEQkaITTLkkNZO2QBhOe3CH+o5imCXeR+Yiygn DmNeVqU+nWi6X/MDLC/NBh5tWIGYH0qIPgYCYc7QEdUf7NV8lX97sCxqjtuqZqOqLRZ3 1NRa9wvWLJyuxhMnpcXPtYneZMJNg7EzKOTFTSLZovmJPysIqPZbmxD0r/4eYdJim+hE BrHqlCRwPlj0RVGmomUm4HSEIXq6fyoF3cOXIfJ2MDydeVCLwYGTvrYzbSojD0e2w8en jusA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=OYKY9mFmL0eJ6Vii+DUBC2q4iHATJVweYT3mzBHdRNo=; fh=WjOiB1ucdy3BwrOlmlBmr7zpAZvANY2hXMFm0rTH090=; b=KQvugdNoAOmykslnPuol6hqRtSyMjYUldIB6WpQlYJSrRSVpQN8OQMZ+JcuwGsqZJK 0UQywooVCk1O/gLOH0+dOj4czq9bYPDA+NvhM6jX+HgtU1gVC+17hj3WjXillyCtPCHl VLFFPgNZwLkKZ+k5kHn8GylJ8YFRauut1lmwPRIk9eDdnALndQgiN02lq40E+5Xj66it QAMWg+44ZzhVlGMnJZ4cAOXIvFHE/LSzU+J+nK4+Ki1NX1aarDqldRt3Zfagl3lSmcBB ULUqpowWt9TSOUhG0rbRuBhatVTZMAYl8b8o4rK5oYzijbWw9bR2v2Jzlryayrmsxl6S n4eQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=iKrxyTwH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id e124-20020a636982000000b00578a7f5a0b2si3023981pgc.403.2023.10.03.23.37.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=iKrxyTwH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id EF16E81CC86E; Tue, 3 Oct 2023 23:37:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241429AbjJDGhk (ORCPT + 17 others); Wed, 4 Oct 2023 02:37:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54996 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241415AbjJDGhj (ORCPT ); Wed, 4 Oct 2023 02:37:39 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C6857AF for ; Tue, 3 Oct 2023 23:37:34 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-9adb9fa7200so127080566b.0 for ; Tue, 03 Oct 2023 23:37:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401453; x=1697006253; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OYKY9mFmL0eJ6Vii+DUBC2q4iHATJVweYT3mzBHdRNo=; b=iKrxyTwHsPTwXH3vxBl3LW0W/G5L1R+MW2SQCA6gx7mZDt094h06zefg/Hsr3aY7lB fUzwwmfaeCo0QLi5biJjGUnSul2O8QnIaNumwmzHFjO6bJVSh0hA2JUbepeXQPnbHK6p OS47pGoWpI1EHp/3ldLl1EjFhc+ZjEk+ZfC8X8R54GQo/omfVZBZjndg6/giwYsSog9g dBsUg9BuBZXzk2Jf1nI2eAOB5xhjEtggk5u9CqSqu4GBjfGN/7cH+DvA46LrkvdZ1BtR ClYUnjBUVELUHolIF+cbPKlDH0HLcY3tVq+Qvr80d9wTRFehgdWcaBKrTXDgd35rXJmw PZDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401453; x=1697006253; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OYKY9mFmL0eJ6Vii+DUBC2q4iHATJVweYT3mzBHdRNo=; b=I4516RwUbFhdmvr+zoUBK22JZbIOWUKRbpT+FKEnkMQ3eIIkUsHIvskpWYGIxXCq2g vo6GmZs+BtG5RkYeHy+d6/thcldsfMVb5PUONObVuo8eoOFSxraOZ5tIGMJbY0gXXqnW UI5E1ipTkeS5yBLPHmxjEhMaaIw+pOrH2ro3uTUE2i1zWpnkdASe2JbAJ6CwqR06qoGv gTi0vqnC905o9z1q0nX/DaUrDbcg0Yq+lpPoq0bNfYaRxTxad2q1D78RMO5HT6pdO+lY i1RGVRn5tEeNqOqaUzDJqs9dmmPy5EgP8xi83noeUOx9T7thAftJnN6yZcnNbM7KBw7r BSSA== X-Gm-Message-State: AOJu0YzxUtlsSO3La17pG9YAElWYooyWyXShPLi8grmCOBLfLeDDDYrH 0lzxJXoE+w1jqjPDeacsqdMygQ== X-Received: by 2002:a17:906:5e:b0:9a9:f0e6:904e with SMTP id 30-20020a170906005e00b009a9f0e6904emr1201861ejg.16.1696401452905; Tue, 03 Oct 2023 23:37:32 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:32 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/4] dt-bindings: clock: si5351: convert to yaml Date: Wed, 4 Oct 2023 08:35:27 +0200 Message-ID: <20231004063712.3348978-2-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 03 Oct 2023 23:37:45 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778805863294035933 X-GMAIL-MSGID: 1778805863294035933 From: Alvin Šipraga The following additional properties are described: - clock-names - clock-frequency of the clkout child nodes In order to suppress warnings from the DT schema validator, the clkout child nodes are prescribed names clkout@[0-7] rather than clkout[0-7]. The latter form is still admissible but the example has been changed to use the former. The example is refined as follows: - correct the usage of property pll-master -> silabs,pll-master - give an example of how the silabs,pll-reset property can be used I made myself maintainer of the file as I cannot presume that anybody else wants the responsibility. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.txt | 126 --------- .../bindings/clock/silabs,si5351.yaml | 253 ++++++++++++++++++ 2 files changed, 253 insertions(+), 126 deletions(-) delete mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.txt create mode 100644 Documentation/devicetree/bindings/clock/silabs,si5351.yaml diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index bfda6af76bee..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml new file mode 100644 index 000000000000..400c8cec2a3a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -0,0 +1,253 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5351A/B/C programmable I2C clock generators + +description: | + The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to + 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 + output clocks are accessible. The internal structure of the clock generators + can be found in [1]. + + [1] Si5351A/B/C Data Sheet + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf + +maintainers: + - Alvin Šipraga + +properties: + compatible: + enum: + - silabs,si5351a # Si5351A, 20-QFN package + - silabs,si5351a-msop # Si5351A, 10-MSOP package + - silabs,si5351b # Si5351B, 20-QFN package + - silabs,si5351c # Si5351C, 20-QFN package + + reg: + enum: + - 0x60 + - 0x61 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + + silabs,pll-source: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of cell pairs containing a PLL index and its source. Allows to + overwrite clock source of the internal PLLs. + minItems: 1 + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). + enum: [ 0, 1 ] + +patternProperties: + "^clkout@[0-7]$": + type: object + + properties: + reg: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Clock output number. + + clock-frequency: true + + silabs,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Source clock of the this output's divider stage. + + 0 - use multisynth N for this output, where N is the output number + 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4 + (otherwise) for this output + 2 - use XTAL for this output + 3 - use CLKIN for this output (Si5351C only) + + silabs,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8 ] + description: Output drive strength in mA. + + silabs,multisynth-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: | + Source PLL A (0) or B (1) for the corresponding multisynth divider. + + silabs,pll-master: + type: boolean + description: | + The frequency of the source PLL is allowed to be changed by the + multisynth when setting the rate of this clock output. + + silabs,pll-reset: + type: boolean + description: Reset the source PLL when enabling this clock output. + + silabs,disable-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + Clock output disable state. The state can be one of: + + 0 - clock output is driven LOW when disabled + 1 - clock output is driven HIGH when disabled + 2 - clock output is FLOATING (HIGH-Z) when disabled + 3 - clock output is never disabled + + allOf: + - if: + properties: + compatible: + contains: + const: silabs,si5351a-msop + then: + properties: + reg: + minimum: 0 + maximum: 2 + else: + properties: + reg: + minimum: 0 + maximum: 7 + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + silabs,clock-source: + enum: [ 0, 1, 2, 3 ] + else: + properties: + silabs,clock-source: + enum: [ 0, 1, 2 ] + required: + - reg + + additionalProperties: false + +allOf: + - $ref: /schemas/clock/clock.yaml + - if: + properties: + compatible: + contains: + enum: + - silabs,si5351a + - silabs,si5351a-msop + - silabs,si5351b + then: + properties: + clocks: + minItems: 1 + maxItems: 1 + clock-names: + items: + - const: xtal + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + clocks: + minItems: 1 + maxItems: 2 + clock-names: + minItems: 1 + items: + - const: xtal + - const: clkin + +required: + - reg + - "#address-cells" + - "#size-cells" + - "#clock-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* Connect XTAL input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* Use XTAL input as source of PLL0 and PLL1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* + * Overwrite CLK0 configuration with: + * - 8 mA output drive strength + * - PLL0 as clock source of multisynth 0 + * - Multisynth 0 as clock source of output divider + * - Multisynth 0 can change PLL0 + * - Set initial clock frequency of 74.25MHz + */ + clkout@0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * Overwrite CLK1 configuration with: + * - 4 mA output drive strength + * - PLL1 as clock source of multisynth 1 + * - Multisynth 1 as clock source of output divider + * - Multisynth 1 can change PLL1 + * - Reset PLL1 when enabling this clock output + */ + clkout@1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + silabs,pll-reset; + }; + + /* + * Overwrite CLK2 configuration with: + * - XTAL as clock source of output divider + */ + clkout@2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; + }; From patchwork Wed Oct 4 06:35:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 148157 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp2562421vqb; Tue, 3 Oct 2023 23:37:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGMdKQsldMn+urCXbWiPkOwbngl3HkuZdI5h3nDOgZdujzaE6Q9zvfCvOumDWtyMW6xyfDW X-Received: by 2002:a05:6808:2224:b0:3a9:bb08:d468 with SMTP id bd36-20020a056808222400b003a9bb08d468mr2034327oib.55.1696401467984; Tue, 03 Oct 2023 23:37:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696401467; cv=none; d=google.com; s=arc-20160816; b=pi171g3tGDb0Wocx3UCyjfZ96OP0PDrVk3X8tq3T/AXrzMYhO6aQTnPyTUkDW0UCta Np5KBJJj2BHV5NqIxEiu1mjOjBJyxxzEdK8qU6WmhQWJSkP/sYzlS2zdM2ff9cCFVYs6 WUyfS/QCcMbBuuRAM9C+MjRyDWuhZ+q9cOVnAQHqGE7/TC8OpAyEurB8aFzjDd0yEo3z cmS/OXZ9CoX6YrAKDbqKd4jNSnVtvY6/JmaHef3ruNgDcna8KwA+0wK1GIoD7Gj8Ec11 EJyBzB16EZ/gdDoDJHmN9ellYP+07Nj/h8h8B2dG0opY4McCTHMNP6qQS9I/MjJAZeVE 9s9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; fh=WWbya8/AwZn6jVUNOIOpUKaA+yAGZ+FjHmGfOgBaeig=; b=su9nETXtGawG9HQQS+P4dXCCvJQabkZQKCwpurXgIQkagvcVUSkII5UIlA3NDTyQOA gV4AbObiZsJL7b4izd+44VBA8mRtp5zJbhya+FTnpzzg5mDRC9oAK8/avWAHaoDjIznW qSw/i9tOf4wrTK7e1xWWDPqD/iNPDrbk+tkY88JJd0CPzsyLPwVueyM3KTBaubvYoqTX zSxymDK4QGb0Lwa23Q5X2h3lGHh+sDF2yap6PCBuAi2ZHhP7+WcK3/irPqtmZ8unxgj7 4AtPA6cdKPg5D5IPrjOjzesTo8xGsLtB0TKB5eGxHa3w0m5DtfrAI39bQyqAIOBq//L4 GP4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=J1h+REUP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id d3-20020a633603000000b005859c29ce86si3091138pga.84.2023.10.03.23.37.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=J1h+REUP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 515B081CC864; Tue, 3 Oct 2023 23:37:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241404AbjJDGhn (ORCPT + 17 others); Wed, 4 Oct 2023 02:37:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241426AbjJDGhk (ORCPT ); Wed, 4 Oct 2023 02:37:40 -0400 Received: from mail-ed1-x534.google.com (mail-ed1-x534.google.com [IPv6:2a00:1450:4864:20::534]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A5AFAD for ; Tue, 3 Oct 2023 23:37:37 -0700 (PDT) Received: by mail-ed1-x534.google.com with SMTP id 4fb4d7f45d1cf-5363227cc80so2887392a12.3 for ; Tue, 03 Oct 2023 23:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401455; x=1697006255; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; b=J1h+REUPf/DWpLP0Tx+f7HWOn5cab89djUvdMpb94WvRETFjFD5/BHGVWaKX0+viTe jkpU9CHvkUpkwxYJUAiGiz2ORgpMhCkSvY5+bAtcSspZ0MniNP8HBwuWEre9TmKc9lVz rT+86CZugEyKl3KiLXlv+5Tlzwnglrf2PNu1O4M5iRsWgyQkLOFMBnps+3ix8XfsTN3W xDL14VmvYo1CbZEpgAwNNKKvOiHEoXix4njYSrBvUhwM0cnnKAZNw7I/W4Hq36OwMCD3 wRvMKnlt5SdzeZOPPSM4ZWjwRYWT/MaEr9OkiZ2KOCAZVhZWY6U2c8HBfXNGQrgU30BE EcBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401455; x=1697006255; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=p7tjP/kNvFdirVdEdO+zKKMbLGQyGDvV/p73al1OJ6o=; b=ZQEArHoiD/kwTE86fm6syJfIyKaQd2KEObADOkNt2zmnu7Fox857XG4LfuAfIecVNg TsoRYmuosGkru79GaVNipCOghM8BvpQpXFmzPqmG/NbSWgdnEVeyzHRppNUJDjRRUkWC Cezt7TG48a+N/DB+4zCoHfSH7KOxHUp9WDqMAvCnxKFPiMgJ8az7Lmp5vhmSGfZh9TU6 4Q02Y30W+jPUvZRrD7lywttaLoFlQAAxbuh85GJxDe7ZeIGXttXHcLyJRCjLJ51rMDVJ 3p3PDtx0ywpv8mJMhVyP5FA0IxW0bRWVrFJvvLFqAEEprsRiTKaceAjsMx/MLF+HK6MK S01A== X-Gm-Message-State: AOJu0YyFejvq/t5mgpiIA5JqEKgLl4jQ/ksC26BKfI8XDO5DPyC0zkjL 8hRc8inUXJYO64ScZXn2kb1nBQ== X-Received: by 2002:a17:907:d047:b0:9ae:6744:4591 with SMTP id vb7-20020a170907d04700b009ae67444591mr1105255ejc.43.1696401455571; Tue, 03 Oct 2023 23:37:35 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:35 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rob Herring , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/4] ARM: dts: dove-cubox: fix si5351 node names Date: Wed, 4 Oct 2023 08:35:28 +0200 Message-ID: <20231004063712.3348978-3-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 03 Oct 2023 23:37:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778805866080567034 X-GMAIL-MSGID: 1778805866080567034 From: Alvin Šipraga Correct the device tree to conform with the bindings. The node name and index should be separated with an @. Suggested-by: Rob Herring Signed-off-by: Alvin Šipraga --- arch/arm/boot/dts/marvell/dove-cubox.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/marvell/dove-cubox.dts b/arch/arm/boot/dts/marvell/dove-cubox.dts index bfde99486a87..bcaaf8320c45 100644 --- a/arch/arm/boot/dts/marvell/dove-cubox.dts +++ b/arch/arm/boot/dts/marvell/dove-cubox.dts @@ -101,7 +101,7 @@ si5351: clock-generator@60 { /* connect xtal input as source of pll0 and pll1 */ silabs,pll-source = <0 0>, <1 0>; - clkout0 { + clkout@0 { reg = <0>; silabs,drive-strength = <8>; silabs,multisynth-source = <0>; @@ -109,7 +109,7 @@ clkout0 { silabs,pll-master; }; - clkout2 { + clkout@2 { reg = <2>; silabs,drive-strength = <8>; silabs,multisynth-source = <1>; From patchwork Wed Oct 4 06:35:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 148159 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp2562761vqb; Tue, 3 Oct 2023 23:38:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH5/o/4EQ3MYZv5aCOtojw2IedQurQmqLpqWc3RUypBqW8tNWV2g1cJxyB5v7kFBr2qHRPs X-Received: by 2002:a05:6358:440a:b0:135:3f5c:9675 with SMTP id z10-20020a056358440a00b001353f5c9675mr1518821rwc.19.1696401519613; Tue, 03 Oct 2023 23:38:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696401519; cv=none; d=google.com; s=arc-20160816; b=PFD7q6ZIB7Q8NKxMQ9ZIwWnwkQNL6Ug2B69LaZX1Z5H9ElSEjMilo78/rProCh6cqZ PNWzy7/+x+fK0dkKjtqA182+9PZlwaMeEgJBWMQo2x+RawBU7qsurjAPQofSMeu7jt8j mVksnht7ZJCAcyzxJIcULNN+GpUh8oECBfTW6stptaylVR/isX99d7NYd9c4GfS3DbKh /4vy7eulaxUq+qQDpzA3iQy4vaTKw5uvRli3nR+LObhLc4KUoLhXO0OF8bC/ZH0fVfXN 3+A88oqcwsrMd2CYd448ZcBVhPmQpZkkRpUg09T8IGp7vJR9bfH646/mAhXv0eDcv20D O7Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+QGSDNn6mvgk3D6FylGr3G9S7gB7eM4JL0YqBrEuXRo=; fh=N5/4ewJCpCFzqRLisDyJ16jMci52tYQcEjnFb7d76uE=; b=kafT2pYHP2jWYukyXQQMdvUn9TACtgYYiwNl6ffUBG5HnbF5CNFKAfsL3+PhOLuOxY 4KDg1jcPwZ8sK7mCEWjKsRvzP4DQCiY+1N2Trzb5nwMXPFtIETsdjegCTlV55CPpKBuX psQ3ru7p751xzsUltHRXEcsa6BxEB5xar31lw+S9eRyPpB5vrQeVsK/3OKGXnkgw3Wh/ CVfRGZ1FuPjI9OMxRNTjQ7rrbMbaxs8HCVf3UHwMIv4DD1ygE6D8PLJltMZ9+ficn4tr KkHht2UrvQXypik7qlgoB91NvjqHKj9u7yeBTfP98ZFhtBz16ozIunpapWOTz/Z8Zr3h 35hQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=cgmX09qu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id 19-20020a630c53000000b0054fbd904b6dsi3108538pgm.500.2023.10.03.23.38.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:38:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=cgmX09qu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 85B9C819E144; Tue, 3 Oct 2023 23:38:37 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232720AbjJDGhu (ORCPT + 17 others); Wed, 4 Oct 2023 02:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55044 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241434AbjJDGhm (ORCPT ); Wed, 4 Oct 2023 02:37:42 -0400 Received: from mail-ed1-x533.google.com (mail-ed1-x533.google.com [IPv6:2a00:1450:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73594AF for ; Tue, 3 Oct 2023 23:37:39 -0700 (PDT) Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-53639fb0ba4so3052914a12.0 for ; Tue, 03 Oct 2023 23:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401458; x=1697006258; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+QGSDNn6mvgk3D6FylGr3G9S7gB7eM4JL0YqBrEuXRo=; b=cgmX09quanarZet8h2P8+bVl4u5yT293Uyg+CS01qEtYIdB5Ll1Uoylfwku5GapOAF iSvfccmHbYCWkAxZPpbNsqdK1CWQO9Wa+FNGWRamNFwLI+9W3uY/ErB93u4MhKZWV9MT NxxVZH0pHIoajQZrrcC/kGxr0lhUB6JhzrAD1iqfjWXh9RV6WK06rRDBHYkGxzJuB5t/ Yb2ZkODMkoX6RlXdhRTaiN4XNDtQ4f9V0RMPnS2X/qqlET8ZFSSvf8RzBD8PdShRBwFZ pX0beRB3nQIJd0Mx4FzrU9NBNGlAoLqsglGCwY7ljeZnUDKXOXQPN6qbUWMl6X1H7ybf ojYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401458; x=1697006258; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+QGSDNn6mvgk3D6FylGr3G9S7gB7eM4JL0YqBrEuXRo=; b=dGoWRWPgQDuqg32ZPsMYX9Hxh9LjiDqqyB/kdvSZkYtwc8kAb8/QcOlF2euG20N1dr EiB3GZx4s6tudhkmu1u5tojxTcfFAKMcm2Gq88ZAZgMTrluVrA2p+R/xThPz0/cRNKGj iImqDrVTerCw64i5X1QFn1VmJXs3mSJTeYLeG2Lpnp6zQIY6K/K1UJY662Nfv7w2UVxu Z067QHxMGPRkQb6XviTINwN8Om7soz3x7guzeofl8n/zpgFdKzeNWWB8Ecc6dyF0qlpO sQYeJG7rRQLZCeJ3UHLAqE77W8wShPv2dnEK0jGKX53vzNc7tQvotZmd/oRLh5w8Thub zgig== X-Gm-Message-State: AOJu0Yw47ymQyA1FT00h/ckTseP6LbsHpzjgTWJohSUJwsz0jiTrZhA1 G0Pr8oa7RNRsVxJtkn5HGgd5eQ== X-Received: by 2002:a17:906:7492:b0:9b2:d018:20b2 with SMTP id e18-20020a170906749200b009b2d01820b2mr1372868ejl.39.1696401458083; Tue, 03 Oct 2023 23:37:38 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:37 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 3/4] dt-bindings: clock: si5351: add PLL reset mode property Date: Wed, 4 Oct 2023 08:35:29 +0200 Message-ID: <20231004063712.3348978-4-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 03 Oct 2023 23:38:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778805919737005743 X-GMAIL-MSGID: 1778805919737005743 From: Alvin Šipraga For applications where the PLL must be adjusted without glitches in the clock output(s), a new silabs,pll-reset-mode property is added. It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga --- .../bindings/clock/silabs,si5351.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml index 400c8cec2a3a..f1be09b5c48c 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -53,6 +53,27 @@ properties: - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). enum: [ 0, 1 ] + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + description: | + A list of cell pairs containing a PLL index and its reset mode. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: | + Reset mode for the PLL. Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is + specified in one of the clock output child nodes that also sources + the PLL. This mode may be preferable if output clocks are expected + to be adjusted without glitches. + enum: [ 0, 1 ] + patternProperties: "^clkout@[0-7]$": type: object @@ -207,6 +228,9 @@ examples: /* Use XTAL input as source of PLL0 and PLL1 */ silabs,pll-source = <0 0>, <1 0>; + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode = <1 1>; + /* * Overwrite CLK0 configuration with: * - 8 mA output drive strength From patchwork Wed Oct 4 06:35:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 148158 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp2562484vqb; Tue, 3 Oct 2023 23:37:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHcLMPQMQMOZWsAWBpiBJ+ri/GYAUwtWbIZNIJAKLskByfyAPYNit3/K57CPMi7WuEyhuSJ X-Received: by 2002:a05:6870:b152:b0:1dc:884a:95c1 with SMTP id a18-20020a056870b15200b001dc884a95c1mr1919111oal.44.1696401477915; Tue, 03 Oct 2023 23:37:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696401477; cv=none; d=google.com; s=arc-20160816; b=Me/JqOF870AWEZEblImruKQiasGgVDoOuiQZ33xJG/tTohdtLeYU5+PcVFAHAIjjqD jZ3obi0lZ8tD5E3nWSCWGLNbQLt7t73xR42vFweZQxgU814WEkPf6B6zXOBE86zz/NWn UKDimIHusoLNjBDa9Clm2dQe9c7FAwPmreVqTkZ6ZqR4w/6SEvr0j8Wu6oRbvRBEGVvp PswdofX818ncKeIKZFLLz6wnwHa1ifdgEmbkHxpPSHxRgzRhqQUrgArZ9WJwO+AKqdq8 d0A4FpYSthIPR4K/6OVyvpLfDqUhc2565oqktesOM/pRhsxf5sbpmv+iY0DWx8at6XjO exeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+rE6XvlSeUckpfUomIWf/ozKzyY+JN+wOSM6QZFHuwo=; fh=N5/4ewJCpCFzqRLisDyJ16jMci52tYQcEjnFb7d76uE=; b=k7ebTthE1GjbO44K03+mz6LKVEJKd0cXKjSIKs5Z8UW8jv72eKirzdE6OWD1N92GUc xiu8FSgaMVESJQ8Sk3RMvJfxe+vPj5xmXNFhwX4OQpwLBM3LHNU3Diltbt4RNqCqoi4p HGGqh63/FVfjc8Mod317tF7LMFGRfWbWY0d+qU5rbyBf1qYYVj0i1pLdQg7fv9X2dYCR CL1wBSd7K6KdVcsEisVZDfQlfZ2VcvbBPQhUGh+V2azmcIbiYa6pSkXRccxydifM38zo UuXSOxhHW5aYkUm3WsDVhnE41JVcM8tW4SgAP8W7lBDafVwbGCIayyghX1x2XOXwSGR2 fKJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=fcVpznuk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id y12-20020a62ce0c000000b006930471d220si2885023pfg.397.2023.10.03.23.37.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=fcVpznuk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 0331881CE107; Tue, 3 Oct 2023 23:37:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241418AbjJDGhw (ORCPT + 17 others); Wed, 4 Oct 2023 02:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241398AbjJDGht (ORCPT ); Wed, 4 Oct 2023 02:37:49 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4A4BBB7 for ; Tue, 3 Oct 2023 23:37:42 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-99c136ee106so312075766b.1 for ; Tue, 03 Oct 2023 23:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=pqrs.dk; s=google; t=1696401461; x=1697006261; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+rE6XvlSeUckpfUomIWf/ozKzyY+JN+wOSM6QZFHuwo=; b=fcVpznuki7i8t50+t0Y7Jji+pu/tEbw8YZxSfI/mx5ZR8C9wz0uS9M74V+j+oFg5kg RWnEUDePJYVXxyh/Jsk7reHDB2hoG8Eq+lO21dZX0eVk93WLT7uB69m1Dgj/yGGs2QMr GBZ0dOf8CfqX1Jse/fekrOOZdKb8RPmvJpWI1/SDLEpCRcd9jnFO0WeuQK7SAIfMXWuT 85HWCyvWlo142VpoRyuO8BdWa7kO5Go3AHUdRLIBTUm3+jntIg5EtRN0OmqCChOuyq51 3wm9mFL9QYGOP0CuTR6esQBSTIQq8HcHbElJGhm6OuUMkvMA31wK8zVb4I4pwv/iw12I 2p+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696401461; x=1697006261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+rE6XvlSeUckpfUomIWf/ozKzyY+JN+wOSM6QZFHuwo=; b=KViGbNrG0CnM8DfAD8UqLUsjGTwaQDdgp8v+WjTdNAdYxFZ1zYy2tGxa+H3yE7pJuf +xIP63kEulSE3Oqo3t7X9wGMAVCeynXddZaLbRmU3BsNWbeesGGZc2opxAey0h+G0ECt EAV/bYPvez2xgaIkiH6gFeFLVnV4932RfsN1IkwI4QiQjr7WatVwhg79OR4EjAl1OjlZ mnrAA0IRSIBld3TFyDxBnnqTD8Ta/YMfCHc9krILgfOQ4hE9CbngbafkSBnyULWOXsr+ TyrKvxMGgbYkAhyhZuqxY6Jh2Ck4vxRc6hNtg0VupLRRQ8JgE4NsKmfjP0O1pIky05N3 I9XQ== X-Gm-Message-State: AOJu0Yxi454kIwRlFwY+7PadxcZs8hTJOnayZbbLMpLfUfvlpqu3t5aN IXHq6xJQYV6xfZ7nnbcXS79NHw== X-Received: by 2002:a17:906:5341:b0:9b8:7709:6360 with SMTP id j1-20020a170906534100b009b877096360mr1121607ejo.40.1696401460849; Tue, 03 Oct 2023 23:37:40 -0700 (PDT) Received: from capella.localdomain ([193.89.194.60]) by smtp.gmail.com with ESMTPSA id jx14-20020a170906ca4e00b009ade1a4f795sm2193507ejb.168.2023.10.03.23.37.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Oct 2023 23:37:40 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= To: =?unknown-8bit?q?Michael_Turquette_=3Cmturquette=40baylibre=2Ecom=3E=2C_?= =?unknown-8bit?q?Stephen_Boyd_=3Csboyd=40kernel=2Eorg=3E=2C_Rob_Herring_=3C?= =?unknown-8bit?q?robh+dt=40kernel=2Eorg=3E=2C_Krzysztof_Kozlowski_=3Ckrzysz?= =?unknown-8bit?q?tof=2Ekozlowski+dt=40linaro=2Eorg=3E=2C_Conor_Dooley_=3Cco?= =?unknown-8bit?q?nor+dt=40kernel=2Eorg=3E=2C_Andrew_Lunn_=3Candrew=40lunn?= =?unknown-8bit?q?=2Ech=3E=2C_Sebastian_Hesselbarth_=3Csebastian=2Ehesselbar?= =?unknown-8bit?q?th=40gmail=2Ecom=3E=2C_Gregory_Clement_=3Cgregory=2Eclemen?= =?unknown-8bit?q?t=40bootlin=2Ecom=3E=2C_=A0ipraga__=3Calsi=40bang-olufsen?= =?unknown-8bit?q?=2Edk=3E?= Cc: Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 4/4] clk: si5351: allow PLLs to be adjusted without reset Date: Wed, 4 Oct 2023 08:35:30 +0200 Message-ID: <20231004063712.3348978-5-alvin@pqrs.dk> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231004063712.3348978-1-alvin@pqrs.dk> References: <20231004063712.3348978-1-alvin@pqrs.dk> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 03 Oct 2023 23:37:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778805876338807314 X-GMAIL-MSGID: 1778805876338807314 From: Alvin Šipraga Introduce a new PLL reset mode flag which controls whether or not to reset a PLL after adjusting its rate. The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga Acked-by: --- drivers/clk/clk-si5351.c | 47 ++++++++++++++++++++++++++-- include/linux/platform_data/si5351.h | 2 ++ 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index 00fb9b09e030..95d7afb8cfc6 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index c71a2dd66143..5f412a615532 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -105,10 +105,12 @@ struct si5351_clkout_config { * @clk_xtal: xtal input clock * @clk_clkin: clkin input clock * @pll_src: array of pll source clock setting + * @pll_reset: array indicating if plls should be reset after setting the rate * @clkout: array of clkout configuration */ struct si5351_platform_data { enum si5351_pll_src pll_src[2]; + bool pll_reset[2]; struct si5351_clkout_config clkout[8]; };