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Tue, 3 Oct 2023 01:22:31 -0500 Received: from xsjarunbala50.xilinx.com (10.180.168.240) by SATLEXMB03.amd.com (10.181.40.144) with Microsoft SMTP Server id 15.1.2507.27 via Frontend Transport; Tue, 3 Oct 2023 01:22:30 -0500 From: Jay Buddhabhatti To: , , CC: , , , Jay Buddhabhatti Subject: [PATCH 1/2] drivers: clk: zynqmp: calculate closest mux rate Date: Mon, 2 Oct 2023 23:21:52 -0700 Message-ID: <20231003062153.12215-2-jay.buddhabhatti@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20231003062153.12215-1-jay.buddhabhatti@amd.com> References: <20231003062153.12215-1-jay.buddhabhatti@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000E9CF:EE_|DS0PR12MB8272:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cf720ad-4a4c-47d0-bc5b-08dbc3d92124 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: XtfyiLDbamowImTNj8Y2C6AmtPLAdar3dEBSMxF6EdMRTdu5DllSIr/Ij3rIAF97m+QeIZrE8kh89gRHHBO2vG8INGsc1L/nV3bOB4XCDdT6TIrmxp6i6QnLwNUjSJXTCanwYFixCCr0r3lsU6aqy4YflZ5Fr0Dw4Drdcay1zpWyPemCH90pHymTiTmQynx3gcd6rSB+PBNCvBXMgDU6xirm1luqIQUyJIkfYnzOARMvUYH9f8RI4oF5tIgVYUHmsc5qjOukhdsQ7TxTJVmnij//QinQ3E4sStUBV6EjRaCvVsXfKlnj1NlDafukPNqotXIwyHt6ll8AXLmjitB6PQsan0NZ9c+IQRy84+4qxONXYck/J+lQNWObiryjm//8Y5wRoZ72sX2uSczDmhv7p/2Ouxtbf51Ba9/rWV7vhkctJI3bqP/V/leH6v6xM7bM8XsuCbfvYQX3zt4MDdCvVfh6OdDWNQP4VZMrZth3jj/LJuKEnFE/02FDjImzjRBZGc4FMWdws2RhKIoOLRY4dRq2h5LaYufjTL1jqyYsUHdbvJ+lXXcl0BVPy8FGyJGnb5f9q4mjwMXjgH89Sh9yDwgnQ5QUUcUh0X024pwXTyi5nUPkLxHjXOfAGDqd4bjYRG5/MxhttMcNKmWGZWF9H8aoNn2b+SXZS+HpmdnDprT+H4lYvpCyocbVKoGgznX6ZIW+vM5wAHMoPi3hBBz4ZrqFxAFY7ovOASrO4llhcD4RSkSqo19jwt4LLc6dVQBGIA9S7dqqjCiSbVsx2ofdYQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(396003)(39860400002)(230922051799003)(64100799003)(82310400011)(1800799009)(186009)(451199024)(46966006)(40470700004)(36840700001)(478600001)(2616005)(336012)(2906002)(83380400001)(26005)(47076005)(1076003)(110136005)(316002)(44832011)(70206006)(6636002)(5660300002)(41300700001)(8936002)(426003)(70586007)(54906003)(4326008)(8676002)(40460700003)(36860700001)(356005)(81166007)(82740400003)(86362001)(36756003)(40480700001)(6666004)(36900700001);DIR:OUT;SFP:1101; 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Mon, 02 Oct 2023 23:22:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778714331546638569 X-GMAIL-MSGID: 1778714331546638569 Currently zynqmp clock driver is not calculating closest mux rate and because of that Linux is not setting proper frequency for CPU and not able to set given frequency for dynamic frequency scaling. E.g., In current logic initial acpu clock parent and frequency as below apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_idiv1 0 0 0 2199999978 0 0 50000 Y acpu0 0 0 0 2199999978 0 0 50000 Y After changing acpu frequency to 549999994 Hz using CPU freq scaling its selecting incorrect parent which is not closest frequency. rpll_to_xpd 0 0 0 1599999984 0 0 50000 Y acpu0_mux 0 0 0 1599999984 0 0 50000 Y acpu0_div1 0 0 0 533333328 0 0 50000 Y acpu0 0 0 0 533333328 0 0 50000 Y Parent should remain same since 549999994 = 2199999978 / 4. So use __clk_mux_determine_rate_closest() generic function to calculate closest rate for mux clock. After this change its selecting correct parent and correct clock rate. apll1 0 0 0 2199999978 0 0 50000 Y acpu0_mux 0 0 0 2199999978 0 0 50000 Y acpu0_div1 0 0 0 549999995 0 0 50000 Y acpu0 0 0 0 549999995 0 0 50000 Y Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/clk-mux-zynqmp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/zynqmp/clk-mux-zynqmp.c b/drivers/clk/zynqmp/clk-mux-zynqmp.c index 60359333f26d..9b5d3050b742 100644 --- a/drivers/clk/zynqmp/clk-mux-zynqmp.c +++ b/drivers/clk/zynqmp/clk-mux-zynqmp.c @@ -89,7 +89,7 @@ static int zynqmp_clk_mux_set_parent(struct clk_hw *hw, u8 index) static const struct clk_ops zynqmp_clk_mux_ops = { .get_parent = zynqmp_clk_mux_get_parent, .set_parent = zynqmp_clk_mux_set_parent, - .determine_rate = __clk_mux_determine_rate, + .determine_rate = __clk_mux_determine_rate_closest, }; static const struct clk_ops zynqmp_clk_mux_ro_ops = { From patchwork Tue Oct 3 06:21:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Buddhabhatti, Jay" X-Patchwork-Id: 147639 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1887981vqb; Mon, 2 Oct 2023 23:23:14 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE7Nt6l5utBFlh06twueHexsez4rLmOkNydlRQo7ASiCBZZeB9Wr3IOVbdpBuguPUNoTH1Y X-Received: by 2002:a05:6a00:2491:b0:68e:41e9:10be with SMTP id c17-20020a056a00249100b0068e41e910bemr13517582pfv.20.1696314194257; Mon, 02 Oct 2023 23:23:14 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696314194; cv=pass; d=google.com; s=arc-20160816; b=O1AqHw2gfBM9EcU+C2yQme+cFL+ZryWiD2pcLU04gAsCQ/ruUJEepGLWuSAWSzNALw vTmuqbAYd3WAvJLzcTCq4hLHjiErubcPQUfR/V2WnCCVh9TOLdAZLXwUqG8bvP8wlWKR MVPYJ9pYFgMnR7WcopS/Be0lSBf8Wc0/9PeCtyB34hCsXr80WFV7NZ26wWSXHQClIrNM s4+E5wXbqoP3OIS7p3STuA+SbsgqHSd+xwvYwwFr3LGlX50ksD+ews4UqZhcwLaIonTl n2iQLmJZ5Ldlfc556AHVIVQW8WPfjZrwf33QBXz+BRlkIaXG3rPBzuHKheT1PgPABbxr isig== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=aX/ewiwVvxectQk+ywRB3ivU2XZjRqHGNqzA3sRY6ZM=; fh=qgqdgEGfhDbjAI1ss1X59igQOOT4WTawiJjMpbG0a4g=; b=res40mFcyswTAFJGAg7ZkwiV1Q/Fi8cfM82RuPiMbN+ABPGsvizaIPSCn88ETL42eR L0H8zfPs9mBEngROQT2DUeyvxnVW/V1YZQtYnHzSU3iOVM954K5eZDuAqw4UDPnGT2Uz HOuyrjiY3u2E1YXpW7+GFrG0Dg2E0EMU1raic5W/my//YCN2WGddbnGw2fOgBmi77YWt GzCYMgC9tX9LW7cyT73kgw4F6gRPcakia6d/StZNfhqEnOtOBRdRKaYP2V93Nzql81zb fwuoJEOXfQMPIvpwefP7t7/lGpkPLybUDlYAB8ctnLMg2tbxH2nc0KobLKmPfEpfmglC qz/w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="B/9X3C8P"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from agentk.vger.email (agentk.vger.email. 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Mon, 02 Oct 2023 23:23:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778714352396469495 X-GMAIL-MSGID: 1778714352396469495 Currently zynqmp divider round rate is considering single parent and calculating rate and parent rate accordingly. But if divider clock flag is set to SET_RATE_PARENT then its not trying to traverse through all parent rate and not selecting best parent rate from that. So use common divider_round_rate() which is traversing through all clock parents and its rate and calculating proper parent rate. Signed-off-by: Jay Buddhabhatti --- drivers/clk/zynqmp/divider.c | 70 ++++++------------------------------ 1 file changed, 10 insertions(+), 60 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 33a3b2a22659..a42c183d7e5d 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -110,52 +110,6 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL(parent_rate, value); } -static void zynqmp_get_divider2_val(struct clk_hw *hw, - unsigned long rate, - struct zynqmp_clk_divider *divider, - u32 *bestdiv) -{ - int div1; - int div2; - long error = LONG_MAX; - unsigned long div1_prate; - struct clk_hw *div1_parent_hw; - struct zynqmp_clk_divider *pdivider; - struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw); - - if (!div2_parent_hw) - return; - - pdivider = to_zynqmp_clk_divider(div2_parent_hw); - if (!pdivider) - return; - - div1_parent_hw = clk_hw_get_parent(div2_parent_hw); - if (!div1_parent_hw) - return; - - div1_prate = clk_hw_get_rate(div1_parent_hw); - *bestdiv = 1; - for (div1 = 1; div1 <= pdivider->max_div;) { - for (div2 = 1; div2 <= divider->max_div;) { - long new_error = ((div1_prate / div1) / div2) - rate; - - if (abs(new_error) < abs(error)) { - *bestdiv = div2; - error = new_error; - } - if (divider->flags & CLK_DIVIDER_POWER_OF_TWO) - div2 = div2 << 1; - else - div2++; - } - if (pdivider->flags & CLK_DIVIDER_POWER_OF_TWO) - div1 = div1 << 1; - else - div1++; - } -} - /** * zynqmp_clk_divider_round_rate() - Round rate of divider clock * @hw: handle between common and hardware-specific interfaces @@ -174,6 +128,8 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, u32 div_type = divider->div_type; u32 bestdiv; int ret; + u8 width = 0; + u16 max; /* if read only, just return current value */ if (divider->flags & CLK_DIVIDER_READ_ONLY) { @@ -193,23 +149,17 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw, return DIV_ROUND_UP_ULL((u64)*prate, bestdiv); } - bestdiv = zynqmp_divider_get_val(*prate, rate, divider->flags); - - /* - * In case of two divisors, compute best divider values and return - * divider2 value based on compute value. div1 will be automatically - * set to optimum based on required total divider value. - */ - if (div_type == TYPE_DIV2 && - (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) { - zynqmp_get_divider2_val(hw, rate, divider, &bestdiv); + max = divider->max_div; + while (max != 0) { + if ((max & 1) == 1) + width++; + max = max >> 1; } - if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac) - bestdiv = rate % *prate ? 1 : bestdiv; + rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags); - bestdiv = min_t(u32, bestdiv, divider->max_div); - *prate = rate * bestdiv; + if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate)) + *prate = rate; return rate; }