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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 36ff6749fbba..c91ab0e46648 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -218,6 +218,12 @@ properties: ratified in the 20191213 version of the unprivileged ISA specification. + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + - const: zicsr description: | The standard Zicsr extension for control and status register From patchwork Tue Oct 3 03:52:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 147602 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1837977vqb; Mon, 2 Oct 2023 20:53:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF8QZwMROn9iQdCNW5Eg2tIyACmFZO5z+yIj6WTRw6Ssfnyy3zLpQ1EaWFsYNrXo5fGX/EY X-Received: by 2002:a05:6902:18d5:b0:d7e:8175:4fa9 with SMTP id ck21-20020a05690218d500b00d7e81754fa9mr16327221ybb.4.1696305189338; Mon, 02 Oct 2023 20:53:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696305189; cv=none; d=google.com; s=arc-20160816; b=ChY09biGyI47AaQuQF1WaoISj0gGgUZj7sfwrCo1Pka8Ef+7kJEBS6pZ0NAuiQFohk EV43HdZ5gVrnzGnA/5Z3+E5VkRzrPyUU24O3wR2Ddjf8+aFVKGm0owvQ1b7Cr9TfzkjR QT3E3H8dWd60zVZpF5F8Q+MYKkAw6y08ubragfYLEeo8/qhPhwwpNfieVS41BjZSdrbm FNAE+7GRw3s0yYLd4WydwroDnHz8NfLVTt73LuhldVEeiOk/+M6f6MdnagrXu2l13dCi IZhwE0fN/XEgUH/oBIdwyVBaRNF+X/vFduFSW2p876Bk062ng66/+xRwI1W51sRQtAtB IEwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yycPMI9rC/acogS1vs0h8BRUvc4a6Kod+MRuzLqJ/0g=; fh=CO4Sjm/nDin0sEXLl6wWVDF+15K1bGSp5eW/uHFaeJQ=; b=WPv2vmcg6Kn0MpEJTw45xAO3kE7xo/0Tb8DGQtZKWGh8Ms8xG+mp4PLwEiPajQojCW KNA3RBYzShuacijCSTABqRhDNNDgtUiPBLQ0UqaI5HN4VojfF59gTXyzHRhPoQdKmQOD 4CPFV3cdTSCCro4xpVHyzrktqcHBSaNfXcbvWOuoGLYMPWDeYBaJ3da04FOeMKYLOoas Ax/sQ7fnVN/zBpvB1Qa6FlE5HR+wRW3HuYQk6UZq/qPkY+2MKw4MolIBun93Bs2i90aT TSXJ7GZHE92OSJ1YW9ZwLMwA8d5z5TOwO5HAhWw1MiHN3BBCLVKJjvLJfRnMq6kw49Jx ITxQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="eYod/e1R"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Mon, 02 Oct 2023 20:52:49 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel , Conor Dooley Subject: [PATCH v3 2/6] RISC-V: Detect Zicond from ISA string Date: Tue, 3 Oct 2023 09:22:22 +0530 Message-Id: <20231003035226.1945725-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231003035226.1945725-1-apatel@ventanamicro.com> References: <20231003035226.1945725-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 02 Oct 2023 20:53:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778704909975908446 X-GMAIL-MSGID: 1778704909975908446 The RISC-V integer conditional (Zicond) operation extension defines standard conditional arithmetic and conditional-select/move operations which are inspired from the XVentanaCondOps extension. In fact, QEMU RISC-V also has support for emulating Zicond extension. Let us detect Zicond extension from ISA string available through DT or ACPI. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Acked-by: Palmer Dabbelt --- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpufeature.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 0f520f7d058a..6fc51c1b34cf 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,6 +59,7 @@ #define RISCV_ISA_EXT_ZIFENCEI 41 #define RISCV_ISA_EXT_ZIHPM 42 #define RISCV_ISA_EXT_SMSTATEEN 43 +#define RISCV_ISA_EXT_ZICOND 44 #define RISCV_ISA_EXT_MAX 64 diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3755a8c2a9de..e3803822ab5a 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), From patchwork Tue Oct 3 03:52:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 147603 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1837996vqb; Mon, 2 Oct 2023 20:53:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEYnhjCpZob2XZnKltZlUIwmccrPjf7P+Nje+s9ukfk0coDHEF6am/rnq/5eJjMdesKWLrM X-Received: by 2002:a05:6a00:2491:b0:68f:c9df:2ccb with SMTP id c17-20020a056a00249100b0068fc9df2ccbmr13468054pfv.1.1696305192018; Mon, 02 Oct 2023 20:53:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696305192; cv=none; d=google.com; s=arc-20160816; b=SXZBfAOPyJlFrLapELUeBALXBsHudLRwWMglVBNOZDUwWehgFc/i7T7Fx3SSlGG3RL QVAVVZgEPbXNh1y8yi2Ld/h/w6C1FtvG3DIDIYdg1KtgYlwIp5bB/NBn+tYBiVpyJPPu gNarERXbPAjyDK71fv/3Qjq8ChIvrZYLQ0+f77r4BW2/yfsDtSiRtjm8RAK2XbBuE3CH /441Eh8WOxa0Uy+YGi8rJtgvZOy/WOpdv4xB+lmRAVDaOqLr/BE4sslGUqTFkuE8bESc matmTjrpOhNmTexFphcGz1c8AQnOi08KFccc7ktKKvo9YmV1T36YfCgihPBKjVb4lUHr /pFQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PR9YD+pr7hv0tmO2NOz2gpQmVbaE/cJ/IAsO/LYC7Pc=; fh=Nnw/Dw3prVIT5KLOVQO3DcS15zu3mo0yAEjXPL5Uo9Q=; b=aDdST15PuMNUmpZJzZbKRpN57taf8zWTMoDlQGPtkZ2LoWgxW/Q59EGUNdgyd03+eM 6A6dWzqp3QH2O1crS3gHCiQ6zF1/+s3N/xfZGxIrj0aZ8fwOYTSjDKWXqE3KwoYoD4d3 kU7RUjeiLNhFTrxx86I/+SZNsVxNyap2q2ZhWBq82Os7XfydGLBHnrdAxhiP6c3ncMY8 ArJ3pLaUnx8Gg1THpWIQvJYhUgns9TReCPCxIUnPT7Ve/UX2it4ok6a2VqnIGmZ2xqet QWWJGnm2bbMcUbqlN35nUrrwe0WY81vC6s6NffA+qaGgFiSbMCZiO7WIDCrAobGyX/89 ZAhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=XndW1qrh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_onereg.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index b1baf6f096a3..917d8cc2489e 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -138,6 +138,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_ZIFENCEI, KVM_RISCV_ISA_EXT_ZIHPM, KVM_RISCV_ISA_EXT_SMSTATEEN, + KVM_RISCV_ISA_EXT_ZICOND, KVM_RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c index 388599fcf684..c6ebce6126b5 100644 --- a/arch/riscv/kvm/vcpu_onereg.c +++ b/arch/riscv/kvm/vcpu_onereg.c @@ -46,6 +46,7 @@ static const unsigned long kvm_isa_ext_arr[] = { KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -93,6 +94,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) case KVM_RISCV_ISA_EXT_ZBB: case KVM_RISCV_ISA_EXT_ZBS: case KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_RISCV_ISA_EXT_ZICOND: case KVM_RISCV_ISA_EXT_ZICSR: case KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: From patchwork Tue Oct 3 03:52:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 147604 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1838002vqb; Mon, 2 Oct 2023 20:53:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHVN8XZ0SG47SSu8gGvGgPSrABzG10rkGZHS8Ixya7J80bLsT6Z3CG5UW0NYjcL5x8rj1h6 X-Received: by 2002:a05:6358:720c:b0:135:6d9:2399 with SMTP id h12-20020a056358720c00b0013506d92399mr14091030rwa.30.1696305196992; Mon, 02 Oct 2023 20:53:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696305196; cv=none; d=google.com; s=arc-20160816; b=fr68jUWmYRk84FbaUWCl2/dfVL7JTTYYqtk04VszSzQu/GgzNnFtcu5+47VLIi1EV9 MCG85ibUoUdq9hCjriWFQc4eFjWG6vMW+d490hzcsoDA/lKBjZ94PF28gyKvoxy1h72v kXUBD8f6um+nwbDO+FQ/72Iuqn35Uhnb2kINfKpTJNokREVZPDqmD1da5Uxbf829ReY8 oz4W3CZHBoT3SCq9dSzIsycVwhwSp7vJKLIBMLbhkD59ATcKopRB12ZG0lXp7ZTJeQob WRGIgJR3piBvtcpnWII/ceGLy7ESJPXptyOkfivSU++wYId3eNAwtUGCNMGOitn7VhLI vINA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qPmuiSFVvpuLv2dpw8j40AU0MURCdJR8iWnmtgcJS7I=; fh=Nnw/Dw3prVIT5KLOVQO3DcS15zu3mo0yAEjXPL5Uo9Q=; b=pr3sRXaNtxLNEKJmnAQmkV0UACMxK9o1GsN8eWKs3WqQBIZ2YIjFVsswt+WOcjP3LL DTkb6eCBTSiFy4D5DSP3chgoKuNtr8ReSIz8cwDqAgGKDiPVg1tnSOty0Fw4scOcLg5R R/rg6C3Vtjl5bHjvAVdoNUlczH/gpLQQfLgOhzlgThqHAw5dcaSaU60EFRcjiMtbfBXf CnrGBaF4Arc3zcuCgF4LEST1n9favkFRj3BIdy261xbk+qvkmE3TC9QiDo2nBcQ/v66k vUfiiZdIVPF5R7M52b5kuq8dCIUlDxXC5u/LJYirq8XXHCDTpA1B85v73otNN0emxZhc bkeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nBqT1V8Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id bw10-20020a056a00408a00b0068a68d71b68si521329pfb.216.2023.10.02.20.53.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 20:53:16 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nBqT1V8Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 4EF8B80FC71F; Mon, 2 Oct 2023 20:53:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239061AbjJCDxL (ORCPT + 18 others); Mon, 2 Oct 2023 23:53:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239065AbjJCDxI (ORCPT ); Mon, 2 Oct 2023 23:53:08 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37DA4197 for ; Mon, 2 Oct 2023 20:53:01 -0700 (PDT) Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c752caeaa6so3434285ad.1 for ; Mon, 02 Oct 2023 20:53:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1696305180; x=1696909980; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qPmuiSFVvpuLv2dpw8j40AU0MURCdJR8iWnmtgcJS7I=; b=nBqT1V8Yesyrd0U06mYSOfd7mgYTFRnLheFr0ZLaZ+iNG4gFv+B4U91dDjdCh/x6be CFKWr6ZuiUQr+BAGD7VK7X8fxnzeuezgwqn9+q0tqW5a2x8kwTf59Vnrer5OZ7l7jG+k i6Dwx/63Vj0u39qBGL+vtxEeS7lPE5Uk5G9ghxEaHn7zAKjs2pUX5Tu1uK6wMmSc0JvR jcSAccOUinzBh9xCNWDoRfGos+YSL4o98N0bwuBtsu8b4kjsxW9gXAFM4rP1mejSgbD0 ZsjeFRxg+1VZMClQHFY6pNvXbYcGY2PsFfoLip+g3ROk7NFcIgfosGvyuoNxd6oOPR16 6DRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696305180; x=1696909980; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qPmuiSFVvpuLv2dpw8j40AU0MURCdJR8iWnmtgcJS7I=; b=pEVF6unPr6hrbpJ8q7pPmSXFlSBYbDdTpth0PKhiAu3Q0P8yzpRApfIhq12O/8mY+i r2zKXJ6N56aZJFENAqd6vjrDol4hf8vdIdTulUYsrnWRO9dR/F6YzUgwb/wjGc6MvyiD 6QPpmlyCavpKdejhj0rzZ1OSDPUw7Z1nJF1S0eNCYDjp1QPFiDsBCPjE0IG+uBAtTKV9 pEOU3OAAdZUz6hhKPXGTOGcACSjWe/dtSMFZiw9qqdn8mesvTQo795DAolnyWPGI1gZs nMJ528g7hxfSZUKb6XOwPtQfpp0yE/jNF721EiWs8+CAw8SY/zBgkB1lQ00VM1JjCTdk PWhA== X-Gm-Message-State: AOJu0YwroiZ93jx69xh4kLUIBqx3z+N2zwHzZTR4A+0XFcbHgL4B0G2r KwhIvo8OMuiMX09IFF3M632vAA== X-Received: by 2002:a17:903:2305:b0:1c6:e4b:bbeb with SMTP id d5-20020a170903230500b001c60e4bbbebmr13020119plh.56.1696305180186; Mon, 02 Oct 2023 20:53:00 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.132]) by smtp.gmail.com with ESMTPSA id ja7-20020a170902efc700b001bf846dd2d0sm277381plb.13.2023.10.02.20.52.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 20:52:59 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Shuah Khan Cc: Andrew Jones , Mayuresh Chitale , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Anup Patel Subject: [PATCH v3 4/6] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Date: Tue, 3 Oct 2023 09:22:24 +0530 Message-Id: <20231003035226.1945725-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231003035226.1945725-1-apatel@ventanamicro.com> References: <20231003035226.1945725-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 20:53:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778704918106700256 X-GMAIL-MSGID: 1778704918106700256 We have a new senvcfg register in the general CSR ONE_REG interface so let us add it to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index a61b706a8778..6cec0ef75cc7 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -211,6 +211,8 @@ static const char *general_csr_id_to_str(__u64 reg_off) return RISCV_CSR_GENERAL(satp); case KVM_REG_RISCV_CSR_REG(scounteren): return RISCV_CSR_GENERAL(scounteren); + case KVM_REG_RISCV_CSR_REG(senvcfg): + return RISCV_CSR_GENERAL(senvcfg); } TEST_FAIL("Unknown general csr reg: 0x%llx", reg_off); @@ -540,6 +542,7 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(sip), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(satp), KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(scounteren), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(senvcfg), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(frequency), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(time), KVM_REG_RISCV | KVM_REG_SIZE_U64 | KVM_REG_RISCV_TIMER | KVM_REG_RISCV_TIMER_REG(compare), From patchwork Tue Oct 3 03:52:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 147605 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1838045vqb; Mon, 2 Oct 2023 20:53:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFje5k9oM7OPrct6z1ROU0qHHaTKGZ+73Sajo3g1w5+Z5EHcGucUgvQC8xtUCQPblg+AgBK X-Received: by 2002:a17:90a:d14a:b0:273:cb91:c74f with SMTP id t10-20020a17090ad14a00b00273cb91c74fmr13432039pjw.8.1696305207333; Mon, 02 Oct 2023 20:53:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696305207; cv=none; d=google.com; s=arc-20160816; b=LnpcYGcadCgARtlIuUQ7uItxy293mC0w0k2G80h90I5/xDrtnDcOm2uajkyXEvYHP5 L/cJkdwIA6kgV6kP0R0AZc3G2vfqslHZiJWrKxwtnsm41KVym/z1eP7+DbrgJPGlhJXJ o1wf67Uu9tAnZIPSMrT8arZF5rxmq7qMDwwh1n+MwIH1K6U3Ga8pkAJZAybAiwt4msGi EznZ/OiPefn0hM29Fklub3PM3t0CbYtE/f1tGFFaL8E0xf4+vp9aCfAklBBSSqM+QLLp m0vE3etMfvzILlGEH1yoGZc9xQdesV2G+vyLe1aOzCWOPH5pXeEIBsrNGFqgnvBzwqhR pk3g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uNHkjMM9HHYX8X83JcKOMwoHgKf/W4d95vsynq44CKo=; fh=Nnw/Dw3prVIT5KLOVQO3DcS15zu3mo0yAEjXPL5Uo9Q=; b=lFN7MmxV0fNHz/83BJ3DlQ7IWDLucGDZZjN8G21n2yQhlbNl1jUYsc390Jh50K5kOS Ux4l3Q0ilDgKgE1q8/Rk771jaIVYfJTDtlL1er79sVsgZSK0R19Xl2q8mIM1wW/ZVTvx SUHnrjWgKVH/gkOJ5PJyCjxRChAUSwqbngW3pz7oTIqXKbu1JfZCsSzUO8EhFDDOijSp rrMcCjdwsi8ul9p5qb5jqKLmlgdC1tq0k9CIi0finiuDUC4jYAuP+1+NyNxo66iGtdEG 1ZPqrXKqWBSi3powpZRjlrBwA9DIG1Se6mt3YbwppC6aBlHv5J5cpFPfmnhCLxy/5cGe YPmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=Xjx551QK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- .../selftests/kvm/riscv/get-reg-list.c | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 6cec0ef75cc7..625118d53b74 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -36,6 +36,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_I: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_M: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_V: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSTC: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SVINVAL: @@ -186,6 +187,8 @@ static const char *core_id_to_str(const char *prefix, __u64 id) "KVM_REG_RISCV_CSR_GENERAL | KVM_REG_RISCV_CSR_REG(" #csr ")" #define RISCV_CSR_AIA(csr) \ "KVM_REG_RISCV_CSR_AIA | KVM_REG_RISCV_CSR_REG(" #csr ")" +#define RISCV_CSR_SMSTATEEN(csr) \ + "KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_REG(" #csr ")" static const char *general_csr_id_to_str(__u64 reg_off) { @@ -243,6 +246,18 @@ static const char *aia_csr_id_to_str(__u64 reg_off) return NULL; } +static const char *smstateen_csr_id_to_str(__u64 reg_off) +{ + /* reg_off is the offset into struct kvm_riscv_smstateen_csr */ + switch (reg_off) { + case KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0): + return RISCV_CSR_SMSTATEEN(sstateen0); + } + + TEST_FAIL("Unknown smstateen csr reg: 0x%llx", reg_off); + return NULL; +} + static const char *csr_id_to_str(const char *prefix, __u64 id) { __u64 reg_off = id & ~(REG_MASK | KVM_REG_RISCV_CSR); @@ -255,6 +270,8 @@ static const char *csr_id_to_str(const char *prefix, __u64 id) return general_csr_id_to_str(reg_off); case KVM_REG_RISCV_CSR_AIA: return aia_csr_id_to_str(reg_off); + case KVM_REG_RISCV_CSR_SMSTATEEN: + return smstateen_csr_id_to_str(reg_off); } TEST_FAIL("%s: Unknown csr subtype: 0x%llx", prefix, reg_subtype); @@ -332,6 +349,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(I), KVM_ISA_EXT_ARR(M), KVM_ISA_EXT_ARR(V), + KVM_ISA_EXT_ARR(SMSTATEEN), KVM_ISA_EXT_ARR(SSAIA), KVM_ISA_EXT_ARR(SSTC), KVM_ISA_EXT_ARR(SVINVAL), @@ -637,6 +655,11 @@ static __u64 aia_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SSAIA, }; +static __u64 smstateen_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_CSR | KVM_REG_RISCV_CSR_SMSTATEEN | KVM_REG_RISCV_CSR_SMSTATEEN_REG(sstateen0), + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_SMSTATEEN, +}; + static __u64 fp_f_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[0]), KVM_REG_RISCV | KVM_REG_SIZE_U32 | KVM_REG_RISCV_FP_F | KVM_REG_RISCV_FP_F_REG(f[1]), @@ -744,6 +767,8 @@ static __u64 fp_d_regs[] = { {"zihpm", .feature = KVM_RISCV_ISA_EXT_ZIHPM, .regs = zihpm_regs, .regs_n = ARRAY_SIZE(zihpm_regs),} #define AIA_REGS_SUBLIST \ {"aia", .feature = KVM_RISCV_ISA_EXT_SSAIA, .regs = aia_regs, .regs_n = ARRAY_SIZE(aia_regs),} +#define SMSTATEEN_REGS_SUBLIST \ + {"smstateen", .feature = KVM_RISCV_ISA_EXT_SMSTATEEN, .regs = smstateen_regs, .regs_n = ARRAY_SIZE(smstateen_regs),} #define FP_F_REGS_SUBLIST \ {"fp_f", .feature = KVM_RISCV_ISA_EXT_F, .regs = fp_f_regs, \ .regs_n = ARRAY_SIZE(fp_f_regs),} @@ -871,6 +896,14 @@ static struct vcpu_reg_list aia_config = { }, }; +static struct vcpu_reg_list smstateen_config = { + .sublists = { + BASE_SUBLIST, + SMSTATEEN_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list fp_f_config = { .sublists = { BASE_SUBLIST, @@ -903,6 +936,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zifencei_config, &zihpm_config, &aia_config, + &smstateen_config, &fp_f_config, &fp_d_config, }; From patchwork Tue Oct 3 03:52:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 147607 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1838152vqb; Mon, 2 Oct 2023 20:53:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEPHG/WvMvcMV/XIQiLvRHCuS4qWfj4L7LZ5UnL5NKXHpWi7Pu8EUU4AC78j+0BzG4uLlTc X-Received: by 2002:a17:902:d3c7:b0:1bb:f1d9:432e with SMTP id w7-20020a170902d3c700b001bbf1d9432emr9644682plb.37.1696305235672; Mon, 02 Oct 2023 20:53:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- .../testing/selftests/kvm/riscv/get-reg-list.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 625118d53b74..77dc5221c465 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -48,6 +48,7 @@ bool filter_reg(__u64 reg) case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOM: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICBOZ: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR: + case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIFENCEI: case KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: @@ -361,6 +362,7 @@ static const char *isa_ext_id_to_str(__u64 id) KVM_ISA_EXT_ARR(ZICBOM), KVM_ISA_EXT_ARR(ZICBOZ), KVM_ISA_EXT_ARR(ZICNTR), + KVM_ISA_EXT_ARR(ZICOND), KVM_ISA_EXT_ARR(ZICSR), KVM_ISA_EXT_ARR(ZIFENCEI), KVM_ISA_EXT_ARR(ZIHINTPAUSE), @@ -632,6 +634,10 @@ static __u64 zicntr_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICNTR, }; +static __u64 zicond_regs[] = { + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICOND, +}; + static __u64 zicsr_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_ISA_EXT | KVM_RISCV_ISA_EXT_ZICSR, }; @@ -759,6 +765,8 @@ static __u64 fp_d_regs[] = { {"zbs", .feature = KVM_RISCV_ISA_EXT_ZBS, .regs = zbs_regs, .regs_n = ARRAY_SIZE(zbs_regs),} #define ZICNTR_REGS_SUBLIST \ {"zicntr", .feature = KVM_RISCV_ISA_EXT_ZICNTR, .regs = zicntr_regs, .regs_n = ARRAY_SIZE(zicntr_regs),} +#define ZICOND_REGS_SUBLIST \ + {"zicond", .feature = KVM_RISCV_ISA_EXT_ZICOND, .regs = zicond_regs, .regs_n = ARRAY_SIZE(zicond_regs),} #define ZICSR_REGS_SUBLIST \ {"zicsr", .feature = KVM_RISCV_ISA_EXT_ZICSR, .regs = zicsr_regs, .regs_n = ARRAY_SIZE(zicsr_regs),} #define ZIFENCEI_REGS_SUBLIST \ @@ -864,6 +872,14 @@ static struct vcpu_reg_list zicntr_config = { }, }; +static struct vcpu_reg_list zicond_config = { + .sublists = { + BASE_SUBLIST, + ZICOND_REGS_SUBLIST, + {0}, + }, +}; + static struct vcpu_reg_list zicsr_config = { .sublists = { BASE_SUBLIST, @@ -932,6 +948,7 @@ struct vcpu_reg_list *vcpu_configs[] = { &zbb_config, &zbs_config, &zicntr_config, + &zicond_config, &zicsr_config, &zifencei_config, &zihpm_config,