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Tue, 19 Jul 2022 20:14:54 GMT Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1CCC56E04E; Tue, 19 Jul 2022 20:14:54 +0000 (GMT) Received: from b03ledav001.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 812AD6E054; Tue, 19 Jul 2022 20:14:53 +0000 (GMT) Received: from sig-9-77-137-222.ibm.com (unknown [9.77.137.222]) by b03ledav001.gho.boulder.ibm.com (Postfix) with ESMTP; Tue, 19 Jul 2022 20:14:53 +0000 (GMT) Message-ID: <31dc528de363088ba74e82ca0fbca06e3dc5ac58.camel@vnet.ibm.com> Subject: [PATCH, rs6000, v2] Cleanup some vstrir define_expand naming inconsistencies To: GCC Patches Date: Tue, 19 Jul 2022 15:14:52 -0500 In-Reply-To: <6da1e35def9d282bcf87483e78cf578fff604723.camel@vnet.ibm.com> References: <6da1e35def9d282bcf87483e78cf578fff604723.camel@vnet.ibm.com> X-Mailer: Evolution 3.28.5 (3.28.5-18.el8) Mime-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: tJJbiqG1GcJGHqd8OJTw5bXCLJL5b9aL X-Proofpoint-GUID: J4GeEeqDeSIVwkIYu6WuUuyKp0L1ITAF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.883,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-07-19_08,2022-07-19_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 mlxlogscore=761 adultscore=0 priorityscore=1501 clxscore=1015 impostorscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2206140000 definitions=main-2207190083 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H2, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: will schmidt via Gcc-patches From: "Li, Pan2 via Gcc-patches" Reply-To: will schmidt Cc: Segher Boessenkool , David Edelsohn Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org Sender: "Gcc-patches" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-LABELS: =?utf-8?b?IlxcSW1wb3J0YW50Ig==?= X-GMAIL-THRID: =?utf-8?q?1738262563663994106?= X-GMAIL-MSGID: =?utf-8?q?1738813780629008823?= [PATCH, rs6000, v2] Cleanup some vstrir define_expand naming inconsistencies Hi, This cleans up some of the naming around the vstrir and vstril instruction definitions, with some cosmetic changes for consistency. No functional changes. Regtested just in case, no regressions. [V2] Used 'direct' instead of 'internal', and cosmetically reworked the changelog. OK for trunk? Thanks, gcc/ * config/rs6000/altivec.md: (vstrir_code_): Rename to... (vstrir_direct_): ... this. (vstrir_p_code_): Rename to... (vstrir_p_direct_): ... this. (vstril_code_): Rename to... (vstril_direct_): ... this. (vstril_p_code_): Rename to... (vstril_p_direct_): ... this. diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index efc8ae35c2e7..2c4940f2e21c 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -884,44 +884,44 @@ (define_expand "vstrir_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] "TARGET_POWER10" { if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstrir_code_ (operands[0], operands[1])); + emit_insn (gen_vstrir_direct_ (operands[0], operands[1])); else - emit_insn (gen_vstril_code_ (operands[0], operands[1])); + emit_insn (gen_vstril_direct_ (operands[0], operands[1])); DONE; }) -(define_insn "vstrir_code_" +(define_insn "vstrir_direct_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIR))] "TARGET_POWER10" "vstrir %0,%1" [(set_attr "type" "vecsimple")]) -;; This expands into same code as vstrir_ followed by condition logic +;; This expands into same code as vstrir followed by condition logic ;; so that a single vstribr. or vstrihr. or vstribl. or vstrihl. instruction ;; can, for example, satisfy the needs of a vec_strir () function paired ;; with a vec_strir_p () function if both take the same incoming arguments. (define_expand "vstrir_p_" [(match_operand:SI 0 "gpc_reg_operand") (match_operand:VIshort 1 "altivec_register_operand")] "TARGET_POWER10" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstrir_p_code_ (scratch, operands[1])); + emit_insn (gen_vstrir_p_direct_ (scratch, operands[1])); else - emit_insn (gen_vstril_p_code_ (scratch, operands[1])); + emit_insn (gen_vstril_p_direct_ (scratch, operands[1])); emit_insn (gen_cr6_test_for_zero (operands[0])); DONE; }) -(define_insn "vstrir_p_code_" +(define_insn "vstrir_p_direct_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIR)) (set (reg:CC CR6_REGNO) @@ -936,17 +936,17 @@ (define_expand "vstril_" (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand")] UNSPEC_VSTRIR))] "TARGET_POWER10" { if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstril_code_ (operands[0], operands[1])); + emit_insn (gen_vstril_direct_ (operands[0], operands[1])); else - emit_insn (gen_vstrir_code_ (operands[0], operands[1])); + emit_insn (gen_vstrir_direct_ (operands[0], operands[1])); DONE; }) -(define_insn "vstril_code_" +(define_insn "vstril_direct_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIL))] "TARGET_POWER10" @@ -962,18 +962,18 @@ (define_expand "vstril_p_" (match_operand:VIshort 1 "altivec_register_operand")] "TARGET_POWER10" { rtx scratch = gen_reg_rtx (mode); if (BYTES_BIG_ENDIAN) - emit_insn (gen_vstril_p_code_ (scratch, operands[1])); + emit_insn (gen_vstril_p_direct_ (scratch, operands[1])); else - emit_insn (gen_vstrir_p_code_ (scratch, operands[1])); + emit_insn (gen_vstrir_p_direct_ (scratch, operands[1])); emit_insn (gen_cr6_test_for_zero (operands[0])); DONE; }) -(define_insn "vstril_p_code_" +(define_insn "vstril_p_direct_" [(set (match_operand:VIshort 0 "altivec_register_operand" "=v") (unspec:VIshort [(match_operand:VIshort 1 "altivec_register_operand" "v")] UNSPEC_VSTRIL)) (set (reg:CC CR6_REGNO)