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Add the leaf and its Automatic IBRS feature bit. Note: New whole leaf (vs a bit) due to propagation via KVM later in this series. Signed-off-by: Kim Phillips Signed-off-by: Borislav Petkov --- arch/x86/include/asm/cpufeature.h | 7 +++++-- arch/x86/include/asm/cpufeatures.h | 5 ++++- arch/x86/include/asm/disabled-features.h | 3 ++- arch/x86/include/asm/required-features.h | 3 ++- arch/x86/kernel/cpu/common.c | 3 +++ 5 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index 1a85e1fb0922..ce0c8f7d3218 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -32,6 +32,7 @@ enum cpuid_leafs CPUID_8000_0007_EBX, CPUID_7_EDX, CPUID_8000_001F_EAX, + CPUID_8000_0021_EAX, }; #define X86_CAP_FMT_NUM "%d:%d" @@ -94,8 +95,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -118,8 +120,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 17, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 20)) + BUILD_BUG_ON_ZERO(NCAPINTS != 21)) #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index aefd0816a333..45ea992716b8 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 20 /* N 32-bit words worth of info */ +#define NCAPINTS 21 /* N 32-bit words worth of info */ #define NBUGINTS 1 /* N 32-bit bug flags */ /* @@ -421,6 +421,9 @@ #define X86_FEATURE_V_TSC_AUX (19*32+ 9) /* "" Virtual TSC_AUX */ #define X86_FEATURE_SME_COHERENT (19*32+10) /* "" AMD hardware-enforced cache coherency */ +/* AMD-defined Extended Feature 2 EAX, CPUID level 0x80000021 (EAX), word 20 */ +#define X86_FEATURE_AUTOIBRS (20*32+ 8) /* AMD Automatic IBRS */ + /* * BUG word(s) */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index bbb03b25263e..9be4e0b01b9c 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -118,6 +118,7 @@ #define DISABLED_MASK17 0 #define DISABLED_MASK18 0 #define DISABLED_MASK19 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define DISABLED_MASK20 0 +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h index aff774775c67..7ba1726b71c7 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -98,6 +98,7 @@ #define REQUIRED_MASK17 0 #define REQUIRED_MASK18 0 #define REQUIRED_MASK19 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20) +#define REQUIRED_MASK20 0 +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) #endif /* _ASM_X86_REQUIRED_FEATURES_H */ diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 2bec4b4b2c50..070350c2c514 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1091,6 +1091,9 @@ void get_cpu_cap(struct cpuinfo_x86 *c) if (c->extended_cpuid_level >= 0x8000001f) c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f); + if (c->extended_cpuid_level >= 0x80000021) + c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021); + init_scattered_cpuid_features(c); init_speculation_control(c); From patchwork Fri Nov 4 21:36:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 15808 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp651650wru; Fri, 4 Nov 2022 14:40:10 -0700 (PDT) X-Google-Smtp-Source: AMsMyM46+BX7G8Gew/FE/b3j50BPItDEoXkmt37szkEMc+Tiw3sEjvitvDx6tNXGCdoRuvw47rqW X-Received: by 2002:a17:907:6d1b:b0:7a1:11a9:1334 with SMTP id sa27-20020a1709076d1b00b007a111a91334mr7922900ejc.131.1667598010791; Fri, 04 Nov 2022 14:40:10 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667598010; cv=pass; d=google.com; s=arc-20160816; b=tSl1qzUX6gEiSFDuD3sdPfvQ7mzz/d/JTLITn9jvmZ73Z9DZlly2SH9i+9qGrudOd5 X+eLnxub4w0x5odbp5czYM9nmd7qbP/YSaD3beJh472b+Ubc3Imydu9tMyltTrBSg9wG +Q4i1sLlIopkAchj3rYDZEHhwlbbAXQWhrgPYebuFmZV/VQjjrNdSGkkODr+Kt+7aBfb WCnBGORZAXEuxM/KTKE9IzGQ5t516PjwGgebED1n5m5Go6Xunj4wdKPr5A7x97GuplsX uYgaOVUB0yAeAHPtm7F5GVG6/mFoxqUDUI76zlhdHvMJPMRIAZ4j+TZGsB2mmO2LbRxp 9bFA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=mbVDM7xURsCJ38pD8le61MToi9JHl8/f+1S9G9aw8d4=; b=qM1HTk7wrR5dQemaO9y+f6+8uLg45r+ZEb5bVcrGDC3SYM3dH+0L/W9VCfTOYjPPBp u0tdP7MAeEqfu1pG6jMg6mZkDoinvlQ+flgNfz/esTjbfyiS4Mivht3v05ljC3obU0Wl ZprP8+twqovY0jZ65epIgREr+BVHqbRFXJseltQ4DSj9BEIJZsNoP766neZxe0pgcj+i KkstPLsvbJ3U8EMrdkaavZoMaVV6oawgEITDn59bw+pNXRfWMOys3dGQ+U4aSwAxpnqu 2guYNzNl+nduzWj3Ez4bNgKAl8mX5gZPJgLZ29TC+EFX4NjeC9lVVm0fGtM9+7hBRUe8 3JHg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=fj8ZPqtd; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Ingo Molnar , Joao Martins , Jonathan Corbet , Konrad Rzeszutek Wilk , "Paolo Bonzini" , Sean Christopherson , Thomas Gleixner , David Woodhouse , Greg Kroah-Hartman , Juergen Gross , Peter Zijlstra , Tony Luck , Babu Moger , Tom Lendacky , , , Subject: [PATCH 2/3] x86/speculation: Support Automatic IBRS Date: Fri, 4 Nov 2022 16:36:50 -0500 Message-ID: <20221104213651.141057-3-kim.phillips@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221104213651.141057-1-kim.phillips@amd.com> References: <20221104213651.141057-1-kim.phillips@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT107:EE_|MW3PR12MB4409:EE_ X-MS-Office365-Filtering-Correlation-Id: 36830118-6dda-4163-36ec-08dabeacc4f7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: qZs9mEbd1QYoPidYqP432+G0b7JuEG6wj5EMH7rLgM5oUwqnc0J0uNr5m8wJhiZaW/itf2KChduzA5+4Q+NUkeR07ofmPGtLVaztV/foTHsx6a9qfj3jcg0kBb3IbxtvcCDe9sg2Wu6TGiHHrTeXeKCRA7hD+vPg+HJYoZKPCoAxJmbUh+SM8YhsjOBaUOzL98j+b/MZaCmtFiulcMcDKxQaFQXyeVHtVRNnvjbKBqb3l8xK16sI3EDEnWPLds7+SYpsTJFlq0Z87mi6YwTyZdd3BL3HDUBel1F7Q05J8U32A6vwu9TSWUTwjbL9zS+5MF8CzX+5ZzeC9Vtid9upCOpj9Oo9UqkqnSVScpIbQfZ29O60kVhjVdMe0hSDwdF/tTF/mfEmMqXqVwDHpL1HZ+c+7CZeFSWiTEoj5GFcL2QdFk2fviVaCIF4Ls1MxG2isneN+yEISsM7RcuQLhaXHQjhBUphXLw4vBCep3tYNNxOQNjJXqPkZQLFNhB9I0iudZ7CxF/Knt/Uujum1zsMdI5eWGDRP+KtDs8lrnuP8m+YpQEHNmhHUuSATsXeRvVMpIF20T0D97ZIJgnX61zgpyXuFOhIeJyuDpA6dndOF/+05uco8yKDnVtGnQe3e+lHdG6XgsLeXk597uAfm8ONGC6ZeSH25ah9m0lN0ribujIZttvcF4ImOyHnc6Y7u88neYQswSxoQPE1F/AjWXxpPaa1Z+QR+xQmSRyfxc8KKuZmmFRxT571TxR7BPWZlxAyE9yRrNluPhn7MFYsvlSRJmxhi9SvWrkeIhqEAGVxuJvZlrc3sXPfExhcHr5OzzVv X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(396003)(376002)(346002)(136003)(451199015)(40470700004)(36840700001)(46966006)(81166007)(36860700001)(82310400005)(36756003)(40480700001)(40460700003)(86362001)(41300700001)(70586007)(4326008)(26005)(356005)(8676002)(70206006)(1076003)(2616005)(44832011)(16526019)(7416002)(186003)(7696005)(336012)(478600001)(5660300002)(6916009)(8936002)(316002)(82740400003)(6666004)(54906003)(2906002)(83380400001)(47076005)(426003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2022 21:37:27.3753 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 36830118-6dda-4163-36ec-08dabeacc4f7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4409 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748603151236721484?= X-GMAIL-MSGID: =?utf-8?q?1748603251490348841?= The AMD Zen4 core supports a new feature called Automatic IBRS. It is a "set-and-forget" feature that means that, unlike e.g., s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation resources automatically across CPL transitions. The feature is advertised by CPUID_Fn80000021_EAX bit 8 and is enabled by setting MSR C000_0080 (EFER) bit 21. Enable Automatic IBRS by default if the CPU feature is present. It typically provides greater performance over the incumbent generic retpolines mitigation. In addition: - Don't clear the RSB on VMEXIT when AutoIBRS is enabled: The internal return address stack used for return address predictions is automatically cleared on VMEXIT. - Automatic IBRS removes the need for toggling IBRS during firmware switches, so don't enable IBRS_FW when Automatic IBRS is enabled. - Allow for spectre_v2=autoibrs in the kernel command line, reverting to auto-selection if the feature isn't available. Signed-off-by: Kim Phillips --- .../admin-guide/kernel-parameters.txt | 1 + arch/x86/include/asm/msr-index.h | 2 ++ arch/x86/include/asm/nospec-branch.h | 1 + arch/x86/kernel/cpu/bugs.c | 34 +++++++++++++++++-- 4 files changed, 35 insertions(+), 3 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index a465d5242774..5ac4422e16a6 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5702,6 +5702,7 @@ eibrs,retpoline - enhanced IBRS + Retpolines eibrs,lfence - enhanced IBRS + LFENCE ibrs - use IBRS to protect kernel + autoibrs - AMD Automatic IBRS Not specifying this option is equivalent to spectre_v2=auto. diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 10ac52705892..bd73e509cfa6 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -30,6 +30,7 @@ #define _EFER_SVME 12 /* Enable virtualization */ #define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */ #define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */ +#define _EFER_AUTOIBRS 21 /* Automatic IBRS Enable */ #define EFER_SCE (1<<_EFER_SCE) #define EFER_LME (1<<_EFER_LME) @@ -38,6 +39,7 @@ #define EFER_SVME (1<<_EFER_SVME) #define EFER_LMSLE (1<<_EFER_LMSLE) #define EFER_FFXSR (1<<_EFER_FFXSR) +#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS) /* Intel MSRs. Some also available on other CPUs */ diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h index 82580adbca4b..12b2b070caab 100644 --- a/arch/x86/include/asm/nospec-branch.h +++ b/arch/x86/include/asm/nospec-branch.h @@ -442,6 +442,7 @@ enum spectre_v2_mitigation { SPECTRE_V2_EIBRS_RETPOLINE, SPECTRE_V2_EIBRS_LFENCE, SPECTRE_V2_IBRS, + SPECTRE_V2_AUTO_IBRS, }; /* The indirect branch speculation control variants */ diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c index 66d7addf1784..31e5af78baa0 100644 --- a/arch/x86/kernel/cpu/bugs.c +++ b/arch/x86/kernel/cpu/bugs.c @@ -1050,6 +1050,7 @@ enum spectre_v2_mitigation_cmd { SPECTRE_V2_CMD_EIBRS_RETPOLINE, SPECTRE_V2_CMD_EIBRS_LFENCE, SPECTRE_V2_CMD_IBRS, + SPECTRE_V2_CMD_AUTOIBRS, }; enum spectre_v2_user_cmd { @@ -1124,6 +1125,7 @@ spectre_v2_parse_user_cmdline(void) return SPECTRE_V2_USER_CMD_AUTO; } +/* Checks for Intel IBRS versions */ static inline bool spectre_v2_in_ibrs_mode(enum spectre_v2_mitigation mode) { return mode == SPECTRE_V2_IBRS || @@ -1233,6 +1235,7 @@ static const char * const spectre_v2_strings[] = { [SPECTRE_V2_EIBRS_LFENCE] = "Mitigation: Enhanced IBRS + LFENCE", [SPECTRE_V2_EIBRS_RETPOLINE] = "Mitigation: Enhanced IBRS + Retpolines", [SPECTRE_V2_IBRS] = "Mitigation: IBRS", + [SPECTRE_V2_AUTO_IBRS] = "Mitigation: Automatic IBRS", }; static const struct { @@ -1249,6 +1252,7 @@ static const struct { { "eibrs", SPECTRE_V2_CMD_EIBRS, false }, { "eibrs,lfence", SPECTRE_V2_CMD_EIBRS_LFENCE, false }, { "eibrs,retpoline", SPECTRE_V2_CMD_EIBRS_RETPOLINE, false }, + { "autoibrs", SPECTRE_V2_CMD_AUTOIBRS, false }, { "auto", SPECTRE_V2_CMD_AUTO, false }, { "ibrs", SPECTRE_V2_CMD_IBRS, false }, }; @@ -1305,6 +1309,13 @@ static enum spectre_v2_mitigation_cmd __init spectre_v2_parse_cmdline(void) return SPECTRE_V2_CMD_AUTO; } + if (cmd == SPECTRE_V2_CMD_AUTOIBRS && + !boot_cpu_has(X86_FEATURE_AUTOIBRS)) { + pr_err("%s selected but CPU doesn't have AMD Automatic IBRS. Switching to AUTO select\n", + mitigation_options[i].option); + return SPECTRE_V2_CMD_AUTO; + } + if ((cmd == SPECTRE_V2_CMD_RETPOLINE_LFENCE || cmd == SPECTRE_V2_CMD_EIBRS_LFENCE) && !boot_cpu_has(X86_FEATURE_LFENCE_RDTSC)) { @@ -1392,6 +1403,7 @@ static void __init spectre_v2_determine_rsb_fill_type_at_vmexit(enum spectre_v2_ */ switch (mode) { case SPECTRE_V2_NONE: + case SPECTRE_V2_AUTO_IBRS: return; case SPECTRE_V2_EIBRS_LFENCE: @@ -1419,6 +1431,7 @@ static void __init spectre_v2_select_mitigation(void) { enum spectre_v2_mitigation_cmd cmd = spectre_v2_parse_cmdline(); enum spectre_v2_mitigation mode = SPECTRE_V2_NONE; + uint64_t efer; /* * If the CPU is not affected and the command line mode is NONE or AUTO @@ -1434,6 +1447,11 @@ static void __init spectre_v2_select_mitigation(void) case SPECTRE_V2_CMD_FORCE: case SPECTRE_V2_CMD_AUTO: + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) { + mode = SPECTRE_V2_AUTO_IBRS; + break; + } + if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) { mode = SPECTRE_V2_EIBRS; break; @@ -1480,6 +1498,10 @@ static void __init spectre_v2_select_mitigation(void) case SPECTRE_V2_CMD_EIBRS_RETPOLINE: mode = SPECTRE_V2_EIBRS_RETPOLINE; break; + + case SPECTRE_V2_CMD_AUTOIBRS: + mode = SPECTRE_V2_AUTO_IBRS; + break; } if (mode == SPECTRE_V2_EIBRS && unprivileged_ebpf_enabled()) @@ -1495,6 +1517,11 @@ static void __init spectre_v2_select_mitigation(void) case SPECTRE_V2_EIBRS: break; + case SPECTRE_V2_AUTO_IBRS: + rdmsrl(MSR_EFER, efer); + wrmsrl(MSR_EFER, efer | EFER_AUTOIBRS); + break; + case SPECTRE_V2_IBRS: setup_force_cpu_cap(X86_FEATURE_KERNEL_IBRS); if (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED)) @@ -1571,8 +1598,8 @@ static void __init spectre_v2_select_mitigation(void) /* * Retpoline protects the kernel, but doesn't protect firmware. IBRS * and Enhanced IBRS protect firmware too, so enable IBRS around - * firmware calls only when IBRS / Enhanced IBRS aren't otherwise - * enabled. + * firmware calls only when IBRS / Enhanced / Automatic IBRS aren't + * otherwise enabled. * * Use "mode" to check Enhanced IBRS instead of boot_cpu_has(), because * the user might select retpoline on the kernel command line and if @@ -1589,7 +1616,8 @@ static void __init spectre_v2_select_mitigation(void) pr_info("Enabling Speculation Barrier for firmware calls\n"); } - } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode)) { + } else if (boot_cpu_has(X86_FEATURE_IBRS) && !spectre_v2_in_ibrs_mode(mode) && + mode != SPECTRE_V2_AUTO_IBRS) { setup_force_cpu_cap(X86_FEATURE_USE_IBRS_FW); pr_info("Enabling Restricted Speculation for firmware calls\n"); } From patchwork Fri Nov 4 21:36:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kim Phillips X-Patchwork-Id: 15809 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp651731wru; Fri, 4 Nov 2022 14:40:22 -0700 (PDT) X-Google-Smtp-Source: AMsMyM4jocbASqKcfbDBTAntfegNaIi6pQFkumqHr6i5C/u3Jb0jHUA6525kNSQHevGmhOpN0+kI X-Received: by 2002:a05:6402:22f1:b0:462:f6eb:6c6b with SMTP id dn17-20020a05640222f100b00462f6eb6c6bmr37291263edb.365.1667598021958; Fri, 04 Nov 2022 14:40:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1667598021; cv=pass; d=google.com; s=arc-20160816; b=PINuceE3N3Bo6r5e/Hn5YU1CuE4IPVUHROqD3rztvtH7T8bwxjOobtVJkjSPH7ZQcq oh10OFjLJQkA5BAbAriz/aOHBqlfF3sHxPnqPFa8Grre8+4/uP7kRQmyVlisO35kBwDn z196wpf/1G1ZjGu8kMAyyPpkgwcjPKDTkXnGswU0jh7foDOp6iPixT1qOKhptw/eWoGA xzjhN/WcH3bogqc9ZrwEBgZBmy9cJoc+9TmDp6xR0fja9uNC+o+dFtvHxm6IIfuj3rj8 o87VBNn/4Izwd2SlSHQtjNHFDbjHQQW3U88q8qLJaWRrYspHchXOVT05gJXOyosmaAF3 Ptjw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cZ0kXE0od6jlWKn9Xxo7jKgWznf16l2AgDC2oB9wId8=; b=tLXL9ZhRyPaQkSNeiJp3CjKgjOtTOMU37dyZ+67UcAkgEVgBzN9R0P5pFBa/yvPJt5 FtChU3xZ0Bt/39UFsbXL0R52G8ATAEyfYyjv1hie+gwnFHGfWGUnpu6xhG2tRy5oHGqg hjWrFCaO+yof0DefXZlGdULrkZAbdhHpYui6dMxgNtB1RC9QHCl7zifC/sh6Jc8aGFDI t7AiCXAX4NIZunmMWugn3OBZICc6yrRUTgZiNsJIlX+aHfiIhDInhid+iSY+icol7nMD SpcTZHwDBpjMTscq4KZ2SzXkORcQaKgBipEJn4gUFoxGk5Nw6dcG635x92KadM1J1Sp3 k9Yw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=gq9znmdW; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Co-developed-by: Babu Moger Signed-off-by: Kim Phillips --- arch/x86/kvm/cpuid.c | 5 ++++- arch/x86/kvm/reverse_cpuid.h | 1 + arch/x86/kvm/svm/svm.c | 3 +++ arch/x86/kvm/x86.c | 3 +++ 4 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 7065462378e2..2524cd82627b 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -730,6 +730,8 @@ void kvm_set_cpu_caps(void) 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | F(SME_COHERENT)); + kvm_cpu_cap_mask(CPUID_8000_0021_EAX, F(AUTOIBRS)); + kvm_cpu_cap_mask(CPUID_C000_0001_EDX, F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | @@ -1211,12 +1213,13 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) * EAX 0 NNDBP, Processor ignores nested data breakpoints * EAX 2 LAS, LFENCE always serializing * EAX 6 NSCB, Null selector clear base + * EAX 8 Automatic IBRS * * Other defined bits are for MSRs that KVM does not expose: * EAX 3 SPCL, SMM page configuration lock * EAX 13 PCMSR, Prefetch control MSR */ - entry->eax &= BIT(0) | BIT(2) | BIT(6); + entry->eax &= BIT(0) | BIT(2) | BIT(6) | BIT(8); if (static_cpu_has(X86_FEATURE_LFENCE_RDTSC)) entry->eax |= BIT(2); if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index a19d473d0184..7eeade35a425 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -48,6 +48,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_7_1_EAX] = { 7, 1, CPUID_EAX}, [CPUID_12_EAX] = {0x00000012, 0, CPUID_EAX}, [CPUID_8000_001F_EAX] = {0x8000001f, 0, CPUID_EAX}, + [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, }; /* diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 58f0077d9357..2add5eb3303f 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4993,6 +4993,9 @@ static __init int svm_hardware_setup(void) tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX); + if (boot_cpu_has(X86_FEATURE_AUTOIBRS)) + kvm_enable_efer_bits(EFER_AUTOIBRS); + /* Check for pause filtering support */ if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) { pause_filter_count = 0; diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index 9cf1ba865562..3dbeda353853 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1687,6 +1687,9 @@ static int do_get_msr_feature(struct kvm_vcpu *vcpu, unsigned index, u64 *data) static bool __kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer) { + if (efer & EFER_AUTOIBRS && !guest_cpuid_has(vcpu, X86_FEATURE_AUTOIBRS)) + return false; + if (efer & EFER_FFXSR && !guest_cpuid_has(vcpu, X86_FEATURE_FXSR_OPT)) return false;