From patchwork Mon Oct 2 11:59:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147448 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1659500vqb; Mon, 2 Oct 2023 13:00:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHID9Zhb6075cBPR8er9HsZaOo1dpERDDsnpyQNqcShNXlQLvuSitNt0thHmIQ9RuxfDMlJ X-Received: by 2002:a05:6808:3613:b0:3ae:108d:acee with SMTP id ct19-20020a056808361300b003ae108daceemr11317238oib.1.1696276847983; Mon, 02 Oct 2023 13:00:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696276847; cv=none; d=google.com; s=arc-20160816; b=VkUxuPJUv0UMG0WZ/U2drj1i6bEgc6vZKXb+/SEfX9MvMraor86saqYRtqIQsVoFP9 PIj5AQFYNNDNa6HPoA0/2wN+Jf2RbGFdZsD0euMAbfutkenctTE1p2HOxqyUD7MLOt0E N52dvodO+DyWbQaJdboGM9+4Y3qITyjx4D7tsklW+uJPmlaKehBoK07sCtmw7nUa8AUH dNSWkxJn+FOZGs7nphizUjEqGjyJVAzHMaVEQeEdPOHlroLztUNAYLkEfun2SsukEhN0 qXAyXFlUi/FP0vxQ1PHII4LeFxkrQCIHUe18wD6kGsP6fV+3yjK4No9S+asS42XZUai3 NUdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=b9icZ312K2wzs7HqQwN4x/Zs/AsYDehC0Dvj7D8ghOo=; fh=HxDzQ6PpfGskWPjhN1cA9fZ24R2R+GZAlvKaaxU0Ayo=; b=d/IueVJjVOkvyllNUtq7erGBUblQIsibVIBzQP5ccNaYVtRpuv1a0iMTnMubFjb8R9 nzNYyWUCQzSIrh3bWFBMuM2YNA/zHSrvz5KhlliqKPqieAmSpKu4c2eHUfj3FPwEO9Xd 9vqSRg4Eq6L8fJd3LAyNs5V9u7Yg8ODxcrxjYG2dyROkRO8pXYXxJiftVSY9ldQlO/TI juY/5/HBbG/wCTI8qVWKcyJaIASZ9DpUTcCzaZEYKPKTFW02MZyQ5of1ysGHmn25DVNS DYGSMiY8qrtFvy9yXYicLzVk0eKdVX9B12tJyVvdXo2DT6c7u6a2z/NTlRt68k1zbdpA 5yAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=H44BLFa2; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id dc15-20020a056a0035cf00b00690cb77d5e5si23998653pfb.394.2023.10.02.13.00.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 13:00:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=H44BLFa2; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 327F480787C9; Mon, 2 Oct 2023 05:00:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236861AbjJBL7q (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60702 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236833AbjJBL7m (ORCPT ); Mon, 2 Oct 2023 07:59:42 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 99E42C6 for ; Mon, 2 Oct 2023 04:59:37 -0700 (PDT) Message-ID: <20231002115902.096543357@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247975; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b9icZ312K2wzs7HqQwN4x/Zs/AsYDehC0Dvj7D8ghOo=; b=H44BLFa2FnIXFcaMuSp2X3fkAWBA7PqjYUOuME9E23xgFAkClaanwd0cjU23eD+KBi4Y7C 6rZA9aqUquKXwwSdkZ6H4BAoPsNq6bZ6tA34TA4H7pJ829SR1aMHvQ4UCgEdlBQPahVNmq k7h6sp79E+MBdfiBY9oHDbLVM5wn57D5yv9pU74JwZZvdiqDv8SsGbyXNhTtdiThzPPosU Wx6C9HE+Z/fTHEi4EdSIjswbtKAZwsRyk6w11IFJRLk/vHciP4XhXmyFCJsN59D9CLuDb8 IyiAHq48nVAPkPZyTtbrKRqIo5nZ8MroEkTYn12yBAhbJcpG0XC1Mvuow0ftlQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247975; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=b9icZ312K2wzs7HqQwN4x/Zs/AsYDehC0Dvj7D8ghOo=; b=8+vhkpQHPzIXZRonRNhrNVU/tU7FzBy58vfqojg6zi1GtS8EHr7YQZGHtmqQrclz+9eErU Zq0dvwnlY4h93vBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov , Fenghua Yu , Peter Anvin Subject: [patch V4 01/30] x86/microcode/32: Move early loading after paging enable References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:35 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778675191890203106 X-GMAIL-MSGID: 1778675191890203106 32-bit loads microcode before paging is enabled. The commit which introduced that has zero justification in the changelog. The cover letter has slightly more content, but it does not give any technical justification either: "The problem in current microcode loading method is that we load a microcode way, way too late; ideally we should load it before turning paging on. This may only be practical on 32 bits since we can't get to 64-bit mode without paging on, but we should still do it as early as at all possible." Handwaving word salad with zero technical content. Someone claimed in an offlist conversation that this is required for curing the ATOM erratum AAE44/AAF40/AAG38/AAH41. That erratum requires an microcode update in order to make the usage of PSE safe. But during early boot PSE is completely irrelevant and it is evaluated way later. Neither is it relevant for the AP on single core HT enabled CPUs as the microcode loading on the AP is not doing anything. On dual core CPUs there is a theoretical problem if a split of an executable large page between enabling paging including PSE and loading the microcode happens. But that's only theoretical, it's practically irrelevant because the affected dual core CPUs are 64bit enabled and therefore have paging and PSE enabled before loading the microcode on the second core. So why would it work on 64-bit but not on 32-bit? The erratum: "AAG38 Code Fetch May Occur to Incorrect Address After a Large Page is Split Into 4-Kbyte Pages Problem: If software clears the PS (page size) bit in a present PDE (page directory entry), that will cause linear addresses mapped through this PDE to use 4-KByte pages instead of using a large page after old TLB entries are invalidated. Due to this erratum, if a code fetch uses this PDE before the TLB entry for the large page is invalidated then it may fetch from a different physical address than specified by either the old large page translation or the new 4-KByte page translation. This erratum may also cause speculative code fetches from incorrect addresses." The practical relevance for this is exactly zero because there is no splitting of large text pages during early boot-time, i.e. between paging enable and microcode loading, and neither during CPU hotplug. IOW, this load microcode before paging enable is yet another voodoo programming solution in search of a problem. What's worse is that it causes at least two serious problems: 1) When stackprotector is enabled then the microcode loader code has the stackprotector mechanics enabled. The read from the per CPU variable __stack_chk_guard is always accessing the virtual address either directly on UP or via FS on SMP. In physical address mode this results in an access to memory above 3GB. So this works by chance as the hardware returns the same value when there is no RAM at this physical address. When there is RAM populated above 3G then the read is by chance the same as nothing changes that memory during the very early boot stage. That's not necessarily true during runtime CPU hotplug. 2) When function tracing is enabled, then the relevant microcode loader functions and the functions invoked from there will call into the tracing code and evaluate global and per CPU variables in physical address mode. What could potentially go wrong? Cure this and move the microcode loading after the early paging enable and remove the gunk in the microcode loader which is required to handle physical address mode. Signed-off-by: Thomas Gleixner Cc: Fenghua Yu Cc: Peter Anvin Link: https://lore.kernel.org/lkml/1356075872-3054-1-git-send-email-fenghua.yu@intel.com --- V3: Remove the early arguments - Chang Fixup the core code - 0day --- arch/x86/include/asm/microcode.h | 5 - arch/x86/kernel/cpu/common.c | 12 --- arch/x86/kernel/cpu/microcode/amd.c | 103 ++++++++------------------- arch/x86/kernel/cpu/microcode/core.c | 73 ++++--------------- arch/x86/kernel/cpu/microcode/intel.c | 116 ++++--------------------------- arch/x86/kernel/cpu/microcode/internal.h | 2 arch/x86/kernel/head32.c | 3 arch/x86/kernel/head_32.S | 10 -- arch/x86/kernel/smpboot.c | 12 +-- 9 files changed, 71 insertions(+), 265 deletions(-) --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -68,11 +68,6 @@ static inline u32 intel_get_microcode_re return rev; } - -void show_ucode_info_early(void); - -#else /* CONFIG_CPU_SUP_INTEL */ -static inline void show_ucode_info_early(void) { } #endif /* !CONFIG_CPU_SUP_INTEL */ #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2166,8 +2166,6 @@ static inline void setup_getcpu(int cpu) } #ifdef CONFIG_X86_64 -static inline void ucode_cpu_init(int cpu) { } - static inline void tss_setup_ist(struct tss_struct *tss) { /* Set up the per-CPU TSS IST stacks */ @@ -2178,16 +2176,8 @@ static inline void tss_setup_ist(struct /* Only mapped when SEV-ES is active */ tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); } - #else /* CONFIG_X86_64 */ - -static inline void ucode_cpu_init(int cpu) -{ - show_ucode_info_early(); -} - static inline void tss_setup_ist(struct tss_struct *tss) { } - #endif /* !CONFIG_X86_64 */ static inline void tss_setup_io_bitmap(struct tss_struct *tss) @@ -2243,8 +2233,6 @@ void cpu_init(void) struct task_struct *cur = current; int cpu = raw_smp_processor_id(); - ucode_cpu_init(cpu); - #ifdef CONFIG_NUMA if (this_cpu_read(numa_node) == 0 && early_cpu_to_node(cpu) != NUMA_NO_NODE) --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -121,24 +121,20 @@ static u16 find_equiv_id(struct equiv_cp /* * Check whether there is a valid microcode container file at the beginning - * of @buf of size @buf_size. Set @early to use this function in the early path. + * of @buf of size @buf_size. */ -static bool verify_container(const u8 *buf, size_t buf_size, bool early) +static bool verify_container(const u8 *buf, size_t buf_size) { u32 cont_magic; if (buf_size <= CONTAINER_HDR_SZ) { - if (!early) - pr_debug("Truncated microcode container header.\n"); - + pr_debug("Truncated microcode container header.\n"); return false; } cont_magic = *(const u32 *)buf; if (cont_magic != UCODE_MAGIC) { - if (!early) - pr_debug("Invalid magic value (0x%08x).\n", cont_magic); - + pr_debug("Invalid magic value (0x%08x).\n", cont_magic); return false; } @@ -147,23 +143,20 @@ static bool verify_container(const u8 *b /* * Check whether there is a valid, non-truncated CPU equivalence table at the - * beginning of @buf of size @buf_size. Set @early to use this function in the - * early path. + * beginning of @buf of size @buf_size. */ -static bool verify_equivalence_table(const u8 *buf, size_t buf_size, bool early) +static bool verify_equivalence_table(const u8 *buf, size_t buf_size) { const u32 *hdr = (const u32 *)buf; u32 cont_type, equiv_tbl_len; - if (!verify_container(buf, buf_size, early)) + if (!verify_container(buf, buf_size)) return false; cont_type = hdr[1]; if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) { - if (!early) - pr_debug("Wrong microcode container equivalence table type: %u.\n", - cont_type); - + pr_debug("Wrong microcode container equivalence table type: %u.\n", + cont_type); return false; } @@ -172,9 +165,7 @@ static bool verify_equivalence_table(con equiv_tbl_len = hdr[2]; if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) || buf_size < equiv_tbl_len) { - if (!early) - pr_debug("Truncated equivalence table.\n"); - + pr_debug("Truncated equivalence table.\n"); return false; } @@ -183,22 +174,19 @@ static bool verify_equivalence_table(con /* * Check whether there is a valid, non-truncated microcode patch section at the - * beginning of @buf of size @buf_size. Set @early to use this function in the - * early path. + * beginning of @buf of size @buf_size. * * On success, @sh_psize returns the patch size according to the section header, * to the caller. */ static bool -__verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize, bool early) +__verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize) { u32 p_type, p_size; const u32 *hdr; if (buf_size < SECTION_HDR_SIZE) { - if (!early) - pr_debug("Truncated patch section.\n"); - + pr_debug("Truncated patch section.\n"); return false; } @@ -207,17 +195,13 @@ static bool p_size = hdr[1]; if (p_type != UCODE_UCODE_TYPE) { - if (!early) - pr_debug("Invalid type field (0x%x) in container file section header.\n", - p_type); - + pr_debug("Invalid type field (0x%x) in container file section header.\n", + p_type); return false; } if (p_size < sizeof(struct microcode_header_amd)) { - if (!early) - pr_debug("Patch of size %u too short.\n", p_size); - + pr_debug("Patch of size %u too short.\n", p_size); return false; } @@ -269,7 +253,7 @@ static unsigned int __verify_patch_size( * 0: success */ static int -verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size, bool early) +verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size) { struct microcode_header_amd *mc_hdr; unsigned int ret; @@ -277,7 +261,7 @@ verify_patch(u8 family, const u8 *buf, s u16 proc_id; u8 patch_fam; - if (!__verify_patch_section(buf, buf_size, &sh_psize, early)) + if (!__verify_patch_section(buf, buf_size, &sh_psize)) return -1; /* @@ -292,16 +276,13 @@ verify_patch(u8 family, const u8 *buf, s * size sh_psize, as the section claims. */ if (buf_size < sh_psize) { - if (!early) - pr_debug("Patch of size %u truncated.\n", sh_psize); - + pr_debug("Patch of size %u truncated.\n", sh_psize); return -1; } ret = __verify_patch_size(family, sh_psize, buf_size); if (!ret) { - if (!early) - pr_debug("Per-family patch size mismatch.\n"); + pr_debug("Per-family patch size mismatch.\n"); return -1; } @@ -309,8 +290,7 @@ verify_patch(u8 family, const u8 *buf, s mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE); if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { - if (!early) - pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id); + pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id); return -1; } @@ -337,7 +317,7 @@ static size_t parse_container(u8 *ucode, u16 eq_id; u8 *buf; - if (!verify_equivalence_table(ucode, size, true)) + if (!verify_equivalence_table(ucode, size)) return 0; buf = ucode; @@ -364,7 +344,7 @@ static size_t parse_container(u8 *ucode, u32 patch_size; int ret; - ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size, true); + ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size); if (ret < 0) { /* * Patch verification failed, skip to the next container, if @@ -456,14 +436,8 @@ static bool early_apply_microcode(u32 cp { struct cont_desc desc = { 0 }; struct microcode_amd *mc; - u32 rev, dummy, *new_rev; bool ret = false; - -#ifdef CONFIG_X86_32 - new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); -#else - new_rev = &ucode_new_rev; -#endif + u32 rev, dummy; desc.cpuid_1_eax = cpuid_1_eax; @@ -484,8 +458,8 @@ static bool early_apply_microcode(u32 cp return ret; if (!__apply_microcode_amd(mc)) { - *new_rev = mc->hdr.patch_id; - ret = true; + ucode_new_rev = mc->hdr.patch_id; + ret = true; } return ret; @@ -514,26 +488,13 @@ static bool get_builtin_microcode(struct static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret) { - struct ucode_cpu_info *uci; struct cpio_data cp; - const char *path; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info); - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - uci = ucode_cpu_info; - path = ucode_path; - use_pa = false; - } if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax))) - cp = find_microcode_in_initrd(path, use_pa); + cp = find_microcode_in_initrd(ucode_path); /* Needed in load_microcode_amd() */ - uci->cpu_sig.sig = cpuid_1_eax; + ucode_cpu_info->cpu_sig.sig = cpuid_1_eax; *ret = cp; } @@ -562,7 +523,7 @@ int __init save_microcode_in_initrd_amd( enum ucode_state ret; struct cpio_data cp; - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return -EINVAL; @@ -738,7 +699,7 @@ static size_t install_equiv_cpu_table(co u32 equiv_tbl_len; const u32 *hdr; - if (!verify_equivalence_table(buf, buf_size, false)) + if (!verify_equivalence_table(buf, buf_size)) return 0; hdr = (const u32 *)buf; @@ -784,7 +745,7 @@ static int verify_and_add_patch(u8 famil u16 proc_id; int ret; - ret = verify_patch(family, fw, leftover, patch_size, false); + ret = verify_patch(family, fw, leftover, patch_size); if (ret) return ret; @@ -918,7 +879,7 @@ static enum ucode_state request_microcod } ret = UCODE_ERROR; - if (!verify_container(fw->data, fw->size, false)) + if (!verify_container(fw->data, fw->size)) goto fw_release; ret = load_microcode_amd(c->x86, fw->data, fw->size); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -90,10 +90,7 @@ static bool amd_check_current_patch_leve native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); - if (IS_ENABLED(CONFIG_X86_32)) - levels = (u32 *)__pa_nodebug(&final_levels); - else - levels = final_levels; + levels = final_levels; for (i = 0; levels[i]; i++) { if (lvl == levels[i]) @@ -105,17 +102,8 @@ static bool amd_check_current_patch_leve static bool __init check_loader_disabled_bsp(void) { static const char *__dis_opt_str = "dis_ucode_ldr"; - -#ifdef CONFIG_X86_32 - const char *cmdline = (const char *)__pa_nodebug(boot_command_line); - const char *option = (const char *)__pa_nodebug(__dis_opt_str); - bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); - -#else /* CONFIG_X86_64 */ const char *cmdline = boot_command_line; const char *option = __dis_opt_str; - bool *res = &dis_ucode_ldr; -#endif /* * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not @@ -123,17 +111,17 @@ static bool __init check_loader_disabled * that's good enough as they don't land on the BSP path anyway. */ if (native_cpuid_ecx(1) & BIT(31)) - return *res; + return true; if (x86_cpuid_vendor() == X86_VENDOR_AMD) { if (amd_check_current_patch_level()) - return *res; + return true; } if (cmdline_find_option_bool(cmdline, option) <= 0) - *res = false; + dis_ucode_ldr = false; - return *res; + return dis_ucode_ldr; } void __init load_ucode_bsp(void) @@ -171,20 +159,11 @@ void __init load_ucode_bsp(void) load_ucode_amd_early(cpuid_1_eax); } -static bool check_loader_disabled_ap(void) -{ -#ifdef CONFIG_X86_32 - return *((bool *)__pa_nodebug(&dis_ucode_ldr)); -#else - return dis_ucode_ldr; -#endif -} - void load_ucode_ap(void) { unsigned int cpuid_1_eax; - if (check_loader_disabled_ap()) + if (dis_ucode_ldr) return; cpuid_1_eax = native_cpuid_eax(1); @@ -226,40 +205,31 @@ static int __init save_microcode_in_init return ret; } -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) +struct cpio_data find_microcode_in_initrd(const char *path) { #ifdef CONFIG_BLK_DEV_INITRD unsigned long start = 0; size_t size; #ifdef CONFIG_X86_32 - struct boot_params *params; - - if (use_pa) - params = (struct boot_params *)__pa_nodebug(&boot_params); - else - params = &boot_params; - - size = params->hdr.ramdisk_size; - + size = boot_params.hdr.ramdisk_size; /* * Set start only if we have an initrd image. We cannot use initrd_start * because it is not set that early yet. */ if (size) - start = params->hdr.ramdisk_image; + start = boot_params.hdr.ramdisk_image; -# else /* CONFIG_X86_64 */ +#else /* CONFIG_X86_64 */ size = (unsigned long)boot_params.ext_ramdisk_size << 32; size |= boot_params.hdr.ramdisk_size; if (size) { start = (unsigned long)boot_params.ext_ramdisk_image << 32; start |= boot_params.hdr.ramdisk_image; - start += PAGE_OFFSET; } -# endif +#endif /* * Fixup the start address: after reserve_initrd() runs, initrd_start @@ -270,23 +240,10 @@ struct cpio_data find_microcode_in_initr * initrd_gone is for the hotplug case where we've thrown out initrd * already. */ - if (!use_pa) { - if (initrd_gone) - return (struct cpio_data){ NULL, 0, "" }; - if (initrd_start) - start = initrd_start; - } else { - /* - * The picture with physical addresses is a bit different: we - * need to get the *physical* address to which the ramdisk was - * relocated, i.e., relocated_ramdisk (not initrd_start) and - * since we're running from physical addresses, we need to access - * relocated_ramdisk through its *physical* address too. - */ - u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk); - if (*rr) - start = *rr; - } + if (initrd_gone) + return (struct cpio_data){ NULL, 0, "" }; + if (initrd_start) + start = initrd_start; return find_cpio_data(path, (void *)start, size, NULL); #else /* !CONFIG_BLK_DEV_INITRD */ --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -319,15 +319,8 @@ static void save_microcode_patch(struct if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) return; - /* - * Save for early loading. On 32-bit, that needs to be a physical - * address as the APs are running from physical addresses, before - * paging has been enabled. - */ - if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); - else - intel_ucode_patch = p->data; + /* Save for early loading */ + intel_ucode_patch = p->data; } /* @@ -420,66 +413,10 @@ static bool load_builtin_intel_microcode return false; } -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) -{ - pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, - new_rev, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); -} - -#ifdef CONFIG_X86_32 - -static int delay_ucode_info; -static int current_mc_date; -static int early_old_rev; - -/* - * Print early updated ucode info after printk works. This is delayed info dump. - */ -void show_ucode_info_early(void) -{ - struct ucode_cpu_info uci; - - if (delay_ucode_info) { - intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); - delay_ucode_info = 0; - } -} - -/* - * At this point, we can not call printk() yet. Delay printing microcode info in - * show_ucode_info_early() until printk() works. - */ -static void print_ucode(int old_rev, int new_rev, int date) -{ - int *delay_ucode_info_p; - int *current_mc_date_p; - int *early_old_rev_p; - - delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); - current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); - early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); - - *delay_ucode_info_p = 1; - *current_mc_date_p = date; - *early_old_rev_p = old_rev; -} -#else - -static inline void print_ucode(int old_rev, int new_rev, int date) -{ - print_ucode_info(old_rev, new_rev, date); -} -#endif - -static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static int apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; - u32 rev, old_rev; + u32 rev, old_rev, date; mc = uci->mc; if (!mc) @@ -513,11 +450,9 @@ static int apply_microcode_early(struct uci->cpu_sig.rev = rev; - if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); - else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); - + date = mc->hdr.date; + pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); return 0; } @@ -535,7 +470,7 @@ int __init save_microcode_in_initrd_inte intel_ucode_patch = NULL; if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return 0; @@ -551,21 +486,11 @@ int __init save_microcode_in_initrd_inte */ static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) { - static const char *path; struct cpio_data cp; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - path = ucode_path; - use_pa = false; - } /* try built-in microcode first */ if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(path, use_pa); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return NULL; @@ -586,30 +511,21 @@ void __init load_ucode_intel_bsp(void) uci.mc = patch; - apply_microcode_early(&uci, true); + apply_microcode_early(&uci); } void load_ucode_intel_ap(void) { - struct microcode_intel *patch, **iup; struct ucode_cpu_info uci; - if (IS_ENABLED(CONFIG_X86_32)) - iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); - else - iup = &intel_ucode_patch; - - if (!*iup) { - patch = __load_ucode_intel(&uci); - if (!patch) + if (!intel_ucode_patch) { + intel_ucode_patch = __load_ucode_intel(&uci); + if (!intel_ucode_patch) return; - - *iup = patch; } - uci.mc = *iup; - - apply_microcode_early(&uci, true); + uci.mc = intel_ucode_patch; + apply_microcode_early(&uci); } static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) @@ -647,7 +563,7 @@ void reload_ucode_intel(void) uci.mc = p; - apply_microcode_early(&uci, false); + apply_microcode_early(&uci); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -44,7 +44,7 @@ struct microcode_ops { }; extern struct ucode_cpu_info ucode_cpu_info[]; -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); +struct cpio_data find_microcode_in_initrd(const char *path); #define MAX_UCODE_COUNT 128 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -34,6 +35,8 @@ asmlinkage __visible void __init __noret /* Make sure IDT is set up before any exception happens */ idt_setup_early_handler(); + load_ucode_bsp(); + cr4_init_shadow(); sanitize_boot_params(&boot_params); --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -118,11 +118,6 @@ SYM_CODE_START(startup_32) movl %eax, pa(olpc_ofw_pgd) #endif -#ifdef CONFIG_MICROCODE - /* Early load ucode on BSP. */ - call load_ucode_bsp -#endif - /* Create early pagetables. */ call mk_early_pgtbl_32 @@ -157,11 +152,6 @@ SYM_FUNC_START(startup_32_smp) movl %eax,%ss leal -__PAGE_OFFSET(%ecx),%esp -#ifdef CONFIG_MICROCODE - /* Early load ucode on AP. */ - call load_ucode_ap -#endif - .Ldefault_entry: movl $(CR0_STATE & ~X86_CR0_PG),%eax movl %eax,%cr0 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -258,12 +258,9 @@ static void notrace start_secondary(void cpu_init_exception_handling(); /* - * 32-bit systems load the microcode from the ASM startup code for - * historical reasons. - * - * On 64-bit systems load it before reaching the AP alive - * synchronization point below so it is not part of the full per - * CPU serialized bringup part when "parallel" bringup is enabled. + * Load the microcode before reaching the AP alive synchronization + * point below so it is not part of the full per CPU serialized + * bringup part when "parallel" bringup is enabled. * * That's even safe when hyperthreading is enabled in the CPU as * the core code starts the primary threads first and leaves the @@ -276,8 +273,7 @@ static void notrace start_secondary(void * CPUID, MSRs etc. must be strictly serialized to maintain * software state correctness. */ - if (IS_ENABLED(CONFIG_X86_64)) - load_ucode_ap(); + load_ucode_ap(); /* * Synchronization point with the hotplug core. Sets this CPUs From patchwork Mon Oct 2 11:59:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147516 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1719361vqb; Mon, 2 Oct 2023 15:11:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG7vnoHKuP9klsfPVGFh8dfvq4NB8PK3DnhnwGEWFIOrfrMe1bKeh4mET9Q+5puYEZgGDCA X-Received: by 2002:a17:903:1ca:b0:1c5:9d00:be84 with SMTP id e10-20020a17090301ca00b001c59d00be84mr1290186plh.33.1696284682286; Mon, 02 Oct 2023 15:11:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284682; cv=none; d=google.com; s=arc-20160816; b=nVRE5w4AY5L5TRZIxjt2qXJX9B3qgUipXobMuUaYtZM571f7iKfNHtouGrs5vMWHKB zDmglrWKh+Wmpxf6H/MwPz6O20WrZmZgwZRcjnoxkb/fo2/iqyXIRjiWLwkn7DojzLPd xFrgODbRRtHvsd7KxMHAtwmCxZO3m3b1CZjY2Q2bWxKHbAsP0ERNSkdFB+kFBCtpPBUu mbzYfxr0d+D7lUocgieIvSt9htcqhnY7NctKBdTphReurQc3Vz6ClUg1zu2QHCv6kGAk viwcpaDh6hW9IrvUpo58tOexJUey4y8SRxeOeMZW4wFOr6vMbBG3I1d7FItkgfUV3X1F gxmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MpCnK67GELVxPmL+nKHxE4OtoLy/US/2UWS6ahSC0yw=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=FT5zpGzeCO2BbPSZSnLcCAiVIDASPOaXJTT0nHYCRMLSBWGaY0NGNav9HZzAt1S+0P ufzfokiYm2tkdrHsS4OmiVj5isveNQ+TpITaGaYw6GLAvjFKUQEoJp2DS1YvZAMUusxY Y0pp1YYjSa0/MWua3fEReIzuMh1y7jjNMTzmxttJ6MFMXjJNBkYGTsi+eK/Kk7JJbsfv rDHoxGqk4Yx1D6eF9/n5jH2GdZQ93arVmfCcbJPCxAZY5RjTrkX1dOF8jYaMdJEawY4+ FRED+Yh6gmgbNdI+UVE7ZMilAVcVbnYqXEuQWmrBA7GsBCjPH+Rld9bW56bYaZIoEdFl YGUQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KKzAKlH7; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=HHGzqGpD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id c15-20020a170902d48f00b001b81fe65fa3si30718573plg.569.2023.10.02.15.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:11:22 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KKzAKlH7; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=HHGzqGpD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id C16DD8106780; Mon, 2 Oct 2023 04:59:48 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236841AbjJBL7o (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60686 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236801AbjJBL7l (ORCPT ); Mon, 2 Oct 2023 07:59:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6EA52D3 for ; Mon, 2 Oct 2023 04:59:38 -0700 (PDT) Message-ID: <20231002115902.156063939@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MpCnK67GELVxPmL+nKHxE4OtoLy/US/2UWS6ahSC0yw=; b=KKzAKlH7CbuBMSxI0yGr7SlgHQhn+BM3XhYs8LN3BViOeoy3EZ6qW48HIPZzUZlrHdv5WN R5bekrTnkJzZNRLV4bTmaf/nV6spDCSibVbXD3u15tP3W7P5GafrnJ2v/LyjWQLoCCNd6p nVGLth1Rs3cDzIOxz6fxoS3UMDt4h6gPoNO0K6yuSyR9i3mWUZr66jYrSbCHsoYGQYR6p1 J20dij6nXx0ThVltKAvpki2v8LLDO03C+EaCb81R1p9TLtyPTU49sFzOmKfctYf+ib9SNM DmvUK6r9ZDJd0Ax+LsybxI6muT8/oD9p41i/V4uDB63Xqkq9h5L9hp1q3M0PBw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247977; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MpCnK67GELVxPmL+nKHxE4OtoLy/US/2UWS6ahSC0yw=; b=HHGzqGpDHgoB65PMZaOFO1tJw+6BVaXiVwp8FJCDZpuiCtek8/uBNemv8bq4pViA56iZdt 2E2nPs1TqqOIfbDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 02/30] x86/boot/32: Disable stackprotector and tracing for mk_early_pgtbl_32() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:36 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 04:59:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778683407152020721 X-GMAIL-MSGID: 1778683407152020721 Stackprotector cannot work before paging is enabled. The read from the per CPU variable __stack_chk_guard is always accessing the virtual address either directly on UP or via FS on SMP. In physical address mode this results in an access to memory above 3GB. So this works by chance as the hardware returns the same value when there is no RAM at this physical address. When there is RAM populated above 3G then the read is by chance the same as nothing changes that memory during the very early boot stage. Stop relying on pure luck and disable the stack protector for the only C function which is called during early boot before paging is enabled. Remove function tracing from the whole source file as there is no way to trace this at all, but in case of CONFIG_DYNAMIC_FTRACE=n mk_early_pgtbl_32() would access global function tracer variables in physical address mode which again might work by chance. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/Makefile | 1 + arch/x86/kernel/head32.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -16,6 +16,7 @@ CFLAGS_REMOVE_kvmclock.o = -pg CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_early_printk.o = -pg CFLAGS_REMOVE_head64.o = -pg +CFLAGS_REMOVE_head32.o = -pg CFLAGS_REMOVE_sev.o = -pg CFLAGS_REMOVE_rethook.o = -pg endif --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -73,7 +73,8 @@ asmlinkage __visible void __init __noret * always zero at this stage. */ void __init mk_early_pgtbl_32(void); -void __init mk_early_pgtbl_32(void) + +void __init __no_stack_protector mk_early_pgtbl_32(void) { #ifdef __pa #undef __pa From patchwork Mon Oct 2 11:59:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147399 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1582304vqb; Mon, 2 Oct 2023 10:33:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFXqWqCHh7NpvPumaKgEKr+NXan7+hlxdCZuql8G/CmAYXj1ORM8RNlT1Q/nfSBri39dtXc X-Received: by 2002:a05:6870:d10d:b0:1c7:ebf5:b6cb with SMTP id e13-20020a056870d10d00b001c7ebf5b6cbmr14663395oac.25.1696268027142; Mon, 02 Oct 2023 10:33:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696268027; cv=none; d=google.com; s=arc-20160816; b=Y4MMfoBzffWQI3zygK0X1ubVVCptE6DwHizHusAn97ajh/b+0F1ynlbA132JNfPgnD WXfn95NAqBKTlPPE3WC4SW0jTqVHh1jc0faVKAgfc01kCetpPEmlEL6TIhHR1FYMHW3S kxWw/Fjff2kRxevkp2IchTRM4cpV10xfmMPysu8Y23ctJ+B/Mqyi75bA1BfXGAkO6dML CMSX4sVr2MKY76N3vk46vITIHGYO50LOnRBoV2yWomqCjmrnOHB1alVjjZFWfy3dB2c7 znLaTGsCBNIA7BulZ9J482EIJkt4B6+pZeKbUjWWyLvepEfY1zhXXmozi3CuVHPSlidU WRhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=CKvapOYaUPsH2+8DKIbmLFaJiDGN1JuOSLBUKN32EsI=; fh=Fw4dspu3lEWS7xf2bQx5+rNTgFONiGLilI8487/7QuM=; b=E3hyl0uks/j/HWUYxCjmM6gUyPcrsqLAvG4Pj5p5upgA4qu3tfI1vYtim4Cs8pCwOt Y7CYiAWuS+LXB/7PLAhsd6Fxr7n/9br5MSw6Bp6hCuBTqr3c8i5syekFqQuuPMf9U7Qi 1ZwM2WDcsm9Oo0usBp236pnHmNYhT38Cnu2rGnuDSRhzCD9ACrE7rP2c2DXw3Beeh8Hi mdSqI7i3uYO0d9rR56csVXf3Yv/Ry1/HcVxjCuoqvEBiHSCndQrnwP6uqSuQomHSylaM cPWSo7etQl6iZCnxjB7AnIoDP8Gy/mZ8HE+qchX4z1JKcHEkpzsDtVipIxwSzUvzxU9h U/GA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=m84KreSB; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=nksenEkd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id l187-20020a6391c4000000b005859baa2aa9si8396573pge.567.2023.10.02.10.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 10:33:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=m84KreSB; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=nksenEkd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D8406810681C; Mon, 2 Oct 2023 05:00:00 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236852AbjJBL7s (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236836AbjJBL7n (ORCPT ); Mon, 2 Oct 2023 07:59:43 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC46994 for ; Mon, 2 Oct 2023 04:59:39 -0700 (PDT) Message-ID: <20231002115902.213619654@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247978; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CKvapOYaUPsH2+8DKIbmLFaJiDGN1JuOSLBUKN32EsI=; b=m84KreSBFovaV4BOzgDOWreokhOxfK9A+wMj+LuJ0XPhEgXFLHy9zdc5sXziXnfKLWP1OX 1rYK4apM5+kNHTcwdEA9wbzzRIg/dhXRRe36eJqoPVzJ2ACcbNAz/fx/YxZ8wesE/pbcVR 5/T3cFfIakVlEf6tw9miub9iPZAoxatIQWTg32ZXJvE01E77BHyYr26fmL0xovUmm+sqPC HvSFhpUuYRhLFuFUun8DVSMquDT9P7soWzbxGH8ARG+RQKezUifZuh/EGEPOWtS3nWIXfQ kN0fLo60F5d6DKIKnIC7p9MOCAKSDBQkQUOn7RKy4av90AEHh+AIdC2VEAutHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247978; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CKvapOYaUPsH2+8DKIbmLFaJiDGN1JuOSLBUKN32EsI=; b=nksenEkdRdbPSWXtmPwPhW7PTg5qti9ouwuBv8pVi3ALnwKXukuUrzcaYADP7u14UoZ8GU GJELtFf4YlZ3bnDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov , Ashok Raj Subject: [patch V4 03/30] x86/microcode/intel: Rip out mixed stepping support for Intel CPUs References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:38 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:00 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778665942719609996 X-GMAIL-MSGID: 1778665942719609996 From: Ashok Raj Mixed steppings aren't supported on Intel CPUs. Only one patch is required for the entire system. The caching of micro code blobs which match the family and model is therefore pointless and in fact it is disfunctional as CPU hotplug updates use only a single microcode blob, i.e. the one where *intel_ucode_patch points to. Remove the microcode cache and make it an AMD local feature. [ tglx: Save only at the end. Otherwise random microcode ends up in the pointer for early loading ] Originally-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- V2: Fix the bogus condition - Borislav --- arch/x86/kernel/cpu/microcode/amd.c | 10 ++ arch/x86/kernel/cpu/microcode/core.c | 2 arch/x86/kernel/cpu/microcode/intel.c | 133 +++++-------------------------- arch/x86/kernel/cpu/microcode/internal.h | 10 -- 4 files changed, 35 insertions(+), 120 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -37,6 +37,16 @@ #include "internal.h" +struct ucode_patch { + struct list_head plist; + void *data; + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +static LIST_HEAD(microcode_cache); + #define UCODE_MAGIC 0x00414d44 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 #define UCODE_UCODE_TYPE 0x00000001 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,8 +46,6 @@ static bool dis_ucode_ldr = true; bool initrd_gone; -LIST_HEAD(microcode_cache); - /* * Synchronization. * --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,10 +33,10 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch; +static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core; +static int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -253,74 +253,19 @@ static int has_newer_microcode(void *mc, return intel_find_matching_signature(mc, csig, cpf); } -static struct ucode_patch *memdup_patch(void *data, unsigned int size) +static void save_microcode_patch(void *data, unsigned int size) { - struct ucode_patch *p; + struct microcode_header_intel *p; - p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL); - if (!p) - return NULL; - - p->data = kmemdup(data, size, GFP_KERNEL); - if (!p->data) { - kfree(p); - return NULL; - } - - return p; -} - -static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigned int size) -{ - struct microcode_header_intel *mc_hdr, *mc_saved_hdr; - struct ucode_patch *iter, *tmp, *p = NULL; - bool prev_found = false; - unsigned int sig, pf; - - mc_hdr = (struct microcode_header_intel *)data; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - mc_saved_hdr = (struct microcode_header_intel *)iter->data; - sig = mc_saved_hdr->sig; - pf = mc_saved_hdr->pf; - - if (intel_find_matching_signature(data, sig, pf)) { - prev_found = true; - - if (mc_hdr->rev <= mc_saved_hdr->rev) - continue; - - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer %p\n", data); - else { - list_replace(&iter->plist, &p->plist); - kfree(iter->data); - kfree(iter); - } - } - } - - /* - * There weren't any previous patches found in the list cache; save the - * newly found. - */ - if (!prev_found) { - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer for %p\n", data); - else - list_add_tail(&p->plist, µcode_cache); - } + kfree(intel_ucode_patch); + intel_ucode_patch = NULL; + p = kmemdup(data, size, GFP_KERNEL); if (!p) return; - if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) - return; - /* Save for early loading */ - intel_ucode_patch = p->data; + intel_ucode_patch = (struct microcode_intel *)p; } /* @@ -332,6 +277,7 @@ scan_microcode(void *data, size_t size, { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; + u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; while (size) { @@ -341,8 +287,7 @@ scan_microcode(void *data, size_t size, mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); - if (!mc_size || - mc_size > size || + if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; @@ -354,31 +299,16 @@ scan_microcode(void *data, size_t size, continue; } - if (save) { - save_microcode_patch(uci, data, mc_size); + /* BSP scan: Check whether there is newer microcode */ + if (!save && cur_rev >= mc_header->rev) goto next; - } - - if (!patch) { - if (!has_newer_microcode(data, - uci->cpu_sig.sig, - uci->cpu_sig.pf, - uci->cpu_sig.rev)) - goto next; - - } else { - struct microcode_header_intel *phdr = &patch->hdr; - - if (!has_newer_microcode(data, - phdr->sig, - phdr->pf, - phdr->rev)) - goto next; - } + /* Save scan: Check whether there is newer or matching microcode */ + if (save && cur_rev != mc_header->rev) + goto next; - /* We have a newer patch, save it. */ patch = data; + cur_rev = mc_header->rev; next: data += mc_size; @@ -387,6 +317,9 @@ scan_microcode(void *data, size_t size, if (size) return NULL; + if (save && patch) + save_microcode_patch(patch, mc_size); + return patch; } @@ -528,26 +461,10 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci); } -static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) +/* Accessor for microcode pointer */ +static struct microcode_intel *ucode_get_patch(void) { - struct microcode_header_intel *phdr; - struct ucode_patch *iter, *tmp; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - - phdr = (struct microcode_header_intel *)iter->data; - - if (phdr->rev <= uci->cpu_sig.rev) - continue; - - if (!intel_find_matching_signature(phdr, - uci->cpu_sig.sig, - uci->cpu_sig.pf)) - continue; - - return iter->data; - } - return NULL; + return intel_ucode_patch; } void reload_ucode_intel(void) @@ -557,7 +474,7 @@ void reload_ucode_intel(void) intel_cpu_collect_info(&uci); - p = find_patch(&uci); + p = ucode_get_patch(); if (!p) return; @@ -601,7 +518,7 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; /* Look for a newer patch in our cache: */ - mc = find_patch(uci); + mc = ucode_get_patch(); if (!mc) { mc = uci->mc; if (!mc) @@ -730,7 +647,7 @@ static enum ucode_state generic_load_mic uci->mc = (struct microcode_intel *)new_mc; /* Save for CPU hotplug */ - save_microcode_patch(uci, new_mc, new_mc_size); + save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, new_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -8,16 +8,6 @@ #include #include -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct device; enum ucode_state { From patchwork Mon Oct 2 11:59:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147504 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1714033vqb; Mon, 2 Oct 2023 15:01:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHC3UINk4a+qEQUskYZpeS2k84ENSq9DEwHQ5gxZv3qPnmQ4yvadiWYviJTzxBSiDn6g1H5 X-Received: by 2002:a67:fa52:0:b0:452:e1f9:584c with SMTP id j18-20020a67fa52000000b00452e1f9584cmr11401383vsq.29.1696284081628; Mon, 02 Oct 2023 15:01:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284081; cv=none; d=google.com; s=arc-20160816; b=VlNLvJr3xDukJH+bar/oze4K3GRtwhnoPCOO0WDT1gY59Uc/8l1KyL+XUfJbiBYs6j SwB9sG8wtU9fA2zHGWm1jheYgcxOZvfJnjNVS4NmG/68pH1ZP3+Lar8u/IUtuf+Upscz YVIWA95UAgBgBec64QD1DN13WVy1behueICAVEdXQGFjeudDC+99eSbBJ1JTrexJYnHe oBw9zkdFuyYpv3W5aYNly9PAFTCUcQg2J3MVhFmJBrhhH3T7ixCfNZsTq25uT4gNojIZ QEdo4THZqFtjKdZwzsTxu42lKE/Rvz+oCYf0WGbH8BHHuTX/A2u8LGHOUpTZ2iHpZle4 wOXA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=L/ZIAb+b7ujT/LgRBtZ/7/iCkZfP4iPRPUCMdmlZuxA=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=Us0lgBO4aB5nIoDIXhPH/DPOuu0m6bCtMroFQnbfKm9nouP8wGig1pUMviOD3ESCn2 lS/ctY1M8PI5FzEGsjwxGx32fYEGOZ1xJ72T8/aRHSTcbrdK1Cj1CsdB9s9oFotGNmCf ZcynebvJi6aJejedONf9uz3lnVjd7k8iYhQYHJO54lukVYUwF3AN8BvYHNi9D30D0LXo NQANtMlyVFjuJoUSQxhVigJ+00QWYsHWDyGxhcAUKywoRJurNnllqVRRsCIOqFRzh+XA paWt6BzNlkh2A8KDz+zUqJku/+QSr/IgwBpXPGT/Nj+HnYR5AixokraPAcqrdEBkRXH2 WX7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=GotJcce1; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id a63-20020a639042000000b00577f65baa3dsi27004544pge.849.2023.10.02.15.01.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:01:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=GotJcce1; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 6724981067BE; Mon, 2 Oct 2023 05:00:07 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236876AbjJBL7y (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236840AbjJBL7n (ORCPT ); Mon, 2 Oct 2023 07:59:43 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1725D7 for ; Mon, 2 Oct 2023 04:59:40 -0700 (PDT) Message-ID: <20231002115902.271940980@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247979; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L/ZIAb+b7ujT/LgRBtZ/7/iCkZfP4iPRPUCMdmlZuxA=; b=GotJcce1G60jQoZRugDQiP6Yfc6kO/d2NZ1uYgSeFKssZQ+5krHSjiB3qNEMl9Of4Avuae gaUM7jSzU6177+3ziaryBYZ5jAfosSPOZixPKzV24PUqhvWjpOuIgHRMQ5ojKOToq0RX2z G+GX/drSIwQD9dEcBxbh5MnhdgQj/19QOX36ms0+TYAyAbbdPVX17xKvzMmKlDYcGtWnhU 82Mg4ihHKzcvpuwHMllO8uk3d+bl21slBL+H1f5h2eD6Rac+bF92Pxs+9uCGxdeDTEG/si izskW2ykRysH2fP2bDKO/rTFLcOlO/7LfZYhllCJ7dkX5k4sJuPATzfZlBmwPg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247979; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L/ZIAb+b7ujT/LgRBtZ/7/iCkZfP4iPRPUCMdmlZuxA=; b=ElxZ3wMlEzmtUAPwRQwyP4xuXPrZYckwj6+uQHI200WeRt4b2pNUFxMFICPqUEU7oHuF8V GDoYH4BkCGWUGlBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 04/30] x86/microcode/intel: Simplify scan_microcode() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:39 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778682777060467805 X-GMAIL-MSGID: 1778682777060467805 Make it readable and comprehensible. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -268,22 +268,16 @@ static void save_microcode_patch(void *d intel_ucode_patch = (struct microcode_intel *)p; } -/* - * Get microcode matching with BSP's model. Only CPUs with the same model as - * BSP can stay in the platform. - */ -static struct microcode_intel * -scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) +/* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ +static struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; - while (size) { - if (size < sizeof(struct microcode_header_intel)) - break; - + for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); @@ -291,27 +285,19 @@ scan_microcode(void *data, size_t size, intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - size -= mc_size; - - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, - uci->cpu_sig.pf)) { - data += mc_size; + if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - } /* BSP scan: Check whether there is newer microcode */ if (!save && cur_rev >= mc_header->rev) - goto next; + continue; /* Save scan: Check whether there is newer or matching microcode */ if (save && cur_rev != mc_header->rev) - goto next; + continue; patch = data; cur_rev = mc_header->rev; - -next: - data += mc_size; } if (size) From patchwork Mon Oct 2 11:59:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147509 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1716686vqb; Mon, 2 Oct 2023 15:05:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHEqBAe9VXJC+MbkglAo9tXZ2KY+2dZiGyLUTlzr21MXNIFLMOpGxl1tvetTNWEdoP3tDe X-Received: by 2002:a25:6f82:0:b0:d7f:3e2:dd99 with SMTP id k124-20020a256f82000000b00d7f03e2dd99mr11745215ybc.0.1696284352872; Mon, 02 Oct 2023 15:05:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284352; cv=none; d=google.com; s=arc-20160816; b=hElnCURQ8a8FdQNIJW/G4jxsqWp4aFxUzz2GL70gANZv22h77LxEJIRMxEQmwfgx0+ b88LijA68tKKlLAX6Zf81Jb0MMsFLxbz5GejgzcxsWLGFT08JtAQeCt29h+BYyEbK0fi L1gC2r5rqaLb7Wvz+i093J3DlqFF2LAiETz7DdDDgNpoTVCNqnTf+wuAqCvGxWMbDXny kFoMD5qqGSUJdWVRl3bvBleRjgKYSBGCv0NesfGAbCECuWNzsKU6kLU/448RM4v4jmIW HYv5bPjMjMeRWU3/eP+HLZEF8I4HhgiQKP6ZEUQhZKVOlKvENBOyAXk1JsMvgN6IxdST 0dVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=CN2QFAx6JB0LSmuYjwWY54K/mbyCNDPxFixGJ6298Ak=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=Dt8n5QYmGYdfIDIOWLtWGg2rbbk+X3h592xmkedM/uenP89CnzheZ1kqIT0ferjVYR peGYagTHGL2LdxsNzUm8+RUC+epOV0r28vYrOfC/sNy5HoFx996UZSr6DmMgx24j5/BR 1iggO68l6PW9tcp5/PpNo1AkgfOoH0/ikZ8Q0Hg/76vISyBFAFI2vff+QpKHYh4kkSpX a9fu/4167gNlVAXPIUya8p6QL/s1L7UTp7bcjlJaJeX8FPxVh9P0TJlqPfu7tCMD7Roq RV1mWU0NZBUijmQwkWEvw3EPUR6KgiAYyA65birDwYvRLSnav7jD26fvtSIgelYykKlX dfAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=M6WFIiYN; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id v1-20020a654601000000b0056a290addadsi28819760pgq.787.2023.10.02.15.05.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:05:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=M6WFIiYN; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 5F4F4810681F; Mon, 2 Oct 2023 05:00:01 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236870AbjJBL7w (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236801AbjJBL7p (ORCPT ); Mon, 2 Oct 2023 07:59:45 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2640594 for ; Mon, 2 Oct 2023 04:59:42 -0700 (PDT) Message-ID: <20231002115902.330295409@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CN2QFAx6JB0LSmuYjwWY54K/mbyCNDPxFixGJ6298Ak=; b=M6WFIiYNitNpNeVRWR4e9icGfTxfl7X7PJ2jb7IanJi0cImW7vVsz3SuuYrbRHb7j5VFEj 1oA6HUsSlSo8WHVRIrOZ4fJ8Zz1iGMqvn3lsoXBIaNBEn2gpPNwsbIwIS3sQbKnHbZzwuw LEELb4A4pN5AhS4xMNXPDN+xJxRtHo7h/OplLi37advCZdNFTjLMsLyCdekSAwu8rs36pI KJqy9IfNNM+3eQ33KyHkXD2VDO/yyGtHouiaI/fZRc2Qxl/NePqLf6/QTgX5UVweJ34dqG M/5TCmklfPQMQdDIvvWP0mwfC7bq3JVeiWKbeTvQWouvcjXyBkYHiF15tkWkMw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247980; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CN2QFAx6JB0LSmuYjwWY54K/mbyCNDPxFixGJ6298Ak=; b=aX4n7L/Dl1IYk0IbL488R1dWdaCCNkUgifzHvj4/g5WfBv+2JAt1XyZ2fs7OHZat/5QN15 ElSAn0lduS5ezJBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 05/30] x86/microcode/intel: Simplify and rename generic_load_microcode() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:40 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778683061410403437 X-GMAIL-MSGID: 1778683061410403437 so it becomes less obfuscated and rename it because there is nothing generic about it. Signed-off-by: Thomas Gleixner --- V3: Rename to parse_microcode_blobs() - Borislav --- arch/x86/kernel/cpu/microcode/intel.c | 47 ++++++++++++---------------------- 1 file changed, 17 insertions(+), 30 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -240,19 +240,6 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) -{ - struct microcode_header_intel *mc_hdr = mc; - - if (mc_hdr->rev <= new_rev) - return 0; - - return intel_find_matching_signature(mc, csig, cpf); -} - static void save_microcode_patch(void *data, unsigned int size) { struct microcode_header_intel *p; @@ -561,14 +548,12 @@ static enum ucode_state apply_microcode_ return ret; } -static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) +static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; - enum ucode_state ret = UCODE_OK; - int new_rev = uci->cpu_sig.rev; + int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - unsigned int csig, cpf; while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; @@ -585,6 +570,7 @@ static enum ucode_state generic_load_mic pr_err("error! Bad data in microcode data file (totalsize too small)\n"); break; } + data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); @@ -607,16 +593,17 @@ static enum ucode_state generic_load_mic break; } - csig = uci->cpu_sig.sig; - cpf = uci->cpu_sig.pf; - if (has_newer_microcode(mc, csig, cpf, new_rev)) { - vfree(new_mc); - new_rev = mc_header.rev; - new_mc = mc; - new_mc_size = mc_size; - mc = NULL; /* trigger new vmalloc */ - ret = UCODE_NEW; - } + if (cur_rev >= mc_header.rev) + continue; + + if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + continue; + + vfree(new_mc); + cur_rev = mc_header.rev; + new_mc = mc; + new_mc_size = mc_size; + mc = NULL; } vfree(mc); @@ -636,9 +623,9 @@ static enum ucode_state generic_load_mic save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); + cpu, cur_rev, uci->cpu_sig.rev); - return ret; + return UCODE_NEW; } static bool is_blacklisted(unsigned int cpu) @@ -687,7 +674,7 @@ static enum ucode_state request_microcod kvec.iov_base = (void *)firmware->data; kvec.iov_len = firmware->size; iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size); - ret = generic_load_microcode(cpu, &iter); + ret = parse_microcode_blobs(cpu, &iter); release_firmware(firmware); From patchwork Mon Oct 2 11:59:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147396 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1578235vqb; Mon, 2 Oct 2023 10:26:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEpEAWuoHEyGJqyEoc8LuaHI8Lw8opfww59CdCFDv6BF/9/smPw5xQo4/dGciEKo5epdzmo X-Received: by 2002:a05:6808:1a13:b0:3a7:6213:6899 with SMTP id bk19-20020a0568081a1300b003a762136899mr15498613oib.24.1696267606510; Mon, 02 Oct 2023 10:26:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696267606; cv=none; d=google.com; s=arc-20160816; b=HCXQ0h5iDypSFGWpYzxtK3h1JBXCmqhYF2DEMcqK4oyTe3HwGlN7aGmsXf5iIivH3B kfXqmzexTD7qmrZukX922mSESea0FeZ6yB4/h90NfVwm9t6lon3VLdmMdUcfdptUjElB 9ea++JRzKtCudQR4cQcm1P0WJ12QoEDpx2pzBPYJ5OD2uGMO2ZSv3x8VQK0BDvCAkFYc cMOcGHQ2JYedppXqVxvGt6iI24UdfaNLLT1YiI67iEsDRTf795eGIyabWEG1ra05lknh DeJBztwVmasi/g0R7inZYJPIlHgLCk2ax0NugnqgFDTmRiUTILSj3r0QakSWKtV/HzbC Zehw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=CL8Mt93Hk88+MM0PiUaqDK+zdUWvTsAJgc1nd1BOMcc=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=s6esM0hrDaXzFnaPAy1DFIa/8PeXgcJq1AKS1nkW5qDQXDlzaSgJ3t2GRiKet2/Gpt mexb0Qy4Tx+34RtKI4rx71UxaBGL8Y++HZbah4KpDyctM3UR9wbv/d6+nTNojtRvG/6A +D8Qka7h8bia3YSpz1ZRNVexM6AiIvxE6IuVWVmHUE5xds7b8YdYBT1VKveapDA0JCbg fScA/8/nVqYa8Ty+c5JRD/8YmT2fpP1bbPe4up8GbYNARlG3WfU/KsHaU5+d5XdvYI/N k4YBSWF9dF0WYklgOtrtuP1/kOn+3MdOLZZXpC9QAmda+sCEtWI/qxM5vnvrfv3mePPt vLig== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1ZR90Hun; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="e1fd2q/a"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id y24-20020a17090aa41800b0027744a9de69si7851674pjp.126.2023.10.02.10.26.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 10:26:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1ZR90Hun; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b="e1fd2q/a"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id CDE2C8076D3D; Mon, 2 Oct 2023 05:00:33 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236881AbjJBL75 (ORCPT + 18 others); Mon, 2 Oct 2023 07:59:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236857AbjJBL7q (ORCPT ); Mon, 2 Oct 2023 07:59:46 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B3B2DD for ; Mon, 2 Oct 2023 04:59:43 -0700 (PDT) Message-ID: <20231002115902.389400871@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CL8Mt93Hk88+MM0PiUaqDK+zdUWvTsAJgc1nd1BOMcc=; b=1ZR90HunL9z5eJ6ksvZnLxRCkDP6aHy7OvvfxSMM9OVjgGH0+MEbvcxfJ3fmeIwrow8ofh tWnQz+KToKu4IXT3FLnOJOTnj/o4snGqbAeeCcE02mxt6HxRV5qFqI1ylt0/6nzmpgTCLf e9NII/4aI0iw1sFRiz89MgNP+njjYSarHXxcZQZK0Cvvig4ghVj4aoa6SQwCghEKMgSwYm WWJ1TZTeXZyZt1zOAY/CnyJMCZXJ+65Xn5uYyfwqfkl2N3H+xdSUxb5ZmaK8LEPRGNgLbX DcJ/HFEJur/QqSjHaZNPfD/nwp+WrEq5tyfiaE8uRnk4BNRjI8X5hLRImYGb3A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247982; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=CL8Mt93Hk88+MM0PiUaqDK+zdUWvTsAJgc1nd1BOMcc=; b=e1fd2q/aWoqUYauDcuakBc68T6pPCnXcRcOBJ0Ol6ItZqqtV/IwBxs4E10STFLIgeloruX Y4zcjwAQo1fuwVCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 06/30] x86/microcode/intel: Cleanup code further References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:41 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778665501426411272 X-GMAIL-MSGID: 1778665501426411272 From: Thomas Gleixner Sanitize the microcode scan loop, fixup printks and move the loading function for builtin microcode next to the place where it is used and mark it __init. Signed-off-by: Thomas Gleixner --- V2: Fix changelog - Nikolay --- arch/x86/kernel/cpu/microcode/intel.c | 76 ++++++++++++++-------------------- 1 file changed, 32 insertions(+), 44 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -36,7 +36,7 @@ static const char ucode_path[] = "kernel static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core __ro_after_init; +static unsigned int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -296,29 +296,6 @@ static struct microcode_intel *scan_micr return patch; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) -{ - unsigned int eax = 1, ebx, ecx = 0, edx; - struct firmware fw; - char name[30]; - - if (IS_ENABLED(CONFIG_X86_32)) - return false; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - sprintf(name, "intel-ucode/%02x-%02x-%02x", - x86_family(eax), x86_model(eax), x86_stepping(eax)); - - if (firmware_request_builtin(&fw, name)) { - cp->size = fw.size; - cp->data = (void *)fw.data; - return true; - } - - return false; -} - static int apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; @@ -362,6 +339,28 @@ static int apply_microcode_early(struct return 0; } +static bool load_builtin_intel_microcode(struct cpio_data *cp) +{ + unsigned int eax = 1, ebx, ecx = 0, edx; + struct firmware fw; + char name[30]; + + if (IS_ENABLED(CONFIG_X86_32)) + return false; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + sprintf(name, "intel-ucode/%02x-%02x-%02x", + x86_family(eax), x86_model(eax), x86_stepping(eax)); + + if (firmware_request_builtin(&fw, name)) { + cp->size = fw.size; + cp->data = (void *)fw.data; + return true; + } + return false; +} + int __init save_microcode_in_initrd_intel(void) { struct ucode_cpu_info uci; @@ -434,25 +433,16 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci); } -/* Accessor for microcode pointer */ -static struct microcode_intel *ucode_get_patch(void) -{ - return intel_ucode_patch; -} - void reload_ucode_intel(void) { - struct microcode_intel *p; struct ucode_cpu_info uci; intel_cpu_collect_info(&uci); - p = ucode_get_patch(); - if (!p) + uci.mc = intel_ucode_patch; + if (!uci.mc) return; - uci.mc = p; - apply_microcode_early(&uci); } @@ -490,8 +480,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - /* Look for a newer patch in our cache: */ - mc = ucode_get_patch(); + mc = intel_ucode_patch; if (!mc) { mc = uci->mc; if (!mc) @@ -682,18 +671,17 @@ static enum ucode_state request_microcod } static struct microcode_ops microcode_intel_ops = { - .request_microcode_fw = request_microcode_fw, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .request_microcode_fw = request_microcode_fw, + .collect_cpu_info = collect_cpu_info, + .apply_microcode = apply_microcode_intel, }; -static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) +static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) { u64 llc_size = c->x86_cache_size * 1024ULL; do_div(llc_size, c->x86_max_cores); - - return (int)llc_size; + llc_size_per_core = (unsigned int)llc_size; } struct microcode_ops * __init init_intel_microcode(void) @@ -706,7 +694,7 @@ struct microcode_ops * __init init_intel return NULL; } - llc_size_per_core = calc_llc_size_per_core(c); + calc_llc_size_per_core(c); return µcode_intel_ops; } From patchwork Mon Oct 2 11:59:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147510 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1716694vqb; Mon, 2 Oct 2023 15:05:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE0E1b42ZUGcL/qVlf39OfJ6q59Wd4IysVkDTX508uIBE56snF0qlpWrLeV6XmhHbiFcnPK X-Received: by 2002:a05:6870:b292:b0:1e0:eb36:a7ed with SMTP id c18-20020a056870b29200b001e0eb36a7edmr14025530oao.29.1696284353337; Mon, 02 Oct 2023 15:05:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284353; cv=none; d=google.com; s=arc-20160816; b=tmNwVaXU42d+6HDX2AQOJ5X2IHi5a5OA6Z5HoinFAtbCQWpfg+wstQODLmZQN1YdcM 9A+MnwIzhLNLpm3NL/FKL/iX0h29EWb5as2vz8IOFQizglQxnCq94vaa5Nhlk5shOMIH 3a0xgomwoI6jMLIoKuZsj1/EgIC22LkCNSOeRGOzRrj6or9Hf8DOHoJpO7AjKuUs4rz1 8ZobYrei0uOvHO4BfuRxeXE6L4dZnYUSzvMqz+PKBR4X7BSzpebFnh7AxmFMy0KqwMVO YCild1YU1XPBvtoAm48yY+F85yGlcDTzADiuBhytHOj6/eYVKYC+WOVAc9SirplWfg0m gijQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=RLEf2izi7qSnm1BxX7UWF4x2xYIklwb4ujkR1N0wQTU=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=eflpvlo9rUjj4dJnY7tDcT/V3j9T2MupQ3uBT2CdLx/XBlMVO8ttgSEX7JK/jwDvzh LE154zUKqLUCJ5sCtNcNhgjHqo4vAXU15c0eupSiRd97As7eI8fF01PDDefDizpcYX5c zs9toUfVhITMqlIDWRUCdl3WNwM5/ouiAcz6OVcn7mfSf+N6X/iRa+5494AG5jENHVcd /TWUAqfSNmjW/KHOGFLjq04ni/Y9MlXCi6e4vnGryKcMaCwMrYZcGqUeNPoUVvLpyLFZ nig0wNyaXik6qhrzizeJyLAtL0JtDQXBKp0LWvAQ+7K5egPOdBIDuzGg8LUca0xvp2MI GF5w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=v1xkMnsS; dkim=neutral (no key) header.i=@linutronix.de header.b=Y8unz4gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id d19-20020a637353000000b00578aedd8e8bsi28180027pgn.716.2023.10.02.15.05.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:05:53 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=v1xkMnsS; dkim=neutral (no key) header.i=@linutronix.de header.b=Y8unz4gk; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 54CEE810686C; Mon, 2 Oct 2023 05:00:09 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236847AbjJBMAC (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236849AbjJBL7s (ORCPT ); Mon, 2 Oct 2023 07:59:48 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C365BE0 for ; Mon, 2 Oct 2023 04:59:44 -0700 (PDT) Message-ID: <20231002115902.447556023@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RLEf2izi7qSnm1BxX7UWF4x2xYIklwb4ujkR1N0wQTU=; b=v1xkMnsSEwwPgS3k6NWJduzz1o/Uw4YZcqWAU8AhLLKtJwBdb44iviN2d0MfFrPbjOImz4 G7oBiQurMS0vkek2B6/5tOO8cJ1ncGXtmWKIiYEBoXQaYj2k3HXHwMqqbCoBaIL3j/k3fz VFbPlpDUQNXsiqT0ce7pMKaCcMbrM8/NgCe/9s3ompNpOty4fOTKeyyniLg2szWwevRJux Kg7yZH4OcA8HflX1Zh2phpAwW+hqVvxQ3GR/9Kc6eQt41WMnW1XFJbZ+Ey73d5NPP3Yd6R 2SZ/w+JKcqTfCCX/Y3C3SmMSLgUUZE2qenwY0dQO6Glx7cF7BWOmqfW9aiuPBg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247983; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=RLEf2izi7qSnm1BxX7UWF4x2xYIklwb4ujkR1N0wQTU=; b=Y8unz4gkvLb5gTliSMgPGHmfJ73eRtSBvSInvuDRTY1wJu8smtB65Ko1w+owgaLbzrDsnw HkNqCEZVM8KQJdCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 07/30] x86/microcode/intel: Simplify early loading References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:43 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778683062195531885 X-GMAIL-MSGID: 1778683062195531885 From: Thomas Gleixner The early loading code is overly complicated: - It scans the builtin/initrd for microcode not only on the BSP, but also on all APs during early boot and then later in the boot process it scans again to duplicate and save the microcode before initrd goes away. That's a pointless exercise because this can be simply done before bringing up the APs when the memory allocator is up and running. - Saving the microcode from within the scan loop is completely non-obvious and a left over of the microcode cache. This can be done at the call site now which makes it obvious. Rework the code so that only the BSP scans the builtin/initrd microcode once during early boot and save it away in an early initcall for later use. Signed-off-by: Thomas Gleixner --- V4: Drop CPIO references - Borislav --- arch/x86/kernel/cpu/microcode/core.c | 4 arch/x86/kernel/cpu/microcode/intel.c | 150 +++++++++++++------------------ arch/x86/kernel/cpu/microcode/internal.h | 2 3 files changed, 65 insertions(+), 91 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -186,10 +186,6 @@ static int __init save_microcode_in_init int ret = -EINVAL; switch (c->x86_vendor) { - case X86_VENDOR_INTEL: - if (c->x86 >= 6) - ret = save_microcode_in_initrd_intel(); - break; case X86_VENDOR_AMD: if (c->x86 >= 0x10) ret = save_microcode_in_initrd_amd(cpuid_eax(1)); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,7 +33,7 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch __read_mostly; +static struct microcode_intel *ucode_patch_va __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -240,24 +240,29 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -static void save_microcode_patch(void *data, unsigned int size) +static void update_ucode_pointer(struct microcode_intel *mc) { - struct microcode_header_intel *p; + kfree(ucode_patch_va); - kfree(intel_ucode_patch); - intel_ucode_patch = NULL; + /* + * Save the virtual address for early loading and for eventual free + * on late loading. + */ + ucode_patch_va = mc; +} - p = kmemdup(data, size, GFP_KERNEL); - if (!p) - return; +static void save_microcode_patch(struct microcode_intel *patch) +{ + struct microcode_intel *mc; - /* Save for early loading */ - intel_ucode_patch = (struct microcode_intel *)p; + mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + if (mc) + update_ucode_pointer(mc); } -/* Scan CPIO for microcode matching the boot CPUs family, model, stepping */ -static struct microcode_intel *scan_microcode(void *data, size_t size, - struct ucode_cpu_info *uci, bool save) +/* Scan blob for microcode matching the boot CPUs family, model, stepping */ +static __init struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; @@ -275,35 +280,25 @@ static struct microcode_intel *scan_micr if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - /* BSP scan: Check whether there is newer microcode */ - if (!save && cur_rev >= mc_header->rev) - continue; - - /* Save scan: Check whether there is newer or matching microcode */ - if (save && cur_rev != mc_header->rev) + /* Check whether there is newer microcode */ + if (cur_rev >= mc_header->rev) continue; patch = data; cur_rev = mc_header->rev; } - if (size) - return NULL; - - if (save && patch) - save_microcode_patch(patch, mc_size); - - return patch; + return size ? NULL : patch; } -static int apply_microcode_early(struct ucode_cpu_info *uci) +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; u32 rev, old_rev, date; mc = uci->mc; if (!mc) - return 0; + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -329,17 +324,17 @@ static int apply_microcode_early(struct rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + return UCODE_ERROR; uci->cpu_sig.rev = rev; date = mc->hdr.date; pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); - return 0; + return UCODE_UPDATED; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) +static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; struct firmware fw; @@ -361,89 +356,75 @@ static bool load_builtin_intel_microcode return false; } -int __init save_microcode_in_initrd_intel(void) +static __init struct microcode_intel *get_microcode_blob(struct ucode_cpu_info *uci) { - struct ucode_cpu_info uci; struct cpio_data cp; - /* - * initrd is going away, clear patch ptr. We will scan the microcode one - * last time before jettisoning and save a patch, if found. Then we will - * update that pointer too, with a stable patch address to use when - * resuming the cores. - */ - intel_ucode_patch = NULL; - if (!load_builtin_intel_microcode(&cp)) cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) - return 0; + return NULL; - intel_cpu_collect_info(&uci); + intel_cpu_collect_info(uci); - scan_microcode(cp.data, cp.size, &uci, true); - return 0; + return scan_microcode(cp.data, cp.size, uci); } +static struct microcode_intel *ucode_early_pa __initdata; + /* - * @res_patch, output: a pointer to the patch we found. + * Invoked from an early init call to save the microcode blob which was + * selected during early boot when mm was not usable. The microcode must be + * saved because initrd is going away. It's an early init call so the APs + * just can use the pointer and do not have to scan initrd/builtin firmware + * again. */ -static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) +static int __init save_builtin_microcode(void) { - struct cpio_data cp; - - /* try built-in microcode first */ - if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path); - - if (!(cp.data && cp.size)) - return NULL; + struct microcode_intel *mc; - intel_cpu_collect_info(uci); + if (!ucode_early_pa) + return 0; - return scan_microcode(cp.data, cp.size, uci, false); + mc = __va((void *)ucode_early_pa); + save_microcode_patch(mc); + return 0; } +early_initcall(save_builtin_microcode); +/* Load microcode on BSP from initrd or builtin blobs */ void __init load_ucode_intel_bsp(void) { - struct microcode_intel *patch; struct ucode_cpu_info uci; - patch = __load_ucode_intel(&uci); - if (!patch) + uci.mc = get_microcode_blob(&uci); + if (!uci.mc) return; - uci.mc = patch; + if (apply_microcode_early(&uci) != UCODE_UPDATED) + return; - apply_microcode_early(&uci); + /* Store the physical address as KASLR happens after this. */ + ucode_early_pa = (struct microcode_intel *)__pa_nodebug(uci.mc); } void load_ucode_intel_ap(void) { struct ucode_cpu_info uci; - if (!intel_ucode_patch) { - intel_ucode_patch = __load_ucode_intel(&uci); - if (!intel_ucode_patch) - return; - } - - uci.mc = intel_ucode_patch; - apply_microcode_early(&uci); + uci.mc = ucode_patch_va; + if (uci.mc) + apply_microcode_early(&uci); } +/* Reload microcode on resume */ void reload_ucode_intel(void) { - struct ucode_cpu_info uci; - - intel_cpu_collect_info(&uci); + struct ucode_cpu_info uci = { .mc = ucode_patch_va, }; - uci.mc = intel_ucode_patch; - if (!uci.mc) - return; - - apply_microcode_early(&uci); + if (uci.mc) + apply_microcode_early(&uci); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) @@ -480,7 +461,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = intel_ucode_patch; + mc = ucode_patch_va; if (!mc) { mc = uci->mc; if (!mc) @@ -540,8 +521,8 @@ static enum ucode_state apply_microcode_ static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - unsigned int curr_mc_size = 0, new_mc_size = 0; int cur_rev = uci->cpu_sig.rev; + unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; while (iov_iter_count(iter)) { @@ -591,7 +572,6 @@ static enum ucode_state parse_microcode_ vfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; - new_mc_size = mc_size; mc = NULL; } @@ -605,11 +585,11 @@ static enum ucode_state parse_microcode_ if (!new_mc) return UCODE_NFOUND; - vfree(uci->mc); - uci->mc = (struct microcode_intel *)new_mc; - /* Save for CPU hotplug */ - save_microcode_patch(new_mc, new_mc_size); + save_microcode_patch((struct microcode_intel *)new_mc); + uci->mc = ucode_patch_va; + + vfree(new_mc); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, cur_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -107,13 +107,11 @@ static inline void exit_amd_microcode(vo #ifdef CONFIG_CPU_SUP_INTEL void load_ucode_intel_bsp(void); void load_ucode_intel_ap(void); -int save_microcode_in_initrd_intel(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(void) { } static inline void load_ucode_intel_ap(void) { } -static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } static inline void reload_ucode_intel(void) { } static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } #endif /* !CONFIG_CPU_SUP_INTEL */ From patchwork Mon Oct 2 11:59:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147257 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1380492vqb; Mon, 2 Oct 2023 05:12:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFTEXXxfyVSoPbIJJ0qKG+C4fIlUTmkodQgdV3Zo4KV85+an3+Cx929B1RSjMm+QCftroOj X-Received: by 2002:a17:902:e5cd:b0:1c4:16f7:d95b with SMTP id u13-20020a170902e5cd00b001c416f7d95bmr10690884plf.63.1696248743024; Mon, 02 Oct 2023 05:12:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696248743; cv=none; d=google.com; s=arc-20160816; b=bCJ/aFZIslN2fFgZONINDRAjfjE4VJMbzBtPwHufFQ0T5sVokm3VdOC3xV5Y9T/lhY OFMn8OZJt/jQBT2ZZVKHJA4YEYes2j5HOchVG37sUnza5u6UhIQ0B6Ey70nclJclRPL2 s9+pGpq94itYVeNdei3IbJZWkguGoEg8c5w+gbQqCRUGgzZXzgYwyl9RtNO+MM+AQthB RM+EyPrMwem04nGKBraSYX9wF/649o5afSLQogN+oki5oyJQiYhsD78duJ6JuIlTCtnN Gdc5HjtfpgWf507yc8T/ubhIPycmX9+pAnbz4U+a2ZIv5LMvUJgdh04pQTuKFtAGi5mv BJdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=hWimmhBWR+BZVXFP5DyDAkJLyIyydcdqq/jEuDzsXXE=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=lwdQirsZtlTq8xPglwttfgTC9PULHA5gAI1AmkIipmbRZxrNFE8xqmreTIw5XQ+h1n BwQcGnfLkclFyhzO1ZpaUjijLFSOYzPgBRXQZXKLr4ERmVrn/LtY2G5gsT+3Ajqj6Fmr DUKeovLA1oN8KNwaqoNL3HR8BWFLzYFAEs4u7X20RvkIbFNPriWlII9TbhJEiglhibcR ADJiTrJH98vtR0DWj645WnlYP2RpAaIl01o//t1yFLPJXeyKLqIOYAof95c17s/VbVpW yufj8ksVUgtddqjO2SE5Hm5TRx0nd2+oeX8CJ7tDkG2GGi5IjaMncOnM6eDVBJOU63FA 6nAg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=mROG4cEu; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=5JmYzRjZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from agentk.vger.email (agentk.vger.email. [23.128.96.32]) by mx.google.com with ESMTPS id w3-20020a170902e88300b001c574110eecsi3017726plg.341.2023.10.02.05.12.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 05:12:23 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) client-ip=23.128.96.32; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=mROG4cEu; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=5JmYzRjZ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 3F85680842DB; Mon, 2 Oct 2023 05:00:26 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236899AbjJBMAI (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236862AbjJBL7t (ORCPT ); Mon, 2 Oct 2023 07:59:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C8E3CC6 for ; Mon, 2 Oct 2023 04:59:45 -0700 (PDT) Message-ID: <20231002115902.505491309@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hWimmhBWR+BZVXFP5DyDAkJLyIyydcdqq/jEuDzsXXE=; b=mROG4cEuDKMkiq1Q7i9PgDp/heruLruWDUKLvCDXvPCA/gNJxEJUlqW4DWDY5hIGVMydzb W/sP576bJccluy6YwVGeTUvEDJRdeQ4iP/c1DunlRlTjzjQ12xDSEcmp+FXozX4e4K4wrR 7XVBZ3VpYAeSICZBqLTs9Xmo/I0G5SlQC4Z2GjRfasEvs/1X+mvs6tigk9wi0HlKhlXLVb jPCPtb15843sr7g33HOBklvNcVxcdFeJe7OBp/iHd2UReLM0Mth62mvQDaSH9SBd7ImU3O RKJf6KvO2LUPvMImx0AKyV5cUsqytvhdOu8UO7LqaWeH7ArysD2SjcXSvmedNQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247984; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=hWimmhBWR+BZVXFP5DyDAkJLyIyydcdqq/jEuDzsXXE=; b=5JmYzRjZ9Uk8G1KZH5Im+FCLK4DDglUFfk8X/Izt/a2RagOGUVUCH4we7nalt14DEq9lkD kiWxrg4zyQ4R8yBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 08/30] x86/microcode/intel: Save the microcode only after a successful late-load References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:44 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778645722338788849 X-GMAIL-MSGID: 1778645722338788849 From: Thomas Gleixner There are situations where the late microcode is loaded into memory, but is not applied: 1) The rendezvouz fails 2) The microcode is rejected by the CPUs If any of this happens then the pointer which was updated at firmware load time is stale and subsequent CPU hotplug operations either fail to update or create inconsistent microcode state. Save the loaded microcode in a separate pointer from with the late load is attempted and when successful, update the hotplug pointer accordingly via a new microcode_ops callback. Remove the pointless fallback in the loader to a microcode pointer which is never populated. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 ++++ arch/x86/kernel/cpu/microcode/intel.c | 30 +++++++++++++++--------------- arch/x86/kernel/cpu/microcode/internal.h | 1 + 3 files changed, 20 insertions(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -400,6 +400,10 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + + if (microcode_ops->finalize_late_load) + microcode_ops->finalize_late_load(ret); + if (!ret) { pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -34,6 +34,7 @@ static const char ucode_path[] = "kernel /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; +static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -461,12 +462,9 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = ucode_patch_va; - if (!mc) { - mc = uci->mc; - if (!mc) - return UCODE_NFOUND; - } + mc = ucode_patch_late; + if (!mc) + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -585,15 +583,7 @@ static enum ucode_state parse_microcode_ if (!new_mc) return UCODE_NFOUND; - /* Save for CPU hotplug */ - save_microcode_patch((struct microcode_intel *)new_mc); - uci->mc = ucode_patch_va; - - vfree(new_mc); - - pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, cur_rev, uci->cpu_sig.rev); - + ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; } @@ -650,10 +640,20 @@ static enum ucode_state request_microcod return ret; } +static void finalize_late_load(int result) +{ + if (!result) + save_microcode_patch(ucode_patch_late); + + vfree(ucode_patch_late); + ucode_patch_late = NULL; +} + static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_intel, + .finalize_late_load = finalize_late_load, }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,6 +31,7 @@ struct microcode_ops { */ enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Mon Oct 2 11:59:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147347 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1515161vqb; Mon, 2 Oct 2023 08:47:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGzOLUM+1lNp6CYyBSkjekPsnAHpncTUPc/PfCPT7yUhL5whrnud5eff9FCVmEcMSKXg4Ry X-Received: by 2002:a05:6300:808c:b0:140:324c:124c with SMTP id ap12-20020a056300808c00b00140324c124cmr9233997pzc.62.1696261653382; Mon, 02 Oct 2023 08:47:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696261653; cv=none; d=google.com; s=arc-20160816; b=NXzInn2KFO/yEqr8KPSmFwlrDN9m+4KsH5F/q5OvTetKJ9DiXzYeQdKMWCCWa655U1 ux3so/0mXxlE0u7+KsZXPI2+5lwr6hA/rmfkF+ZwulqhrU2ydR9FhAWaUurKZqX+Suao +WgCXbv9ei4+quxfXYtbRqFGZZ17MrHx0d5YAJE4ucEFtPRK8pII5YigaXaIG+X+UCXc 1FfO8kmpnXhWyfLMquGAH86HYDJ5KUuSAEz34MUSNed3ClBiXGFHPpJAT6qSK1+8jchh W4+4lD7WdRsXuBHPnDUsEi7JiKrckzA/XcEB+60MNmrj7l/7zein+xWjbAk9PBBwXbbR OFDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=zPYr0Ydgl25/awrI3nekKS7noAl2zorfqWbbUsVIQD4=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=k0ZKkclD6Aekux5JRIX5qZ+aackysEjLGaKO/+tNoVYwEAwwKOmd5KjCY5g0lZhr8u 5CNmcF1ndDCn0CYQVeTA+/rrTV0IGsp+57rmzbLCzIEc4GJRrtvcyPnpy1iHlHtKwq1V BfpjGLKANkScEwVj+bTdOgL4TiO1wFQFcgthwWOIBFbqsGEODpuZYa+PhxnpL0snnq02 3dRzyD3lwxZqySL7V41NPUFq5iJu9o3n+EeaSc8DXTC+b+Ftl4IIZyGjajHaoKikp/pW BgusHRiIrBPPIbMzEGVgKkhukxT0+SnUlTkjFgdVF8NM2XokXnDfADfw1qxyXcFX2NgX p1Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=yn2ol6kB; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id x24-20020a056a000bd800b00690d42e3347si24934751pfu.157.2023.10.02.08.47.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 08:47:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=yn2ol6kB; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id C9B37803986C; Mon, 2 Oct 2023 05:00:10 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236885AbjJBMAF (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236857AbjJBL77 (ORCPT ); Mon, 2 Oct 2023 07:59:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14801D7 for ; Mon, 2 Oct 2023 04:59:47 -0700 (PDT) Message-ID: <20231002115902.564323243@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zPYr0Ydgl25/awrI3nekKS7noAl2zorfqWbbUsVIQD4=; b=yn2ol6kBePK92/CVO9nMPwtwkEEsQY3Ykf51fmhVz3y95uid0YFOPj2S5ujFBTuUOYkvzr ImvJGNWM4VNKTgwzrpRYneOdQGi1ftAsPMqiCf3Zf2bQsmr0mHPd3hS744XUe8bcV9JpiF 7BCHv52nmpt+ZYSH/gp27y3l5Xibzi/QCcggbqYflKVmXeFKdymn7vll3a6DyFGZsL3IF+ 3Vme0ebx3s4wtRhYuLNIwaBrBKJ1tTYB75W9wdc4ixb52Q/pYIR9TV5Pyd9uoH+lRsjzf3 X4k+s8Nu4jUKIb5c1VFOlo3a8gfxeU/+hnobjQVKCTei5wp8SNJKRksmXwQtTA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247985; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zPYr0Ydgl25/awrI3nekKS7noAl2zorfqWbbUsVIQD4=; b=AKn2Ahc995IbJqR7HuqRbyxXslTXz1k/SMqOD4rUDC+9032YVQFBzw0+mmU4uxuekS4Xb/ hLznSzMLPQSqpwCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 09/30] x86/microcode/intel: Switch to kvmalloc() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:45 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:10 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778659259558478519 X-GMAIL-MSGID: 1778659259558478519 From: Thomas Gleixner Microcode blobs are getting larger and might soon reach the kmalloc() limit. Switch over kvmalloc(). Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 48 +++++++++++++++++----------------- 1 file changed, 25 insertions(+), 23 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -243,7 +242,7 @@ EXPORT_SYMBOL_GPL(intel_microcode_sanity static void update_ucode_pointer(struct microcode_intel *mc) { - kfree(ucode_patch_va); + kvfree(ucode_patch_va); /* * Save the virtual address for early loading and for eventual free @@ -254,11 +253,14 @@ static void update_ucode_pointer(struct static void save_microcode_patch(struct microcode_intel *patch) { + unsigned int size = get_totalsize(&patch->hdr); struct microcode_intel *mc; - mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + mc = kvmemdup(patch, size, GFP_KERNEL); if (mc) update_ucode_pointer(mc); + else + pr_err("Unable to allocate microcode memory size: %u\n", size); } /* Scan blob for microcode matching the boot CPUs family, model, stepping */ @@ -530,36 +532,34 @@ static enum ucode_state parse_microcode_ if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) { pr_err("error! Truncated or inaccessible header in microcode data file\n"); - break; + goto fail; } mc_size = get_totalsize(&mc_header); if (mc_size < sizeof(mc_header)) { pr_err("error! Bad data in microcode data file (totalsize too small)\n"); - break; + goto fail; } - data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); - break; + goto fail; } /* For performance reasons, reuse mc area when possible */ if (!mc || mc_size > curr_mc_size) { - vfree(mc); - mc = vmalloc(mc_size); + kvfree(mc); + mc = kvmalloc(mc_size, GFP_KERNEL); if (!mc) - break; + goto fail; curr_mc_size = mc_size; } memcpy(mc, &mc_header, sizeof(mc_header)); data = mc + sizeof(mc_header); if (!copy_from_iter_full(data, data_size, iter) || - intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) { - break; - } + intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) + goto fail; if (cur_rev >= mc_header.rev) continue; @@ -567,24 +567,26 @@ static enum ucode_state parse_microcode_ if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - vfree(new_mc); + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; mc = NULL; } - vfree(mc); - - if (iov_iter_count(iter)) { - vfree(new_mc); - return UCODE_ERROR; - } + if (iov_iter_count(iter)) + goto fail; + kvfree(mc); if (!new_mc) return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; + +fail: + kvfree(mc); + kvfree(new_mc); + return UCODE_ERROR; } static bool is_blacklisted(unsigned int cpu) @@ -643,9 +645,9 @@ static enum ucode_state request_microcod static void finalize_late_load(int result) { if (!result) - save_microcode_patch(ucode_patch_late); - - vfree(ucode_patch_late); + update_ucode_pointer(ucode_patch_late); + else + kvfree(ucode_patch_late); ucode_patch_late = NULL; } From patchwork Mon Oct 2 11:59:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1413905vqb; Mon, 2 Oct 2023 06:08:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENcDpeN52tsEi6of9qWelopxtq5KV8+NTHDcbdZ31/Xpja1ICNWJTuSubs3WFnVh9b7E7M X-Received: by 2002:a05:6808:1788:b0:3ad:fcd4:275e with SMTP id bg8-20020a056808178800b003adfcd4275emr13913574oib.35.1696252124019; Mon, 02 Oct 2023 06:08:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696252123; cv=none; d=google.com; s=arc-20160816; b=FpOEgUcs9G9Vy1rlHKEuT96UW19s1bkW/9YZs8CXTWF4yE0TG2ykkMYZ2p/jHq7NNE Z9BIm0mIXSjmQ3UCNC4yAXt3gSISgzTb/hoEvGfGReN4YD7d2CgskOROXGXlXqP68PNv 4S/YMynML0BRLQKNQ3MAZEVftqWNs+2HqydYk5lLFBmIsnd+q+nUjhaU9IHeLUZXf+bT JN1ir/bMIqJJPdzC0rQ/dz6eEiYX4G9aJCuPRbV9rbNQnHxs27iVL489xFrFAnrs2jWi BWKEnmfJHKZGyzU3Fi+G1hwYBoLnzNdat8T/gw4zuDA3qRKsGxBVBqYhxnYbBqsoI0sZ Bj4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=6QTtAY94WVgFeqVOBeoLwL5w5RpplIpcErlL3QoLU9M=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=dCf2XmgLE6ZM+asRiJlUPIZPL9VBkRxuvLS6+LaCACZnMomiZrr0ffytP8FwI+5rvl 0FNzZ45qhfMifX8BBG5M7NfYbS28rRyxSdAYyyQJ2cqzQOHMGswWGikmxXLPz7noggtZ RE6p78z+8oANGv1nvSXf0WWJc871GuFS31Ciz9iL1KfGpoQCc4FPsz/m3I8j+LEjO8nj 160F7J7vt6zbqTa4wyhXwQwHcXhsF6R3kZmXk8W2uAr/WybN5AzDApNVAtz/6Nu13xxu NegaTt7XyaUvpYiXiCgWWW4eAASA7XyrhBLmvP220CjBTIx3dYlyPo3Ndg8+OwAKatNW tWnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FJ+d98A8; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=EdBNalcx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id kk18-20020a17090b4a1200b002748c1bbd79si8679570pjb.6.2023.10.02.06.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 06:08:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FJ+d98A8; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=EdBNalcx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 4C06E8048D85; Mon, 2 Oct 2023 05:01:38 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236901AbjJBMAL (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236887AbjJBL77 (ORCPT ); Mon, 2 Oct 2023 07:59:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 828B1E8 for ; Mon, 2 Oct 2023 04:59:48 -0700 (PDT) Message-ID: <20231002115902.625388847@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247986; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6QTtAY94WVgFeqVOBeoLwL5w5RpplIpcErlL3QoLU9M=; b=FJ+d98A82j4dhHNhXNhPZgPnPK4DgXguEIX2zPE2yrw6prAZU3VVVSJDAZ0ID4Rgny277X 2vhwMzX34YZXxgDg/oMJJugMSmDXqFtyrA8wSicPVu6WKYghyss00IQQxwm8OxPwkaXC0P 1tGe2Pt7wh+bIRu/bW1qhYpJAsP5FyY4BNlwOaH/4XUphrv7AKaW7qLAmzY4wkAs1e5vfd TEwyLcSMWStT34VVIgGtyVyi370Mw8AKhlqIIw40YTZPtbq8WCuYn+Iy3Xz7hR3nQH2CiR /CnGaMs7BMCoti+FS4OeunF371UPiUvP9u4U8OysOtYnigv1b9Yz6IHAEdU7wQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247986; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=6QTtAY94WVgFeqVOBeoLwL5w5RpplIpcErlL3QoLU9M=; b=EdBNalcxNPXNmadOD/Ahrxp+JctRBlRCrxZCFo3jahEU8iNtbfyYvhYieGPvu2QYMizuop ppvjLNcqlC3cOvDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 10/30] x86/microcode/intel: Unify microcode apply() functions References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:46 +0200 (CEST) X-Spam-Status: No, score=1.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, PDS_OTHER_BAD_TLD,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:38 -0700 (PDT) X-Spam-Level: * X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778649266963410988 X-GMAIL-MSGID: 1778649266963410988 Deduplicate the early and late apply() functions. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 105 +++++++++++----------------------- 1 file changed, 36 insertions(+), 69 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -294,12 +294,11 @@ static __init struct microcode_intel *sc return size ? NULL : patch; } -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +static enum ucode_state apply_microcode(struct ucode_cpu_info *uci, struct microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev, date; + u32 rev; - mc = uci->mc; if (!mc) return UCODE_NFOUND; @@ -308,14 +307,12 @@ static enum ucode_state apply_microcode_ * operation - when the other hyperthread has updated the microcode * already. */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - uci->cpu_sig.rev = rev; + *cur_rev = intel_get_microcode_revision(); + if (*cur_rev >= mc->hdr.rev) { + uci->cpu_sig.rev = *cur_rev; return UCODE_OK; } - old_rev = rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -330,13 +327,24 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; uci->cpu_sig.rev = rev; - - date = mc->hdr.date; - pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); return UCODE_UPDATED; } +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +{ + struct microcode_intel *mc = uci->mc; + enum ucode_state ret; + u32 cur_rev, date; + + ret = apply_microcode(uci, mc, &cur_rev); + if (ret == UCODE_UPDATED) { + date = mc->hdr.date; + pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + cur_rev, mc->hdr.rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); + } + return ret; +} + static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; @@ -450,70 +458,29 @@ static int collect_cpu_info(int cpu_num, return 0; } -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc = ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; - - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() != cpu)) - return UCODE_ERROR; - - mc = ucode_patch_late; - if (!mc) - return UCODE_NFOUND; + u32 cur_rev; - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - ret = UCODE_OK; - goto out; - } - - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev = intel_get_microcode_revision(); - - if (rev != mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); + if (WARN_ON_ONCE(smp_processor_id() != cpu)) return UCODE_ERROR; - } - if (bsp && rev != prev_rev) { - pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + ret = apply_microcode(uci, mc, &cur_rev); + if (ret != UCODE_UPDATED && ret != UCODE_OK) + return ret; + + if (!cpu && uci->cpu_sig.rev != cur_rev) { + pr_info("Updated to revision 0x%x, date = %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev = rev; } - ret = UCODE_UPDATED; - -out: - uci->cpu_sig.rev = rev; - c->microcode = rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode = rev; + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; return ret; } @@ -654,7 +621,7 @@ static void finalize_late_load(int resul static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, }; From patchwork Mon Oct 2 11:59:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147433 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1635822vqb; Mon, 2 Oct 2023 12:10:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEd+ppC/Ka4jyZHt5n3dqf3rTQhhkao8Cm6G5hJWGqbRmyUZxR2HEJThWjXI/9nPyF2JN97 X-Received: by 2002:a17:90b:3a85:b0:278:faf8:af9f with SMTP id om5-20020a17090b3a8500b00278faf8af9fmr11524016pjb.20.1696273824323; Mon, 02 Oct 2023 12:10:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696273824; cv=none; d=google.com; s=arc-20160816; b=uPWkiD0FfCuy0RLA4eYdxdipooHDHRwCvD+WVrrrHU7LRwxvdY3PIuou/Kd+DjBJAD w94jr1qC4OZkGF8VSIwAoNyDmiWM6ewcCMcJoQHcnjTexdu84Rw63tcrAJYqgSTUZY+W f9KHWjwDd0e1l05uym2KnYuLZqtxDehB7if3FAIuk1uiA+UNMXNHzrzeAljr3p1Z0u9T S2TrcGg27FWU7B6DuHkOsBqrrYm4+cy2gTdFKaPUn/omM594sOygT5ElwQCdoMdE61Pz zwUiUzK5sHBwRIzMkZQog6r24LMeRK+gNmXrIzGZSKfP7hJ0V509edEuhyb6g/5k91G3 edKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Y5qxxKqecrle90S2dXSe1Mr+hVulDTSr+daYuKbLlV8=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=VXGJkaSt1Ci7eMH/ygN4PzbopU6vEDMRAF2ajlH4AIWUF9bWfIYHoqmEaD09NtdgID TYe32j1JpqS2YAVovIX3Vs+xejULkFpbMuvIVuKYo2pcRLqUi9qDvv5/fuAN3QOMuDpd twH3n4Lpfm6XGWHvvreJ36hl+iY547ZgZArX1r4wqog2hnW1lCQMnl7kmttYV1HT2IUd 8JVS+m6Xs95DShYUd2Xr2yqZrYNMUAOnNlzwYXVBk79OZDWwRhjwqd5WBwQQdrakFiiS 31U3grJDVkg6HjUfkHcwWYc8siPnbZCFIRRRdK9u0m0DIh3MnbWmIL9SHJOdWeh+gQyD G1tQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=bmensbdz; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kd5tbAIK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id f4-20020a170902684400b001bdc664cd5fsi25497108pln.168.2023.10.02.12.10.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 12:10:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=bmensbdz; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=kd5tbAIK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id C0F918106878; Mon, 2 Oct 2023 05:00:42 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236933AbjJBMAO (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236893AbjJBL77 (ORCPT ); Mon, 2 Oct 2023 07:59:59 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B3C0F2 for ; Mon, 2 Oct 2023 04:59:49 -0700 (PDT) Message-ID: <20231002115902.684026662@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Y5qxxKqecrle90S2dXSe1Mr+hVulDTSr+daYuKbLlV8=; b=bmensbdziZmshoPUC1vUh4BpkQ7Qnsg2EkOBQlm5HyU7L4/ktzCTe8Yk2lXP/W2a7+6EVa ZIorSy0pw079gFUXT99N7BKxo/L4HqkpNZ9Eh0AyvvIs9qjLDmmQkGkyqGGc/y7rP18D7P Vn4qgK9TUzbNh4vbhMWkJ4Gb3f2n4RO6b1N78duvH33LkyNpYUH/DrioDCHo+H3eyGzhCM 4UYPEY1ZWwUH7MYFTldwKtT1RFOH1EwZjKzfn1gVkIiCVvLhc15djX7k9M1kbE0C/A6HEY Zhc1ZGcGryBl18xMkDfk08vOdvcj7lzKFPWQFbWKSDfY6O91yYBrzZ3XjKNtMg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247988; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Y5qxxKqecrle90S2dXSe1Mr+hVulDTSr+daYuKbLlV8=; b=kd5tbAIKuoATrkVyfG8j5tt9s7V3FKK8wnxgaU6lE8ymh85ygPfCbzr2//n4sTrrwCYp49 ZN75/+FKo1YtP9Ag== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 11/30] x86/microcode/intel: Rework intel_cpu_collect_info() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:47 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778672021658190736 X-GMAIL-MSGID: 1778672021658190736 Nothing needs struct ucode_cpu_info. Make it take struct cpu_signature, let it return a boolean and simplify the implementation. Rename it now that the silly name clash with collect_cpu_info() is gone. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/include/asm/cpu.h | 4 ++-- arch/x86/kernel/cpu/microcode/intel.c | 33 +++++++++------------------------ drivers/platform/x86/intel/ifs/load.c | 8 +++----- 3 files changed, 14 insertions(+), 31 deletions(-) --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -73,9 +73,9 @@ static inline void init_ia32_feat_ctl(st extern __noendbr void cet_disable(void); -struct ucode_cpu_info; +struct cpu_signature; -int intel_cpu_collect_info(struct ucode_cpu_info *uci); +void intel_collect_cpu_info(struct cpu_signature *sig); static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, unsigned int s2, unsigned int p2) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -66,36 +66,21 @@ static inline unsigned int exttable_size return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } -int intel_cpu_collect_info(struct ucode_cpu_info *uci) +void intel_collect_cpu_info(struct cpu_signature *sig) { - unsigned int val[2]; - unsigned int family, model; - struct cpu_signature csig = { 0 }; - unsigned int eax, ebx, ecx, edx; + sig->sig = cpuid_eax(1); + sig->pf = 0; + sig->rev = intel_get_microcode_revision(); - memset(uci, 0, sizeof(*uci)); + if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + unsigned int val[2]; - eax = 0x00000001; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - csig.sig = eax; - - family = x86_family(eax); - model = x86_model(eax); - - if (model >= 5 || family > 6) { /* get processor flags from MSR 0x17 */ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig.pf = 1 << ((val[1] >> 18) & 7); + sig->pf = 1 << ((val[1] >> 18) & 7); } - - csig.rev = intel_get_microcode_revision(); - - uci->cpu_sig = csig; - - return 0; } -EXPORT_SYMBOL_GPL(intel_cpu_collect_info); +EXPORT_SYMBOL_GPL(intel_collect_cpu_info); /* * Returns 1 if update has been found, 0 otherwise. @@ -377,7 +362,7 @@ static __init struct microcode_intel *ge if (!(cp.data && cp.size)) return NULL; - intel_cpu_collect_info(uci); + intel_collect_cpu_info(&uci->cpu_sig); return scan_microcode(cp.data, cp.size, uci); } --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -227,7 +227,7 @@ static int scan_chunks_sanity_check(stru static int image_sanity_check(struct device *dev, const struct microcode_header_intel *data) { - struct ucode_cpu_info uci; + struct cpu_signature sig; /* Provide a specific error message when loading an older/unsupported image */ if (data->hdrver != MC_HEADER_TYPE_IFS) { @@ -240,11 +240,9 @@ static int image_sanity_check(struct dev return -EINVAL; } - intel_cpu_collect_info(&uci); + intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, - uci.cpu_sig.sig, - uci.cpu_sig.pf)) { + if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Mon Oct 2 11:59:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147313 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1457188vqb; Mon, 2 Oct 2023 07:15:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzjf5HZ5Q5624J5/HCUDEEFTDPGjIhAEyRwOPo36m09yLYhoEB9CBxgiV37z8KWU6i1g+R X-Received: by 2002:a92:c94f:0:b0:349:67b0:6045 with SMTP id i15-20020a92c94f000000b0034967b06045mr11456694ilq.3.1696256106701; Mon, 02 Oct 2023 07:15:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696256106; cv=none; d=google.com; s=arc-20160816; b=rC0T2KDY5BMx1RYQnK75voXj3YE2URDfl7QcgoqorJh76qMam4TMlIMpfsJEnt3qFn xSHa75JewJ+MjHtBBB/5gjQAHXzinQ0fSuzKVx3pRZn8an8tjSsVuZ+IYpvKdm5MvFTv tiwgEk/i4dB0FsQ2+y1y0Bw74JCQ9h9u7PS/W6H2RXM7GNcvnKkz0srlkPOiTwkxCRTB y/zFmN2giHiicnYKNGX1W4ZVkh4SJzwm67SEU5KG+9Kc6L4iEAzhrxh9XEXemJOh/IS8 RMbL8K1r6rPID/K6Bci0bNhKrYQWigIs4kL2e/8Q5DjIUbBBIUKHJxANcDwdyQBlSjYv mEUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ihivJowKww+fe1UCzdxyPRQezAmQeOqgMJYs1huTU/U=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=dTiFjyKGR3gTmj8bwfPTMzqrKXnmFxSXBuT+99K2sEqSwaeP5+po/IcJMtwvXzlx+f KAdCZqHClTKFNiAkCERl+Is0+wXsCNH0v8nZfKiOurpNgWdpUnuCRwHVH6hneY20KULp sWf3B+YOk4MyBp5n7dFj89qoGN8OWC/0DKb6SFtaphuuCpVkaxxUMMg/psuQcIV0B7QT YxT//6tBpJ+49/ewByFLQEy+wcitKIMo1sEPqEDf3anRPMX8vwbZgKVnVcc6ZR6pW843 jRnnJ2k0dFFU+wvzXDyx9h4K0+CqMNimd9w5P7kYIo6q8bShgM7c4Ee3n5efTxB32R2T gxDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wWaFWCqr; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id j190-20020a6380c7000000b0057745d87b4csi26910052pgd.526.2023.10.02.07.15.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 07:15:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wWaFWCqr; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D235B810C2CC; Mon, 2 Oct 2023 05:00:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236937AbjJBMAQ (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236905AbjJBMAA (ORCPT ); Mon, 2 Oct 2023 08:00:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD17D115 for ; Mon, 2 Oct 2023 04:59:50 -0700 (PDT) Message-ID: <20231002115902.741173606@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247989; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ihivJowKww+fe1UCzdxyPRQezAmQeOqgMJYs1huTU/U=; b=wWaFWCqriKzwJj+tiIe3SEuTR4hlFXDY8SbkqL5M2A7hg42Mp8ZhaL+ZVT0QgCiPf/5wK9 Ws+g2sstPgt9NDgziMd89XKkGJDR9XgUHm7Ouf0fRkQQOHRzSbi3W6B+vsdV1FZ4paHnPS jyXGHAbNqGdBEmx2vd+BvDwK3ls2518fFJz2Q/pNDaSX1inD4ZaMBbWClIg4+hBX3FwnIs SI/SLmb/kTgAErWaTk+QJjcA0Q4eD6h2IAQJ3acpH9MToicyE6Jtmr7ffbkEt9I1AeEnrd g9nrnOh8wREw1sGqWPox3Levp/XxoS+xs3Sirg+g4HJ2DUlY9lc5hgdhyA0AmQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247989; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ihivJowKww+fe1UCzdxyPRQezAmQeOqgMJYs1huTU/U=; b=XNFufHleMeX20JiOkPES/gphi9j4ns1gcdEigvhaBEjZ1lz4CE9I1Tvy6Uk+J6lpu5QLY8 +36OP5/o9FAGURDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 12/30] x86/microcode/intel: Reuse intel_cpu_collect_info() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:49 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778653443590584341 X-GMAIL-MSGID: 1778653443590584341 No point for an almost duplicate function. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/intel.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -425,21 +425,7 @@ void reload_ucode_intel(void) static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { - struct cpuinfo_x86 *c = &cpu_data(cpu_num); - unsigned int val[2]; - - memset(csig, 0, sizeof(*csig)); - - csig->sig = cpuid_eax(0x00000001); - - if ((c->x86_model >= 5) || (c->x86 > 6)) { - /* get processor flags from MSR 0x17 */ - rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig->pf = 1 << ((val[1] >> 18) & 7); - } - - csig->rev = c->microcode; - + intel_collect_cpu_info(csig); return 0; } From patchwork Mon Oct 2 11:59:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147258 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1381064vqb; Mon, 2 Oct 2023 05:13:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF1DNyzsTPgOWDyXG2bfBaZf6p3PTG5cFgfKLVo+bGpvvOhroWFbJO1FXums40LNJXw8QK1 X-Received: by 2002:a9d:4f15:0:b0:6c0:a95b:44e4 with SMTP id d21-20020a9d4f15000000b006c0a95b44e4mr11403485otl.38.1696248793527; Mon, 02 Oct 2023 05:13:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696248793; cv=none; d=google.com; s=arc-20160816; b=V5B/vmj111VUO9Oe7poP9KeCbIkeUQHhmWnV2SlmEaA+ibzHsd0W2/DVIBHcJDSI3U DxCdG7eKWr6U6e0XJblr75L7JxL6h8FjiolNQrFWmS0r3zpLY/oIxkUCeKUfKHAMxTGP N7pGhXDUDhbbM7VOMDUBOFCfFl/4W9GmCzRA7sTe3cidtsBL6eMV5skFLlhQPfJqXKDn hdLGqK2APz/qBbOslnW16vgxzApzn5jCafJvbAXagmjX1Q3p3zJcq32YGXMZamK+bVdv tZRCaTRMLYniar51CXddpiGVrBYzVwueB7L+mPWJAtVEJsjxCfOvoudjtneW4xynE+CN qSqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=Edjc5SXneM2Y7YATZhugxt5CD7O42zD0vvyDzGON3Qo=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=yqBjkDN1+fKZSTdHI63Qn3TFF4PmLoC8bDy6QXYQOZZki4ze6t4f9BJwX6BxQ76/GR Uv2GRVNR1CaRrxT3SpuixfEZ2/SY8JpKOlMnPVubdvqenMYqNt+x7SGZhLHxAuke9yT0 NyqEFA9UQSZ58WQyXMMqcl9/IPqtMseJaA5zo6hqW07Z4ApskQnn/lqhY5DthTHwE6es H297UdE40xQf8aTRDKSDkCHn2ZanXEZ07ZYgwyHUHm1K5f6MpVReV/ofJXcNqZwX4OOp 3q9Zwt1rffdmUX2lBsXUExGB+GdnQH+cpT3fW7ozuvn40nLwFByyBhuJoUy+qCnBUaNW qzDQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FYWBqoSY; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id g123-20020a636b81000000b005775a4a2960si27022859pgc.261.2023.10.02.05.13.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 05:13:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FYWBqoSY; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 5504C8030D13; Mon, 2 Oct 2023 05:00:34 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236897AbjJBMAY (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236914AbjJBMAA (ORCPT ); Mon, 2 Oct 2023 08:00:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1D5861AE for ; Mon, 2 Oct 2023 04:59:52 -0700 (PDT) Message-ID: <20231002115902.797820205@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247990; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Edjc5SXneM2Y7YATZhugxt5CD7O42zD0vvyDzGON3Qo=; b=FYWBqoSY5GXWUA06qH9KUcKD01kDPSrjc80iVMpJrUfvNQEP/c+ZB3FgehcCdrXTzy1ElL 1n9Yh1UKCYr8UhVFAmA2pnUoArRGg9g1NziyayhhBCj0MRzVAk8bR5nFMkj41fjwEIlHuy UpNWvNjhb/E3nLXwRvL3G/NkjX0zHtxEvSpKTKvjYARyUjA3TBiWU8hZgPKVIiE064o7uM PAVZZ5hQyC/S4cQC0VdRgLrQHi/2IhtD5KytwArIYpeHkk6Zwn0VOtB+/wqY5ZswTYcc49 LOZhux9cHgACTKuNoQaEuR1nke17mqkcyYQE8kxcRrT0qMQmDU1VKZdbKZwRIw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247990; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=Edjc5SXneM2Y7YATZhugxt5CD7O42zD0vvyDzGON3Qo=; b=k/iqOT8qBEo9Y7t90O1resES/FxwmjKxD73vqLztEXcR+99XCAF05HAcDqOfdLEHuMa+cu QqHIucSVXLyxw2AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 13/30] x86/microcode/intel: Rework intel_find_matching_signature() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:50 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:34 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778645774834782418 X-GMAIL-MSGID: 1778645774834782418 Take a cpu_signature argument and work from there. Move the match() helper next to the callsite as there is no point for having it in a header. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/include/asm/cpu.h | 16 +--------------- arch/x86/kernel/cpu/microcode/intel.c | 31 +++++++++++++++++++------------ drivers/platform/x86/intel/ifs/load.c | 2 +- 3 files changed, 21 insertions(+), 28 deletions(-) --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -77,22 +77,8 @@ struct cpu_signature; void intel_collect_cpu_info(struct cpu_signature *sig); -static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, - unsigned int s2, unsigned int p2) -{ - if (s1 != s2) - return false; - - /* Processor flags are either both 0 ... */ - if (!p1 && !p2) - return true; - - /* ... or they intersect. */ - return p1 & p2; -} - extern u64 x86_read_arch_cap_msr(void); -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf); +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig); int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type); extern struct cpumask cpus_stop_mask; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -82,29 +82,36 @@ void intel_collect_cpu_info(struct cpu_s } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) +static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2, + unsigned int pf2) +{ + if (s1->sig != sig2) + return false; + + /* Processor flags are either both 0 or they intersect. */ + return ((!s1->pf && !pf2) || (s1->pf & pf2)); +} + +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig) { struct microcode_header_intel *mc_hdr = mc; - struct extended_sigtable *ext_hdr; struct extended_signature *ext_sig; + struct extended_sigtable *ext_hdr; int i; - if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) - return 1; + if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf)) + return true; /* Look for ext. headers: */ if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) - return 0; + return false; ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { - if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) - return 1; + if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf)) + return true; ext_sig++; } return 0; @@ -265,7 +272,7 @@ static __init struct microcode_intel *sc intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(data, &uci->cpu_sig)) continue; /* Check whether there is newer microcode */ @@ -502,7 +509,7 @@ static enum ucode_state parse_microcode_ if (cur_rev >= mc_header.rev) continue; - if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; kvfree(new_mc); --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -242,7 +242,7 @@ static int image_sanity_check(struct dev intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { + if (!intel_find_matching_signature((void *)data, &sig)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Mon Oct 2 11:59:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147364 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1539494vqb; Mon, 2 Oct 2023 09:23:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGLa/Z2QiavU/avRyVhR9vjFhxF1k8NUIxhMDUaKiaflUXhDmuAgbV0jqXkjGURJRHYjptt X-Received: by 2002:a17:902:da86:b0:1be:f45c:bc38 with SMTP id j6-20020a170902da8600b001bef45cbc38mr14388875plx.2.1696263825787; Mon, 02 Oct 2023 09:23:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696263825; cv=none; d=google.com; s=arc-20160816; b=ppDYPnBfofxfOpRGgOIb3pGMlKdyfu6yN8h4+mRagBKWxfS6drXPPgUbcS2hhqoZUH 2t/Mjqtn6mC7VeqXHTjGbGX6tsBm36zFHa5TwD3i5vEtWnM9rhtSemKIeEhhJhA+oPvG p5/QRZNWzfzLUlzbEJ4bmaIDYwRYYFmmxITEm2Lb+ck7o/PLABEhSo3ihAqBu0DUshiR 1RpxvW4fFP2BxgfdRV33CeBc4nnJn4d3t0cMafIruhT+iZ29+rEfG0/O4oRm7F0aonV8 FVySC2i5NJOsLiY8XXlB86YcAt1IK7bDiRXBJM+kFYdeGHo+V4Z1cmWS6Zkj8aNGMCAK nUeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=wSIKumgnxSQh4jImaEIP58qXBdiBffu/K6t5/ntvIzQ=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=DPQG8BUSwdcJqYXKunoJFMY61GCwokelkBUYrItxwB1Vm2r7EtAu05YxgA8cqIdOAi 1x3WsXLKbBDnz99irDwjmg6gk4IvhUUvQuFSer8fVXoMtJ1J/I/5HmxKd8JIFY8+4Zxp QdAfQoKqSmuFyx7XkzDcMlwPQZ6a+AsFDvRW7v9S6gMdf4vq8XaFVEWhFqyMVL//iXwi NCHTUDka0l6p2xcz50U9qedrbkzSWtC1IiNvguN2AdNhHixFOTYTM+51JFG2Tti5AcL8 qKksZPKI3EkOx5xwhRRj0BXym/Fw9cOCasquPV5jBdNKwwkzDDaYdpt0j2kpD7MDwDkg raLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tSDpcr5r; dkim=neutral (no key) header.i=@linutronix.de header.b=TBKKTtA1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id s1-20020a170903200100b001c62139b16esi16884140pla.4.2023.10.02.09.23.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 09:23:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=tSDpcr5r; dkim=neutral (no key) header.i=@linutronix.de header.b=TBKKTtA1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 28BA180A2226; Mon, 2 Oct 2023 05:00:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236960AbjJBMAa (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236921AbjJBMAA (ORCPT ); Mon, 2 Oct 2023 08:00:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 403D71B6 for ; Mon, 2 Oct 2023 04:59:53 -0700 (PDT) Message-ID: <20231002115902.854919221@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247991; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wSIKumgnxSQh4jImaEIP58qXBdiBffu/K6t5/ntvIzQ=; b=tSDpcr5rWCDpa5okkQctpU3oe2fk8ZQztVdUP8lJ+eg0iqaXsaT8RZcr9YMh3l+dJdnfOL vha25su6LdaNwPHe6Z4hc+g7DBiKcXHokZ9ID3LtOWYJjJ/dBXnE2gwySfxhERfwD7+bsu GE4adkXnzmhS15Jl5Rx/96uLkoCSKsOxCnBdVokVccSUBJEDnC92kJt0A13vd7RaCodcAj CLMr0pxWkNBjn8KU5geQc4CUrozwM+sDlX5fa7qFdal8eHIrmjOYSk4GO61KsC5ifRzQNB 3wwCiS+nSwyFDlVYsQnv3anxR+p+dlJpNNySE4M+/1eh9M5sJmDDqZbmrz1Mmw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247991; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wSIKumgnxSQh4jImaEIP58qXBdiBffu/K6t5/ntvIzQ=; b=TBKKTtA1j5HNxDEtmf3rFeMukhPCQNSKVB+EtkrfabEqMwQCo24qURJXZz2bMSmEpjxagS u2s0llm9RrQTIwBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 14/30] x86/microcode/amd: Read revision from hardware in collect_cpu_info_amd() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:51 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778661537379673995 X-GMAIL-MSGID: 1778661537379673995 Prepare to decrapify the core initialization logic which invokes microcode_ops::apply_microcode() several times just to set cpu_data::microcode. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/amd.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -634,12 +634,12 @@ void reload_ucode_amd(unsigned int cpu) static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig) { - struct cpuinfo_x86 *c = &cpu_data(cpu); struct ucode_cpu_info *uci = ucode_cpu_info + cpu; + u32 dummy __always_unused; struct ucode_patch *p; csig->sig = cpuid_eax(0x00000001); - csig->rev = c->microcode; + rdmsr(MSR_AMD64_PATCH_LEVEL, csig->rev, dummy); /* * a patch could have been loaded early, set uci->mc so that From patchwork Mon Oct 2 11:59:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147266 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1387830vqb; Mon, 2 Oct 2023 05:24:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQN/zZVEbou9IbZCFEnV5nWkEzQrYonKPPgojInsD6bZmOPtl3LhX56YcoJqicmPed3oma X-Received: by 2002:a05:6a20:9751:b0:14c:6cd9:bf9d with SMTP id hs17-20020a056a20975100b0014c6cd9bf9dmr9309237pzc.35.1696249474207; Mon, 02 Oct 2023 05:24:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696249474; cv=none; d=google.com; s=arc-20160816; b=tVfbR+cXzN9ovVKya+zq0MaseHBLvHDzpkUFuNOjwB9xBowrwmzNQcm1+vSCkklbnX ifNDEOUolIOb1MMnT+/3wkzO14VyTFsKu/MuA/Wa8LKr/8BeozE1txe5Yky1pjxqAtKZ fyO4FZXB4nJO/iRx70CF+j8PD3dPxcp1N7BYZh6rr+GQ+HfoW6wzvJ7Aukof68+wVaZB 02sR7W2yrRbr11Ro4DBAZPbbhX59SvL/C4I6n4RyEDa8TVIhuIaSfPFSHICTIoYwwzG8 7CjCguwdmOaYUkD4yFFSSOg4usqFqtUXB4L+Gi1G0vG65Nfz4dIKhPeHDCmtGB+1p37u vYZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=rHi089u9X95MCYe+6Slgr0l9oghgbG+86h4o3zvQkNE=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=FJJIXVG9LoDt84R/TSrEqMwicMBbqVQxyLdb8P8eLCwFcDATWC9jeRd48PbubA96pj l9ZqcD2Su0uA8vJLdmwKgo8VVmtmnvgh69ojQU2MBDgU8kYw+O6ch8Mn3uCzdASRfB/Z 3fj14V1SdWrf0IabBYgUIMWZ5M2ACt4h11AUG/0pNWmyCp6wOF3IkPsV1MS441xqPW/w DUPfe68/W2AWyS5ZwyWg7Z/rts0S+oU/NhIiM5PewU/EXOzczsM8qHqv1AazAr4rxBcW SY7FKC/sWxj6nI+85rTc6G84bO8soLIZ0UHYFs/aeDYhFuPuEVquDNWpEve1JX4z9Kj9 1UUg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=LB1Rpi07; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id f5-20020a056a0022c500b0068fb8704b9csi28847597pfj.28.2023.10.02.05.24.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 05:24:34 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=LB1Rpi07; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 21C738048F0F; Mon, 2 Oct 2023 05:01:10 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236849AbjJBMA2 (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236925AbjJBMAA (ORCPT ); Mon, 2 Oct 2023 08:00:00 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 916EB1BD for ; Mon, 2 Oct 2023 04:59:54 -0700 (PDT) Message-ID: <20231002115902.914469212@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rHi089u9X95MCYe+6Slgr0l9oghgbG+86h4o3zvQkNE=; b=LB1Rpi078hWn2/+ZoOUDZ2i2+hOukLr0RlRgCW6GjS6qqTibUJkS6M5oWfmQ7uZbCFu+P/ IPDKHIMZvfQpTzAPHwz4cX3/O5ZknIXoK3w/iWmJOYoAFiDrjM19CvdtrqPuTCOUdhsMwK BbwNc1wOaELFmkWEqhBAv2Kgf1AVMSViIzZMrs9JzKsgrOXmXrgeSK/SI3CxiZoe8F1g5C bFFpcHpsvtDk/S0x/m0rlJCycxsXgXtxcbaR76Hgque9Um1j/VxxTo5EvDUAS5ho5IcPim eXYE7x2LsTuKTDIcQ8RucTZhvEGlBWOGTX1stTk4FxHTxyGx9lmKlCj3WX0qZg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247993; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=rHi089u9X95MCYe+6Slgr0l9oghgbG+86h4o3zvQkNE=; b=yriIHcyDWEfqtiVp3kyxNo0poPHEY4mpvTr2dPFY7AsUXYnxCZkpPzyK4Itw/p40ACwaKU mojRa5YPCgOW94AA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 15/30] x86/microcode: Remove pointless apply() invocation References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:52 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:10 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778646488754740687 X-GMAIL-MSGID: 1778646488754740687 Microcode is applied on the APs during early bringup. There is no point in trying to apply the microcode again during the hotplug operations and neither at the point where the microcode device is initialized. Collect CPU info and microcode revision in setup_online_cpu() for now. This will move to the CPU hotplug callback in the next step. Signed-off-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov (AMD) --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 34 ++++++---------------------------- include/linux/cpuhotplug.h | 1 - 2 files changed, 6 insertions(+), 29 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -490,17 +490,6 @@ static void microcode_fini_cpu(int cpu) microcode_ops->microcode_fini_cpu(cpu); } -static enum ucode_state microcode_init_cpu(int cpu) -{ - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - - return microcode_ops->apply_microcode(cpu); -} - /** * microcode_bsp_resume - Update boot CPU microcode during resume. */ @@ -519,15 +508,6 @@ static struct syscore_ops mc_syscore_ops .resume = microcode_bsp_resume, }; -static int mc_cpu_starting(unsigned int cpu) -{ - enum ucode_state err = microcode_ops->apply_microcode(cpu); - - pr_debug("%s: CPU%d, err: %d\n", __func__, cpu, err); - - return err == UCODE_ERROR; -} - static int mc_cpu_online(unsigned int cpu) { struct device *dev = get_cpu_device(cpu); @@ -555,14 +535,14 @@ static int mc_cpu_down_prep(unsigned int static void setup_online_cpu(struct work_struct *work) { int cpu = smp_processor_id(); - enum ucode_state err; + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - err = microcode_init_cpu(cpu); - if (err == UCODE_ERROR) { - pr_err("Error applying microcode on CPU%d\n", cpu); - return; - } + memset(uci, 0, sizeof(*uci)); + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; mc_cpu_online(cpu); } @@ -615,8 +595,6 @@ static int __init microcode_init(void) schedule_on_each_cpu(setup_online_cpu); register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting", - mc_cpu_starting, NULL); cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -156,7 +156,6 @@ enum cpuhp_state { CPUHP_AP_IRQ_LOONGARCH_STARTING, CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, CPUHP_AP_ARM_MVEBU_COHERENCY, - CPUHP_AP_MICROCODE_LOADER, CPUHP_AP_PERF_X86_AMD_UNCORE_STARTING, CPUHP_AP_PERF_X86_STARTING, CPUHP_AP_PERF_X86_AMD_IBS_STARTING, From patchwork Mon Oct 2 11:59:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1734823vqb; Mon, 2 Oct 2023 15:50:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH16aOv1fslOADAjaUMGF+5U3skY0XP/r1z7ntH2rzln1H7tfSA7HhqFEhDv9bdMjRP8mYC X-Received: by 2002:a05:6a20:3d95:b0:13e:debc:3657 with SMTP id s21-20020a056a203d9500b0013edebc3657mr1106927pzi.30.1696287054372; Mon, 02 Oct 2023 15:50:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696287054; cv=none; d=google.com; s=arc-20160816; b=nCq/V5b4lmlCLLmCCIcUy0cMOmmcmmHJnZKivdXRKNPY8KbwwkhcQj6xmr2DB4LoDa FdadlWSFryw7KAaTSSpNhsU4UUmjr1BCoppHn8y8lvL3QS5uLGo7V84Hhe/QNEnvXw2s GYsi6Th+R+cvFpOG/h94FL/qH+1IFIIHy8n5bWm+3+dhLvs4c8QS2M3Y8E8AcqqbDSan 2AhaMeO7S+ZAYxztQn7WqxUC6EzpXaaHtfsh0GCab5AorzhZhXx3Ap8M8Fn553z/SptY Pu3RNtRtdMV6sA/7FzJ8nlMDLn9HdVairJQqGnROLumhEVyo2vB08shO5JFeflsDga6V CIvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=lI3+LwrA6MimboCQf/gMpTVBIb07iXYJSWw2tVS61ec=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=BtmhvcZjgnN4EDcUgR4Ep0BSNoEoxHtDMDmvhAWwhGwHYyQYKa3xJzVUUVKobrLkF6 vAGO8UCqFEvyGA4+mEW5GxU/t3cXjJPeXLUSpNnxA+8RnE6NZr+eFrNbh27BaiCXo6u3 O1OOX6R10u0rnhKQO3Az511mA4NefYltqVR856wAK9fxoAss2t8BGtcV6Fo5rne8h2eB brzwwzy+TO6ChtplVtmnxFLFU6ZIdggytYGlNAMWcRyRNO5Sv6cg+dRtnJqJ07veNeCL xVnX2Zs2Q9VROfCVmoJrYtZqgw5HquDszvvj77ybDP23oXAo0or0o/X0uNi8FlkzU/ZV Vs6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Wp9I6xd7; dkim=neutral (no key) header.i=@linutronix.de header.b=dvJTVZRI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id w2-20020a637b02000000b00573fb2f7537si28619347pgc.586.2023.10.02.15.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:50:54 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Wp9I6xd7; dkim=neutral (no key) header.i=@linutronix.de header.b=dvJTVZRI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id DE25C810C2EE; Mon, 2 Oct 2023 05:00:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236869AbjJBMAc (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236941AbjJBMAV (ORCPT ); Mon, 2 Oct 2023 08:00:21 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0CBACC4 for ; Mon, 2 Oct 2023 04:59:55 -0700 (PDT) Message-ID: <20231002115902.971709581@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247994; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lI3+LwrA6MimboCQf/gMpTVBIb07iXYJSWw2tVS61ec=; b=Wp9I6xd7IiOCzUoPlpJhDGFCm4aPZSxN44w28ehk4bNry/LR1yYU3kgepXt+pfXPSpBkR6 3lwXXjKzsgs9U/hB9IgPuyY+NkiHW8jp12DBN/jETmyBwChSXYmVNB54n9b3zq4/8PlXcJ /Uh2GTcaq/x2J2GLk+Vm7pIgPp2+A01lGl0+hm4xkCNOigXZgxslJEVsQMu/6D2edD76TE qoQNRe0tYGCTstO6jXkkCUusOrOgHbgk7qG30yKXPtQ24TEv8W3Ent5Yq0c4IvfG4SI9re 8fLqJGl7EPawOAHod9KTRh3YjZonx3pA/7r9aNYMQrjyxcjgA0uDRl1u7sD20g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247994; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lI3+LwrA6MimboCQf/gMpTVBIb07iXYJSWw2tVS61ec=; b=dvJTVZRIaGkey0iEnVOKIxdRNzx5888IbAez8+qbXsGEHDlaUdW3m0/EMis7sILeMqgdgR z3j4OpvJrOzKq+BA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 16/30] x86/microcode: Get rid of the schedule work indirection References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:54 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778685894461026861 X-GMAIL-MSGID: 1778685894461026861 Scheduling work on all CPUs to collect the microcode information is just another extra step for no value. Let the CPU hotplug callback registration do it. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -510,8 +510,16 @@ static struct syscore_ops mc_syscore_ops static int mc_cpu_online(unsigned int cpu) { + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; struct device *dev = get_cpu_device(cpu); + memset(uci, 0, sizeof(*uci)); + + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; + if (sysfs_create_group(&dev->kobj, &mc_attr_group)) pr_err("Failed to create group for CPU%d\n", cpu); return 0; @@ -532,20 +540,6 @@ static int mc_cpu_down_prep(unsigned int return 0; } -static void setup_online_cpu(struct work_struct *work) -{ - int cpu = smp_processor_id(); - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - cpu_data(cpu).microcode = uci->cpu_sig.rev; - if (!cpu) - boot_cpu_data.microcode = uci->cpu_sig.rev; - mc_cpu_online(cpu); -} - static struct attribute *cpu_root_microcode_attrs[] = { #ifdef CONFIG_MICROCODE_LATE_LOADING &dev_attr_reload.attr, @@ -591,12 +585,9 @@ static int __init microcode_init(void) } } - /* Do per-CPU setup */ - schedule_on_each_cpu(setup_online_cpu); - register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", - mc_cpu_online, mc_cpu_down_prep); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", + mc_cpu_online, mc_cpu_down_prep); pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); From patchwork Mon Oct 2 11:59:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147408 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1598352vqb; Mon, 2 Oct 2023 11:02:44 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGa34SBe1wez9P0uKjOVuD7jsTuxUgJbZRSxbd4DQaEezBpL1RdiaQW9O3GJPAITENrU48B X-Received: by 2002:a05:6870:ac25:b0:1b0:17f2:6518 with SMTP id kw37-20020a056870ac2500b001b017f26518mr15051176oab.42.1696269764504; Mon, 02 Oct 2023 11:02:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696269764; cv=none; d=google.com; s=arc-20160816; b=NVMRN7dKmoPDp8vMpEn1sF5n0r5M8o/91lTHfOOtpDXzogPnKIOVvoGkM7zj/Vxvx1 JlXEaxwOqxQd9dxJ+Qg0m/sBflQJqoyhpJDRWYoaFvOE/E1Bq95NBPBukIsXhpRMkE9v DT2LtwwMH0eFwHN7vsywfAmT6GSnpRQX/TxVGmoA7R8DFyXktyDTs/YoEpwqzdatQPym fqbwX2XD0gXNSAC19Jw0U/hmXbEn6ldPYMDzyAODxB8dKBXEyseBYxHoJb5SNVfE+goG PnVaRcxDhwz+xQRDgqL5orrdCK890VovSmPv19pnHzxGUyg4KBqDaIrBPQd5cv7Dv8LG H0xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=7j90uOLtW2Wz9UtqDt1Dp/sqHiCZcf49IdRLgKDZvBw=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=m3ryZnOaiIHRHsfbow2+N6V/ygIdR+K3fmbN35fR+gDDj+lfrVK1vJqllGJ4ri9uto PbZ5RxJ/6zM+OB7JYLtmzxkeVUevUZavvuaQm9uLKoQ6rXMx0ze3HfWgfzPv7lm5y/D5 9DWRK/WOBwGtJIRr/hGUNgGBesMi9bQtmR8w5l3eucFLqi2FGPq4Cxtfa+hBFDqQ7T32 DGRCEnQVTrKpAy9SfaYH/zPA6Rc2EA/1WNXF5ct7vmFYvDjlG6MXsRlLrfQ76b8omyvl cD2AHuOC0zqNgHmcRi/gTunINDhd98j2Qws2IIVn2wwqssE5xOZ0xzXC0BZqCCXzLRz6 Rh3w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FAZjiJ69; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=TK+09Dsj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id z11-20020a6552cb000000b005775a0cd009si15604685pgp.331.2023.10.02.11.02.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:02:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=FAZjiJ69; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=TK+09Dsj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id AA14F802AFD8; Mon, 2 Oct 2023 05:02:09 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236932AbjJBMAf (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236946AbjJBMAW (ORCPT ); Mon, 2 Oct 2023 08:00:22 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E425CCCC for ; Mon, 2 Oct 2023 04:59:56 -0700 (PDT) Message-ID: <20231002115903.028651784@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247995; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=7j90uOLtW2Wz9UtqDt1Dp/sqHiCZcf49IdRLgKDZvBw=; b=FAZjiJ692BNjL7M3QRIjWGOh9L7JutBy22k9ZlFOJfpicREccxMM2sbNeu9RVwIWmcfqym 7zgvao+1iBLiMrEQN5NYriWwPexJc069HWuS19nlqUMMK0DymyZ8xna+5HaIra8cyuByD+ FgGrlXL7jwF4I2F9q9bRKAxrEKPHcjOQ8WrqOVoi3r6hwkEGcS2vP5F1Vf5+4d8NlkAyi2 /gtX1DhQsf0nCGgTM34qm4zDAHNdP9hHm0LbyAqNsMOxAoGGpzXkDfisil5qtrCL+FLz16 qmHQh40Jtrif03klDVAv3vnux4ON0naJYIUH4ikQIfzGVoqJd5NA9ITkn/eRBQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247995; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=7j90uOLtW2Wz9UtqDt1Dp/sqHiCZcf49IdRLgKDZvBw=; b=TK+09Dsj/i8zlx64hwldIx+xmav0JdFReJ64MI2lZPzHncy/tailjJEa/JKQZqiAAHW70T 8CXkEIk/QfKrynDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 17/30] x86/microcode: Clean up mc_cpu_down_prep() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:55 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:02:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778667764290204326 X-GMAIL-MSGID: 1778667764290204326 This function has nothing to do with suspend. It's a hotplug callback. Remove the bogus comment. Drop the pointless debug printk. The hotplug core provides tracepoints which track the invocation of those callbacks. Signed-off-by: Thomas Gleixner --- V2: New patch --- arch/x86/kernel/cpu/microcode/core.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -527,16 +527,10 @@ static int mc_cpu_online(unsigned int cp static int mc_cpu_down_prep(unsigned int cpu) { - struct device *dev; - - dev = get_cpu_device(cpu); + struct device *dev = get_cpu_device(cpu); microcode_fini_cpu(cpu); - - /* Suspend is in progress, only remove the interface */ sysfs_remove_group(&dev->kobj, &mc_attr_group); - pr_debug("%s: CPU%d\n", __func__, cpu); - return 0; } From patchwork Mon Oct 2 11:59:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147402 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1586708vqb; Mon, 2 Oct 2023 10:41:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGMLaaG8bWNLzVkrbNRU0V6sDbWuOprYYIQJl/7rw9dUzMQYGV5bbQYgkIeR7pf9Zrt0OMK X-Received: by 2002:a05:6a00:1788:b0:690:d0d4:6fb0 with SMTP id s8-20020a056a00178800b00690d0d46fb0mr13554911pfg.3.1696268512265; Mon, 02 Oct 2023 10:41:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696268512; cv=none; d=google.com; s=arc-20160816; b=r3bNIDuh4Y6se/d1JC+sonhK9Q1WwxA575FyoPaFpGWOLSD27bueJvYwP8wRZh4t2x MaEva37SJXGaHyVrFKjsqsJA8Nml/6m3kav/qn+HgRjJtLTCRzSLEksH+YOKmcfJUtcU lGVm/Hdt52+uTvuWFQoeBC5+VPlCxS9F+XjhnvwekM+BmodXuca4L0IMJevyWtEDOvwu RORW8lmeiWWYrMrD8RzYgc8MAdZlEqB+18S07t1/+FD3TZFkN32US/mriJQ7SAbcpUyU wXkZrsTreun0d45dS77GWnsNj/s2yg1g6O5K7HMVzWP5cNYqMWleMJnRy9Vy55BzrzCX hspA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=J0zNjtrmxlOZ3cIxLGlZizAd9pmzXfVNcRvGruLfMIs=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=CiNZt/tuRG+p+eQaH1Df6R+IeqSFjDYVFEWecBObGYwKiNgUPmEKe/5QRAAfBJ9nL/ E1PYSc96Uu+Q5xInQ9BpsBEnzZQWTUWmoJgR8HH1PwtT8+l3tuE/MWYbE8hGjMsZ/kQZ OifRPrM5wecKdR3JmqgjJIzXsATYND1BaOv1lh0I9rXqiXqNPTjLaIYtNuTuFUPndr2W 8P6lw51VxCD279uzekiNzZuOmws7xOcU4Gdr3dSvOGqyzcBXpeLnvAJYX+pWInYlHIw8 Z18aiSMk6Pz7p1NBqsgGBxllOnMwSM5r4lsPjaaS4Xtw51GaDDtS7SkE3V3Mhh+vAQZs n1eA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=dmi170l6; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4kHq3rEP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id ef7-20020a056a002c8700b00690bdd08026si26970055pfb.251.2023.10.02.10.41.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 10:41:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=dmi170l6; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=4kHq3rEP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 433C3806A62A; Mon, 2 Oct 2023 05:01:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236905AbjJBMAi (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236954AbjJBMAX (ORCPT ); Mon, 2 Oct 2023 08:00:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D609D3 for ; Mon, 2 Oct 2023 04:59:58 -0700 (PDT) Message-ID: <20231002115903.087472735@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=J0zNjtrmxlOZ3cIxLGlZizAd9pmzXfVNcRvGruLfMIs=; b=dmi170l6gBazhbvWrscBAf9pb+pU6+AiWqYuoLqZYCH4SdmD2NKvKcbTc4BR3oc9VLhBgt qK8gaS3B8MsW0UCiCYql/QOfVeAf/b/o66zfEyOfBiG0bo+Ti5AFNmJYzQjE2E2566+t6a 7lzzxZL6+MbxVIV+1qlsay1mPfZdZ8puiadZSeyH7YCBbUPmkv10nmgvaFnicNScVCCgvr jvy0ZMf5+b7Ikh63hHvOeeJs7jC4loYZC49YfVc08+qcoMaOpQzWPNi9fbW/5YL7hJYZHQ 1WP2ALrwmofcwvSBoMzHw8ntHqT5aKlKSdl9CSmusX8OjAW7lbp4C5H04ipYTw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247996; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=J0zNjtrmxlOZ3cIxLGlZizAd9pmzXfVNcRvGruLfMIs=; b=4kHq3rEPUygP1oZu6plB0wbNvgIPljh4xMKiA+rVR9ZPliH4mp9PkgBPHsUueEraPFYNaV 2g1Tv57piCjW52Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 18/30] x86/microcode: Handle "nosmt" correctly References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:56 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778666451136961211 X-GMAIL-MSGID: 1778666451136961211 From: Thomas Gleixner On CPUs where microcode loading is not NMI safe the SMT siblings which are parked in one of the play_dead() variants still react on NMIs. So if a NMI hits while the primary thread updates the microcode the resulting behaviour is undefined. The default play_dead() implementation on modern CPUs is using MWAIT, which is not guaranteed to be safe against a microcode update which affects MWAIT. Take the cpus_booted_once_mask into account to detect this case and refuse to load late if the vendor specific driver does not advertise that late loading is NMI safe. AMD stated that this is safe, so mark the AMD driver accordingly. This requirement will be partially lifted in later changes. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 2 - arch/x86/kernel/cpu/microcode/amd.c | 9 +++-- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------ arch/x86/kernel/cpu/microcode/internal.h | 13 +++---- 4 files changed, 44 insertions(+), 31 deletions(-) --- --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1316,7 +1316,7 @@ config MICROCODE config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n - depends on MICROCODE + depends on MICROCODE && SMP help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -909,10 +909,11 @@ static void microcode_fini_cpu_amd(int c } static struct microcode_ops microcode_amd_ops = { - .request_microcode_fw = request_microcode_amd, - .collect_cpu_info = collect_cpu_info_amd, - .apply_microcode = apply_microcode_amd, - .microcode_fini_cpu = microcode_fini_cpu_amd, + .request_microcode_fw = request_microcode_amd, + .collect_cpu_info = collect_cpu_info_amd, + .apply_microcode = apply_microcode_amd, + .microcode_fini_cpu = microcode_fini_cpu_amd, + .nmi_safe = true, }; struct microcode_ops * __init init_amd_microcode(void) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -283,23 +283,6 @@ static struct platform_device *microcode */ #define SPINUNIT 100 /* 100 nsec */ -static int check_online_cpus(void) -{ - unsigned int cpu; - - /* - * Make sure all CPUs are online. It's fine for SMT to be disabled if - * all the primary threads are still online. - */ - for_each_present_cpu(cpu) { - if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { - pr_err("Not all CPUs online, aborting microcode update.\n"); - return -EINVAL; - } - } - - return 0; -} static atomic_t late_cpus_in; static atomic_t late_cpus_out; @@ -416,6 +399,35 @@ static int microcode_reload_late(void) return ret; } +/* + * Ensure that all required CPUs which are present and have been booted + * once are online. + * + * To pass this check, all primary threads must be online. + * + * If the microcode load is not safe against NMI then all SMT threads + * must be online as well because they still react on NMI when they are + * soft-offlined and parked in one of the play_dead() variants. So if a + * NMI hits while the primary thread updates the microcode the resulting + * behaviour is undefined. The default play_dead() implementation on + * modern CPUs uses MWAIT, which is also not guaranteed to be safe + * against a microcode update which affects MWAIT. + */ +static bool ensure_cpus_are_online(void) +{ + unsigned int cpu; + + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + if (!cpu_online(cpu)) { + if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { + pr_err("CPU %u not online\n", cpu); + return false; + } + } + } + return true; +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) @@ -431,9 +443,10 @@ static ssize_t reload_store(struct devic cpus_read_lock(); - ret = check_online_cpus(); - if (ret) + if (!ensure_cpus_are_online()) { + ret = -EBUSY; goto put; + } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -20,18 +20,17 @@ enum ucode_state { struct microcode_ops { enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); - void (*microcode_fini_cpu)(int cpu); /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. + * The generic 'microcode_core' part guarantees that the callbacks + * below run on a target CPU when they are being called. * See also the "Synchronization" section in microcode_core.c. */ - enum ucode_state (*apply_microcode)(int cpu); - int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); - void (*finalize_late_load)(int result); + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); + unsigned int nmi_safe : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Mon Oct 2 11:59:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147302 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1443810vqb; Mon, 2 Oct 2023 06:57:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOcQrfEG4yv+wPeT/ImFqYJqeFCFVyyt0bAOdjUP3QKXNkOHuN9I8ShDzmDDh+sgZJBDKa X-Received: by 2002:a17:902:dac8:b0:1bf:1a9e:85f7 with SMTP id q8-20020a170902dac800b001bf1a9e85f7mr13688157plx.1.1696255065367; Mon, 02 Oct 2023 06:57:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696255065; cv=none; d=google.com; s=arc-20160816; b=ZnCK2tgvYtXLyQnpcCSwTCBIGuFsPDIYrB42Qai+yx9HBhGU9CtqRnY1DV4M4P2Qli tI3WS6gqoLjBPpQLHJHeJfoMhGGwUY+zg9HD3M+lU2cJHkFnQScfRQB0VVTa2duaHOOF FQ8NNzQWxH78lbzohsqj7ueFggOHV8ny6M6PacnrLbDB83yGD7724k1aHSzNFevhP2lA 1pMHt3MKXE/+jM5Lv3KZdiY/h7/Ca+ozkkgU/X7VwEQHQ4K5ro3dgbUCaJUOZ3Xo1aSd M73vlolFNLzBBhrB7RzZrzy2JiHEPCyO3ZcsaPBJgfOjfH7SUkX3arpjF0+QJKm89iNe dRHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=AKE/XS6SEIbqho91Hmin0oksrMtPi1Xkc5zYgAfFhzQ=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=YL0//M8ceXBZH+eYuZSg/aTGU7p978mLTHaU0Y1Q2apGvZgmKONigXaukfrFGrXFZz D3uwtzrtngzQrkfaPAKSG6Ozf0YSuwXQMbfpGe3HGGPcZdv4rG+m4NRvF5/HwCLoMR+K DOSt0aMimfApFtAKLM9SrdjNwCE8TgstV7JnFQqvK7sTkLCRTVSboYZQvjB2j3KOt6Dw +DYDXn7dmk8rPc0UIPmk7RmcK/dun3vi7PamWEMt99vZLSNj/cYHpjRFjii92d0Q3ySH BjxDh6uY9va+JWX1dq6aDmOd/zBLE126LNfVnd9QlP3Zs4X4LVlbWFn1zK70WwwWc6KP ocBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=onKOuI3K; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=ag8vZTbF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id lq13-20020a170903144d00b001b9fb1a0465si24844388plb.385.2023.10.02.06.57.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 06:57:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=onKOuI3K; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=ag8vZTbF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 48549810C2E4; Mon, 2 Oct 2023 05:00:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236981AbjJBMAm (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236915AbjJBMAX (ORCPT ); Mon, 2 Oct 2023 08:00:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5FE71E3 for ; Mon, 2 Oct 2023 04:59:59 -0700 (PDT) Message-ID: <20231002115903.145048840@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247998; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AKE/XS6SEIbqho91Hmin0oksrMtPi1Xkc5zYgAfFhzQ=; b=onKOuI3KLeunKNft9ejU67gHNGLSwK0diHMkh49crfc162JLJuX/jFLh/QdbHI/WqAZDoA fNYeninSONC1fv6Xg73oTNdA5fqv4scX9rAPgqjoEVcmKELWeLiLSGqM0qcID7mMI3Fe9T 9GkEpXp0hTx9HCs6qijlCRy9qiQmAru+HVNwOgk4iaAa0g8lomv1G/8nutRLZvY/lBn9Px vqAz8/jwn2tyKZo/IDwjjOvQtcTz6IqwdE4yTHBfTlIT703c9IONKN0DmVWeax0x3pLtdq Ja1MOtc2GNJ+QR6/EYE7GbRHQaBnRWC3kwHYDuDZSgot0CqYX3DAP11EZo9KMw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247998; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AKE/XS6SEIbqho91Hmin0oksrMtPi1Xkc5zYgAfFhzQ=; b=ag8vZTbFFEGB9v4EDRB9E+KijGSPy2iC083XmbmRZFXl4zOqMomeo56sRzwNBytrOUODoT RPdU92cAESVk0JCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 19/30] x86/microcode: Clarify the late load logic References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:57 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:00:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778652351422059088 X-GMAIL-MSGID: 1778652351422059088 From: Thomas Gleixner reload_store() is way too complicated. Split the inner workings out and make the following enhancements: - Taint the kernel only when the microcode was actually updated. If. e.g. the rendevouz fails, then nothing happened and there is no reason for tainting. - Return useful error codes Signed-off-by: Thomas Gleixner Reviewed-by: Nikolay Borisov --- arch/x86/kernel/cpu/microcode/core.c | 41 ++++++++++++++++------------------- 1 file changed, 19 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -391,11 +391,11 @@ static int microcode_reload_late(void) pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); microcode_check(&prev_info); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); } else { pr_info("Reload failed, current microcode revision: 0x%x\n", boot_cpu_data.microcode); } - return ret; } @@ -428,40 +428,37 @@ static bool ensure_cpus_are_online(void) return true; } +static int ucode_load_late_locked(void) +{ + if (!ensure_cpus_are_online()) + return -EBUSY; + + switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { + case UCODE_NEW: + return microcode_reload_late(); + case UCODE_NFOUND: + return -ENOENT; + default: + return -EBADFD; + } +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { - enum ucode_state tmp_ret = UCODE_OK; - int bsp = boot_cpu_data.cpu_index; unsigned long val; - ssize_t ret = 0; + ssize_t ret; ret = kstrtoul(buf, 0, &val); if (ret || val != 1) return -EINVAL; cpus_read_lock(); - - if (!ensure_cpus_are_online()) { - ret = -EBUSY; - goto put; - } - - tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); - if (tmp_ret != UCODE_NEW) - goto put; - - ret = microcode_reload_late(); -put: + ret = ucode_load_late_locked(); cpus_read_unlock(); - if (ret == 0) - ret = size; - - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - - return ret; + return ret ? : size; } static DEVICE_ATTR_WO(reload); From patchwork Mon Oct 2 11:59:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147494 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1712508vqb; Mon, 2 Oct 2023 14:58:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEzqDrBGEnsPkTVk5YCqRrSGBNPiT3EUEKgs7NB0hcoVqZDZOM8StWgBUYSxo1DwjNe6+qa X-Received: by 2002:a05:6830:33cd:b0:6c4:7516:f2cf with SMTP id q13-20020a05683033cd00b006c47516f2cfmr13314477ott.2.1696283916860; Mon, 02 Oct 2023 14:58:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696283916; cv=none; d=google.com; s=arc-20160816; b=g0Fnj0NXtZdBM+ZhK1IS27Pe9y9SZ3+TMF1SLxGKaouwVDKVKlvCqk1DlkVfAOHSZB axleqj/lt4K0hI0HgsWvf6rDA3NMuZnLZUN/NJ60/xiCFvEYSApn/JanEco5aPc7KJnV owTPwmyyADeKXZZ8eC6/a2irQ8i6Jpt0AEv9d/2KfzVFqDh53NgzZfW8jkRRHrLRpC7f jw6+x++pyuRa3r0QDcCw9seKO0plEOSlg5STM67cTizY6qz5I6djIjQuIgmy/sq6fiVS UH+cVRmw2BHNuIi4GEF0/4ZpwZV6/wLuJZaadlbZ9YuWsqD5G5RWmlIKSG9/MUD5bk6e b6ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=GB4YWv4rtaFx36R21sEFu25/AV6Nske0fJrPY0aBq78=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=HxPNN9Q6FuE19q5zWFEIjaDxL0TDGrRxkmMms7EDDVP3o+A9rLrO1shN5IND1YRMIX xt1Rx2hldgaxE5nKKgLHn2gkysvuEebbM55maM93EAQfMRJgSyyJ2xuCSiwsgbhRB1ae /VzsAd8kEVAz7TvDNjInMxbe3kkfL0fn6Ls6E8pbZZ8HWyeeZh5pN92+kvOLkiiEYhff 3aJPp3Eu6XzsP6kINpWxaKyKjW2gDzB9mMdgwj2QnOBTiIwRmSwGAzyM2egAJPiHOR+3 TccwkOHB9rChbXNj71d26HoyeIyFXYNKENjuNPh8qwcyh1Dp+ljRHq4Hum15WWu8GTO9 7iag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=j0hwbKEq; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id c128-20020a633586000000b00578f7063adasi16854122pga.33.2023.10.02.14.58.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 14:58:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=j0hwbKEq; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 07E06810C2E5; Mon, 2 Oct 2023 05:01:02 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236979AbjJBMAr (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236968AbjJBMAX (ORCPT ); Mon, 2 Oct 2023 08:00:23 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FFA3FE for ; Mon, 2 Oct 2023 05:00:00 -0700 (PDT) Message-ID: <20231002115903.204251527@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696247999; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GB4YWv4rtaFx36R21sEFu25/AV6Nske0fJrPY0aBq78=; b=j0hwbKEqTNeguQXWS6kkYTIhBz8qjbxkqYcU9mtwAhjwNJUTRM/noc03rAXjYI6ydMtNeG UqUDouPVRZGLQEzaq+tE4BWjx5bbsWkKZA+da6JT3i2APVv2LEQQdLcV6YsS9b3sJv70x3 l3qeSFqbGz6fhgZ/ZEBoeMI1ruIWZZvVrKtU9OBT9vxfubu2x2XCzORwu0hFmv7E2K8tdo Utgk0eZA6Pbag4YXIefo+DjmZYNGd4yM/srVRmjVW3Vtv7I8VPS9cjB+lheIqOWYABydC/ IMsmsJan9TV8mmIevyw0yWwuLpOuzqx0bC3aniSABA4LK6mO/Kh87PJYHsXlCQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696247999; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=GB4YWv4rtaFx36R21sEFu25/AV6Nske0fJrPY0aBq78=; b=Kn0ZRuKqoslqTiylEu2PHyjDxd1mPxSP/FHSMcNaOB87SxClTKPuukXjyTk7MuExTYFTpK XfvkSYIaaljz3VBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 20/30] x86/microcode: Sanitize __wait_for_cpus() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 13:59:59 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:02 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778682604871258347 X-GMAIL-MSGID: 1778682604871258347 From: Thomas Gleixner The code is too complicated for no reason: - The return value is pointless as this is a strict boolean. - It's way simpler to count down from num_online_cpus() and check for zero. - The timeout argument is pointless as this is always one second. - Touching the NMI watchdog every 100ns does not make any sense, neither does checking every 100ns. This is really not a hotpath operation. Preload the atomic counter with the number of online CPUs and simplify the whole timeout logic. Delay for one microsecond and touch the NMI watchdog once per millisecond. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -281,31 +281,26 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ -#define SPINUNIT 100 /* 100 nsec */ +static atomic_t late_cpus_in, late_cpus_out; - -static atomic_t late_cpus_in; -static atomic_t late_cpus_out; - -static int __wait_for_cpus(atomic_t *t, long long timeout) +static bool wait_for_cpus(atomic_t *cnt) { - int all_cpus = num_online_cpus(); + unsigned int timeout; - atomic_inc(t); + WARN_ON_ONCE(atomic_dec_return(cnt) < 0); - while (atomic_read(t) < all_cpus) { - if (timeout < SPINUNIT) { - pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", - all_cpus - atomic_read(t)); - return 1; - } + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (!atomic_read(cnt)) + return true; - ndelay(SPINUNIT); - timeout -= SPINUNIT; + udelay(1); - touch_nmi_watchdog(); + if (!(timeout % USEC_PER_MSEC)) + touch_nmi_watchdog(); } - return 0; + /* Prevent the late comers from making progress and let them time out */ + atomic_inc(cnt); + return false; } /* @@ -323,7 +318,7 @@ static int __reload_late(void *info) * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_in)) return -1; /* @@ -346,7 +341,7 @@ static int __reload_late(void *info) } wait_for_siblings: - if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_out)) panic("Timeout during microcode update!\n"); /* @@ -373,8 +368,8 @@ static int microcode_reload_late(void) pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); - atomic_set(&late_cpus_out, 0); + atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Mon Oct 2 12:00:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1415850vqb; Mon, 2 Oct 2023 06:11:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGHzL+IuE8A5raYmaQH7Zb6NOR86A9tY8uk8JqCxn9042LYoPcLrfRa0jVTmcNi0yqpAYxl X-Received: by 2002:a05:6a20:cea5:b0:13f:8153:7e31 with SMTP id if37-20020a056a20cea500b0013f81537e31mr8686498pzb.20.1696252285572; Mon, 02 Oct 2023 06:11:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696252285; cv=none; d=google.com; s=arc-20160816; b=CWlBHPoIMlQuWGhOPeFd4NaxhPy2oq9PtUhq4+uQAdhNiMZp1Ybh22Qke/36N32O1H CMM55+L3bDEkm/iNM93TtVaRh8KC9RvC7OhZdobjC606fpYuPfAmKSccYoWtop4ySFC4 rte5tmmLu8lB4yy88ej3rhFo2/Up5Js2ON64nsf5Ru/Fhk3J/JFNjwbyJYrkPKOj0XT2 nK6wVtHGPRK/qFWPSosVmSuoVv9dJXXNJfCa1hZF7y0pKtU183ldPWQJSO+0w6zMoNLH XHfdTtnCq4Rz21/d/f6JmroJX1OhyXD8etEiSiRWNGYYet7bKDI1XWltYdmQqBjhwTnh /4kw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=UeM0gcDdtu4Q5hOuXaPXZf9xAZkloT57pR5hJH36+Rc=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=I1+M1z8Dwgn3cKZreidbgb6laJk9YvfBPF6jtenZwOEnylWqhFEuvMBWLCJb7vSL+N AlHguGZ3m8i+QipwS5gCmj4sIl6biMMt8gGkbbdgBi1ct/0Dj360VMFC217iaVT0WSrO H06YTFRF8hWfqQOqqOmlj2qL/OnJieUgZoYCB/0JHd/f1MoyQBpMzpC1Li9UQqdd/Av+ IeCFnWNGr5lQRYcJPIiUvWfWKLTVxl2LUvA95HELEeUB24rQGozA1tMaZ01tybK9npPy 484UJjAeaqIz7/mCsBXQkj5wJY3qjjbmsnHwb+H7/PDf+SA+vM8hjM0rgft95W7MfgGA S2TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gyoomB8v; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id y33-20020a056a001ca100b006901f2f2577si26635291pfw.380.2023.10.02.06.11.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 06:11:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gyoomB8v; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 7F3BC8047557; Mon, 2 Oct 2023 05:01:14 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236993AbjJBMAt (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236930AbjJBMAY (ORCPT ); Mon, 2 Oct 2023 08:00:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27FECE2 for ; Mon, 2 Oct 2023 05:00:01 -0700 (PDT) Message-ID: <20231002115903.262232260@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248000; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UeM0gcDdtu4Q5hOuXaPXZf9xAZkloT57pR5hJH36+Rc=; b=gyoomB8v9yabLuugTqV7UwkLzKxpy1ov0uqx7ak5dgTt15CA1w4mCV8dTmxyUAIydaklkc aiImilkXe6dfcsoMdpshfLbGYob7/d0vpOwrRF0ULT4I3Ys1IaVil8CT7vZ6lfuyFsDHmo KWyCDbMFHIrJvN108d5rOL4h2mis8+IHUGK6UiaIjueDUnM2OThRsqmCMyE8EeMhI1/w3P WC2vg9ntcr0TS85Kuwem810cY01eOC42G3bh39Kwe6szsLGBdTSvDRc2rj32dYvqXI4WgL RFBRkj80NgpbIvnTAx5jpxTcFfbCePm7lFm9m9ozA/3Wt2KyeVFMTqtoA47r0g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248000; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=UeM0gcDdtu4Q5hOuXaPXZf9xAZkloT57pR5hJH36+Rc=; b=SV32byAJsV8WRpZ3dg1PKJ64cQnSshlQggUX3HSFrvr50GoHgDLUDkYvp5v9GKSg3Hln+h vQjek7ipJwgkcHCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 21/30] x86/microcode: Add per CPU result state References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:00 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:14 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778649436943919241 X-GMAIL-MSGID: 1778649436943919241 From: Thomas Gleixner The microcode rendevouz is purely acting on global state, which does not allow to analyze fails in a coherent way. Introduce per CPU state where the results are written into, which allows to analyze the return codes of the individual CPUs. Initialize the state when walking the cpu_present_mask in the online check to avoid another for_each_cpu() loop. Enhance the result print out with that. The structure is intentionally named ucode_ctrl as it will gain control fields in subsequent changes. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 112 ++++++++++++++++++------------- arch/x86/kernel/cpu/microcode/internal.h | 1 2 files changed, 67 insertions(+), 46 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -281,6 +281,11 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +struct microcode_ctrl { + enum ucode_state result; +}; + +static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, late_cpus_out; static bool wait_for_cpus(atomic_t *cnt) @@ -303,23 +308,19 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } -/* - * Returns: - * < 0 - on error - * 0 - success (no update done or microcode was updated) - */ -static int __reload_late(void *info) +static int load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); - enum ucode_state err; - int ret = 0; + enum ucode_state ret; /* * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (!wait_for_cpus(&late_cpus_in)) - return -1; + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return 0; + } /* * On an SMT system, it suffices to load the microcode on one sibling of @@ -328,17 +329,11 @@ static int __reload_late(void *info) * loading attempts happen on multiple threads of an SMT core. See * below. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - err = microcode_ops->apply_microcode(cpu); - else + if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) goto wait_for_siblings; - if (err >= UCODE_NFOUND) { - if (err == UCODE_ERROR) { - pr_warn("Error reloading microcode on CPU %d\n", cpu); - ret = -1; - } - } + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); wait_for_siblings: if (!wait_for_cpus(&late_cpus_out)) @@ -350,19 +345,18 @@ static int __reload_late(void *info) * per-cpu cpuinfo can be updated with right microcode * revision. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - err = microcode_ops->apply_microcode(cpu); + if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) + return 0; - return ret; + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + return 0; } -/* - * Reload microcode late on all CPUs. Wait for a sec until they - * all gather together. - */ -static int microcode_reload_late(void) +static int load_late_stop_cpus(void) { - int old = boot_cpu_data.microcode, ret; + unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); @@ -377,26 +371,47 @@ static int microcode_reload_late(void) */ store_cpu_caps(&prev_info); - ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + + /* Analyze the results */ + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + switch (per_cpu(ucode_ctrl.result, cpu)) { + case UCODE_UPDATED: updated++; break; + case UCODE_TIMEOUT: timedout++; break; + case UCODE_OK: siblings++; break; + default: failed++; break; + } + } if (microcode_ops->finalize_late_load) - microcode_ops->finalize_late_load(ret); + microcode_ops->finalize_late_load(!updated); - if (!ret) { - pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); - microcode_check(&prev_info); - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - } else { - pr_info("Reload failed, current microcode revision: 0x%x\n", - boot_cpu_data.microcode); + if (!updated) { + /* Nothing changed. */ + if (!failed && !timedout) + return 0; + pr_err("update failed: %u CPUs failed %u CPUs timed out\n", + failed, timedout); + return -EIO; } - return ret; + + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("load: updated on %u primary CPUs with %u siblings\n", updated, siblings); + if (failed || timedout) { + pr_err("load incomplete. %u CPUs timed out or failed\n", + num_online_cpus() - (updated + siblings)); + } + pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); + microcode_check(&prev_info); + + return updated + siblings == num_online_cpus() ? 0 : -EIO; } /* - * Ensure that all required CPUs which are present and have been booted - * once are online. + * This function does two things: + * + * 1) Ensure that all required CPUs which are present and have been booted + * once are online. * * To pass this check, all primary threads must be online. * @@ -407,9 +422,12 @@ static int microcode_reload_late(void) * behaviour is undefined. The default play_dead() implementation on * modern CPUs uses MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. + * + * 2) Initialize the per CPU control structure */ -static bool ensure_cpus_are_online(void) +static bool setup_cpus(void) { + struct microcode_ctrl ctrl = { .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -419,18 +437,20 @@ static bool ensure_cpus_are_online(void) return false; } } + /* Initialize the per CPU state */ + per_cpu(ucode_ctrl, cpu) = ctrl; } return true; } -static int ucode_load_late_locked(void) +static int load_late_locked(void) { - if (!ensure_cpus_are_online()) + if (!setup_cpus()) return -EBUSY; switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return microcode_reload_late(); + return load_late_stop_cpus(); case UCODE_NFOUND: return -ENOENT; default: @@ -450,7 +470,7 @@ static ssize_t reload_store(struct devic return -EINVAL; cpus_read_lock(); - ret = ucode_load_late_locked(); + ret = load_late_locked(); cpus_read_unlock(); return ret ? : size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -16,6 +16,7 @@ enum ucode_state { UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, + UCODE_TIMEOUT, }; struct microcode_ops { From patchwork Mon Oct 2 12:00:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147521 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1721524vqb; Mon, 2 Oct 2023 15:16:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEr+xXEfZmiD9bw0Sn8xoFbh7HeXwsOLk8kJg0vWgEqSqRdY7KBboCS+EU9EE+kYhWfzPiF X-Received: by 2002:a05:6a20:9746:b0:157:609f:6057 with SMTP id hs6-20020a056a20974600b00157609f6057mr10373997pzc.27.1696284966811; Mon, 02 Oct 2023 15:16:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284966; cv=none; d=google.com; s=arc-20160816; b=JYDHtd6cR3hTPXuhIe1EUIi1GSM9fxM5aEcOE8GG7jAP7FgopPUqL4KSrc6FKcEp2I Fcq+W7BRmERjptjwWFI5TENsVMkvK7pdjOer3YsuiI0ivOXtrapdLixbJ/JjqpHWej+9 B4qQZ1h0blB8AzFHwm9/SznzECFnX2IwxIBTRdZ5AL8X7DxKN7ho7LjiqMzUUJXndcQ5 PwsJKBvjP3fGE+3BX9CpfuGpDvHmSVaV4G3NnXMucbmuQ/JQzhoGkXqQETyprPMbdw7I Kynrp0QTHJzsTonxuPr/xm8gK7Lwtju5h6LaWY+zYhMzzBjheK89gPFvWUNSC3QvWeFA 9UKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=wKKYiTE48a7OwEb1vlvH36sR8XqCrTrFsE1Q8U0VLR4=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=xvxp7XzDo7H7j1Gb+Sqn9HgC5kY0h9o3arg8bAhT6bvmE76zZq40JIxIkStElqL4NI JtsmBnI2aymaj0ZbGpxl1JEpouciHXehLdRVL6pnrzRq0PpepUa4oVGmJ+eqwNNX/enq Cqg1q08LcHw5djH/FGCukC13dNYR9fYqRNNeSfkxrzhHUVvif5EU1kXDGt1l6IRkmx2E F8qtwBaJhxZh2tQ6vWky3Xz8VGHTash/uemjm6VJ+0YjrO3573CI/ugK/oukdGQwM5Ui 9PHYab5Plyl+TW2Cw0i67KUW/SM2VrbmvRQvomjylRFUwiLdFqqzc7ms9pDSN67qAghf 3W4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IVjvQ16M; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=uWCOZ98b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id n13-20020a65488d000000b005777bea0b6asi27881278pgs.859.2023.10.02.15.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:16:06 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IVjvQ16M; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=uWCOZ98b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id A053781121D2; Mon, 2 Oct 2023 05:01:18 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236999AbjJBMAv (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236940AbjJBMAZ (ORCPT ); Mon, 2 Oct 2023 08:00:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 19230CEB for ; Mon, 2 Oct 2023 05:00:03 -0700 (PDT) Message-ID: <20231002115903.319959519@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248001; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wKKYiTE48a7OwEb1vlvH36sR8XqCrTrFsE1Q8U0VLR4=; b=IVjvQ16MNF8vUmza7Z3GeGDYlgJISJ9FX/IDbArQLQzy3j6fdQYZ8G1WU0FfAxbvG8zBBx XhYXx/fInBVJlcbFJYYWzTdkOYxzjaLOvBuLpPiG9/MNp7bqD+/2d5tb6oyPSWBmFyr+pP wolg9Y0/s/X+HdgAAJmIabFicBeHa2+zYoZBy0OUiWfpjnWQh44aJWK8OQl8sfvI9qNlXq a1wqW97jx2hkMyr9/Xf6yNY1jECuouiPlxFZEtYSwUDewuz84U5Xvz+6G1h9B8YVYQsWoC DmrETpReNvQgVtJfIIog0etQL35Lv4a3/MQTZYui4I8PolBE12nHUlu3N6YpTg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248001; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=wKKYiTE48a7OwEb1vlvH36sR8XqCrTrFsE1Q8U0VLR4=; b=uWCOZ98b8YS9Caz23vxnKKM0cXrwnhmjFwplYnzlXCKqxlPGM8/Tt4XKskQF9qr4xl3eRQ dXk9/uNpTNGvVNDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 22/30] x86/microcode: Add per CPU control field References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:01 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778683705325153100 X-GMAIL-MSGID: 1778683705325153100 From: Thomas Gleixner Add a per CPU control field to ucode_ctrl and define constants for it which are going to be used to control the loading state machine. In theory this could be a global control field, but a global control does not cover the following case: 15 primary CPUs load microcode successfully 1 primary CPU fails and returns with an error code With global control the sibling of the failed CPU would either try again or the whole operation would be aborted with the consequence that the 15 siblings do not invoke the apply path and end up with inconsistent software state. The result in dmesg would be inconsistent too. There are two additional fields added and initialized: ctrl_cpu and secondaries. ctrl_cpu is the CPU number of the primary thread for now, but with the upcoming uniform loading at package or system scope this will be one CPU per package or just one CPU. Secondaries hands the control CPU a CPU mask which will be required to release the secondary CPUs out of the wait loop. Preparatory change for implementing a properly split control flow for primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- V4: Simplify control CPU selection --- arch/x86/kernel/cpu/microcode/core.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -281,8 +281,19 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +enum sibling_ctrl { + /* Spinwait with timeout */ + SCTRL_WAIT, + /* Invoke the microcode_apply() callback */ + SCTRL_APPLY, + /* Proceed without invoking the microcode_apply() callback */ + SCTRL_DONE, +}; + struct microcode_ctrl { + enum sibling_ctrl ctrl; enum ucode_state result; + unsigned int ctrl_cpu; }; static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); @@ -427,7 +438,7 @@ static int load_late_stop_cpus(void) */ static bool setup_cpus(void) { - struct microcode_ctrl ctrl = { .result = -1, }; + struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -437,7 +448,12 @@ static bool setup_cpus(void) return false; } } - /* Initialize the per CPU state */ + + /* + * Initialize the per CPU state. This is core scope for now, + * but prepared to take package or system scope into account. + */ + ctrl.ctrl_cpu = cpumask_first(topology_sibling_cpumask(cpu)); per_cpu(ucode_ctrl, cpu) = ctrl; } return true; From patchwork Mon Oct 2 12:00:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1419816vqb; Mon, 2 Oct 2023 06:17:10 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGDRh6ned4WsZvgml3tiet6mblIFOpW4bVRUcqhCYUTaArhDnsYvoWoRPJQCw3oXWZMqN6V X-Received: by 2002:a17:90a:17a2:b0:277:2d7c:1be4 with SMTP id q31-20020a17090a17a200b002772d7c1be4mr10204891pja.1.1696252630367; Mon, 02 Oct 2023 06:17:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696252630; cv=none; d=google.com; s=arc-20160816; b=XLRDZ5NH2qD0ZYuHI3u56crMMjOuDFriPUxTFtRBJWsV4pkVFG0gD5feu5CYUgU8Ph +Ar73PqU8R3AJwuujBGwcziOxXossmUO92iDJhYwq21OkkzroE1q/xX2N4STi6pl8Wx2 a7VSm2UkMJUG0/nqbO7udW4iP3WLlnn1mEw01fiiirKEuQNG/5hHws4cttgkN3mgtC93 WlYgjWh56cnwY2mkiaiNyhnKcdTkbdKX8dUnIGPRbeVFcynOkFuF1INTXrxUp/fLbnfN URkrhUuMfFvSqnpoNnZXmPhfyjoi7XJeUkDEnoHp0NhVaZvanxVvCUATydVER9G1PCyv NXhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=p686dGKnLUGiOBuJ3ZmFJ4Qfbmz+TWkPBvmKkOJ7OCc=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=zpZ01quO9Q1Js1iZfrdAT/VWthU35Gc9JRKUwTVzN5RM9ibLRMYmHs5YuShO6VKZIo aImhAtU8IpZ7yhkDbYDulr9lTKNQWCMpDCw9kKIbAKtiwz/IHYIrX7E3qPO1KFPCtWeC FTQXQF/7AP4mto/zEcHSng5XRwM2j7nh9/HTbJ/zbgjX+Rm4buOYwq3t7MiAK3/IdLn8 IWZLydJn6ZPr8YMZBxbzSK68mkMh8ySIZRkr1nNBGwGge/+SvSlYYvs3NwFT/IKF7DRg ExxvthSngaJY1T+sT3HCip2TArgYSGOHxryiLiCivCRs2nbUtNSBUpr6iAdKMSkvJ8Ja SGhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SPqIhS1h; dkim=neutral (no key) header.i=@linutronix.de header.b=WmdkA0xp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id om13-20020a17090b3a8d00b002790b1320d4si8143330pjb.84.2023.10.02.06.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 06:17:10 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=SPqIhS1h; dkim=neutral (no key) header.i=@linutronix.de header.b=WmdkA0xp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 7882C807E937; Mon, 2 Oct 2023 05:01:29 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237003AbjJBMAy (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236983AbjJBMAZ (ORCPT ); Mon, 2 Oct 2023 08:00:25 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 97669CF3 for ; Mon, 2 Oct 2023 05:00:04 -0700 (PDT) Message-ID: <20231002115903.377922731@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=p686dGKnLUGiOBuJ3ZmFJ4Qfbmz+TWkPBvmKkOJ7OCc=; b=SPqIhS1hrgF2dkqtk/+E/F0nA3bJ4MDo+PwLvXGME2dgr7O8LbXe3/8abKLvmTN6fe1xHC K3hCNngS+/8ca/hRZOWgQPhOpm5Gq5UXia+eY5x4Ws3vIKhDpdTj9lNWmfaionaGBcXEqo K9KDHcVpvQBczZ8tr3WQ5ghm9TLctmpv+33X/FGXO2s9FpDAGv0G65r53hofeFP67OdSmH jiH/x9qtkRbE2S8JlqOBEtusSp3SsAfxz3NXrR5gN/q8CMahquCfkeB8uRFpxGbyabqzzB 3+SEDyr9cpK4wdHuyg7eZrpJnYoRG24A5QdvLcfvKWdN+JLEwq6JrtijlQxSmw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248002; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=p686dGKnLUGiOBuJ3ZmFJ4Qfbmz+TWkPBvmKkOJ7OCc=; b=WmdkA0xpYnMj5C2a8Q91uUzS8bCPoIvxADv7s9Fh2OTUIEa85bY2tcN1Zr7Ja3Vqt8GnN+ gWeq3LxnSWCMeXCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 23/30] x86/microcode: Provide new control functions References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:02 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778649797995562767 X-GMAIL-MSGID: 1778649797995562767 From: Thomas Gleixner The current all in one code is unreadable and really not suited for adding future features like uniform loading with package or system scope. Provide a set of new control functions which split the handling of the primary and secondary CPUs. These will replace the current rendezvouz all in one function in the next step. This is intentionally a separate change because diff makes an complete unreadable mess otherwise. So the flow separates the primary and the secondary CPUs into their own functions, which use the control field in the per CPU ucode_ctrl struct. primary() secondary() wait_for_all() wait_for_all() apply_ucode() wait_for_release() release() apply_ucode() Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 84 +++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -319,6 +319,90 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } +static bool wait_for_ctrl(void) +{ + unsigned int timeout; + + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); + } + return false; +} + +static __maybe_unused void load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + /* Initial rendezvouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return; + } + + /* + * Wait for primary threads to complete. If one of them hangs due + * to the update, there is no way out. This is non-recoverable + * because the CPU might hold locks or resources and confuse the + * scheduler, watchdogs etc. There is no way to safely evacuate the + * machine. + */ + if (!wait_for_ctrl()) + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + + /* + * If the primary succeeded then invoke the apply() callback, + * otherwise copy the state from the primary thread. + */ + if (this_cpu_read(ucode_ctrl.ctrl) == SCTRL_APPLY) + ret = microcode_ops->apply_microcode(cpu); + else + ret = per_cpu(ucode_ctrl.result, ctrl_cpu); + + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); +} + +static __maybe_unused void load_primary(unsigned int cpu) +{ + struct cpumask *secondaries = topology_sibling_cpumask(cpu); + enum sibling_ctrl ctrl; + enum ucode_state ret; + unsigned int sibling; + + /* Initial rendezvouz to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + return; + } + + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + + /* + * If the update was successful, let the siblings run the apply() + * callback. If not, tell them it's done. This also covers the + * case where the CPU has uniform loading at package or system + * scope implemented but does not advertise it. + */ + if (ret == UCODE_UPDATED || ret == UCODE_OK) + ctrl = SCTRL_APPLY; + else + ctrl = SCTRL_DONE; + + for_each_cpu(sibling, secondaries) { + if (sibling != cpu) + per_cpu(ucode_ctrl.ctrl, sibling) = ctrl; + } +} + static int load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); From patchwork Mon Oct 2 12:00:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147400 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1582872vqb; Mon, 2 Oct 2023 10:34:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIhJH6Rbyr2wSi6WUFkFdlASC9Rz30i24wBR0QwvHeVsvheniVbZoJc6kjM1Xa7rfzWP9F X-Received: by 2002:a05:6a20:96d3:b0:14d:6309:fc92 with SMTP id hq19-20020a056a2096d300b0014d6309fc92mr8545911pzc.46.1696268089969; Mon, 02 Oct 2023 10:34:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696268089; cv=none; d=google.com; s=arc-20160816; b=hd9POdzqNQonfo3vsI80F+eRw08LnC56M3Jqhx9gifxppX+pg8AQuGNPrkrChOxjD1 aU98scSJbPi+41dTZkrUCMocUfKnOszUcusMFo6N3Si1TEYsWzfx3ZXX5M3YEzlOVNIU oMJpm0gEVtLtLoXVzTYYQtPDhqOTn9zk9v64bWJgiKj/dsUHkl8OTCMvNqRlEzR4J4Sl nijr4aan2od/gBTFxBwVGMxAWhO5Akye59kuJsY4ieH013gIHP/N66Wfgq7gq87pEOgk aDM4AAGLiBUe6iJ4exujSt2AyHjovzh9oZuGKQg5NamPSwZKNhtv0x176H9QZeMjDbFE ZgUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=ieBuqQWksnZY/BH9wf5B9oj4Sl+Y6MDqsZ/PHThlnTM=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=qAVv6z6cBOxmNxv9nr0i8+/ntikZrqUptG0t/MZ+VhdMoM0JVkULhElQEOJ90tDTP1 W96xhXEXnXdEBRcYWVfOPGbWB5pvth9F+U0Nu9J+guGF7J9mdt/B/9hoQk2lhk56/pgA WZ5c0ETTWvtpQGaaGFIRn2YWuqz4f9ZYwnA+mInUtg+iDKj/tZYLW+hfQSOw0jlSuO5c palTcPENkXHeDDMnlKJBlXS8r0jHSiDLux0QuvJXYg2pDqfm8ltXYjAnEqgcxl4d00Pp F2mxP2igLEhrD99mlvK99yxcuvM3WzD/dQ9xLPC04Czy5rTgINwVs9g7yOwtT7iNDQF7 Ol9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Q4TE8q8l; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=jnpSpz9u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id ca6-20020a056a00418600b0068fb4842092si27481921pfb.183.2023.10.02.10.34.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 10:34:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Q4TE8q8l; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=jnpSpz9u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 6F82181121D7; Mon, 2 Oct 2023 05:01:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237021AbjJBMA5 (ORCPT + 18 others); Mon, 2 Oct 2023 08:00:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236914AbjJBMA0 (ORCPT ); Mon, 2 Oct 2023 08:00:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C3FACFC for ; Mon, 2 Oct 2023 05:00:05 -0700 (PDT) Message-ID: <20231002115903.433704135@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ieBuqQWksnZY/BH9wf5B9oj4Sl+Y6MDqsZ/PHThlnTM=; b=Q4TE8q8l5JiNVhzWFESeoJszo8+qdH8T7XjwskCMAqXgXL7Wgn2blSnXkFketydzCYoDch 36F1qFbJ1+B7zGqwVLuVHxT9yxJ92VlbDghmyq195VQpp6s4xnoEMc8/dr2s2htP/fptcb 3YT4r3pZ8Io1aoqmWJ7xW/0FheDMLo3Awdf+fCBbct9bL31SEQohk6f9tiUNGzXveCKw0E h2VhXlUXS/oTNhCDpBzdXCwRshugTmiTohWb+mz6u8Mnq4oZrX982YdaFAXalkAc3/n6hu /AhoCCtPVXcRyyMKLyh8foywn5+WM6R+KzkJyFNmDsOXTxWJW5ljsSPK5E8JRw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248004; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ieBuqQWksnZY/BH9wf5B9oj4Sl+Y6MDqsZ/PHThlnTM=; b=jnpSpz9uCWSbygDlUogcWaBQGJDOA45yddJGvbtunkIhhEPXQ64SvD5b1C704gPZrfgIM8 k1KwwGfTXiVMGvDA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 24/30] x86/microcode: Replace the all in one rendevouz handler References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:03 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778666008798720691 X-GMAIL-MSGID: 1778666008798720691 From: Thomas Gleixner with a new handler which just separates the control flow of primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 51 ++++++----------------------------- 1 file changed, 9 insertions(+), 42 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -297,7 +297,7 @@ struct microcode_ctrl { }; static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); -static atomic_t late_cpus_in, late_cpus_out; +static atomic_t late_cpus_in; static bool wait_for_cpus(atomic_t *cnt) { @@ -333,7 +333,7 @@ static bool wait_for_ctrl(void) return false; } -static __maybe_unused void load_secondary(unsigned int cpu) +static void load_secondary(unsigned int cpu) { unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); enum ucode_state ret; @@ -368,7 +368,7 @@ static __maybe_unused void load_secondar this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); } -static __maybe_unused void load_primary(unsigned int cpu) +static void load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -405,46 +405,14 @@ static __maybe_unused void load_primary( static int load_cpus_stopped(void *unused) { - int cpu = smp_processor_id(); - enum ucode_state ret; - - /* - * Wait for all CPUs to arrive. A load will not be attempted unless all - * CPUs show up. - * */ - if (!wait_for_cpus(&late_cpus_in)) { - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return 0; - } - - /* - * On an SMT system, it suffices to load the microcode on one sibling of - * the core because the microcode engine is shared between the threads. - * Synchronization still needs to take place so that no concurrent - * loading attempts happen on multiple threads of an SMT core. See - * below. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - goto wait_for_siblings; + unsigned int cpu = smp_processor_id(); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); - -wait_for_siblings: - if (!wait_for_cpus(&late_cpus_out)) - panic("Timeout during microcode update!\n"); - - /* - * At least one thread has completed update on each core. - * For others, simply call the update to make sure the - * per-cpu cpuinfo can be updated with right microcode - * revision. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - return 0; + if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + load_primary(cpu); + else + load_secondary(cpu); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); + /* No point to wait here. The CPUs will all wait in stop_machine(). */ return 0; } @@ -458,7 +426,6 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); - atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Mon Oct 2 12:00:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147287 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1416673vqb; Mon, 2 Oct 2023 06:12:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGKX2w5mSSIQsoen3HWabX2KJS7i/H1NseZ/DphzeIwy8aA2/5BqOItZIbDkB2aduZAQzz6 X-Received: by 2002:a9d:65c9:0:b0:6b9:b600:589 with SMTP id z9-20020a9d65c9000000b006b9b6000589mr10937403oth.15.1696252361459; Mon, 02 Oct 2023 06:12:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696252361; cv=none; d=google.com; s=arc-20160816; b=hBWSFH3WxUnUSb3TTxYsG2zJg4qvnnSe81qwcGrmi3vl2Vg7M8VyA2i4CV6yX0HPeM GUG01gwh+pV39eoIEfYNQyKXMCrSzH/T+kwbgfqSxvdchdQBleTWl0TO6WElSMb1DiN2 E3ly6gXaYIdMSQ7rFw8zV1EVQMTSCagvMtAmGUFJcBQhi+/PgUaqKSdnlDDXuzzVawMG DxQyJRklNKoFn95uBkV/xbd/t+cvq72ZaK75r26PSwlgSyXocBq2UaV8rMFhBQQQVNTe 5oWsTaGlNInRExH9EuxRaQYhEkmKBUHh7vRRbqL4rhF6f/SFaadV9gA5PtalqZlq/fdW DGsw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=8hntDVXvdbfrMrv3R4oy13cuwBY//aEeCSC8iMVq/cg=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=1JEFIaZHKXUZHOLd5piFdjsifOTciNgwNUes3QffGdNaOopn/rPCLRt3oi7Wq0LJFD 3LDUhpLS+ByoznF+qxwhioJ9JE1YvBWPTkbjiKw/SIpawysDtegI5/xlto3npJMWANfb n9peLX4Z+NVf22PTNwRgDz/JhaQLc5+AVROvZ8vguMgvzLQ2B3YR7kM1otraePXIMp8K ol5PwDiLgwMGRFz6jiBo1yA3eyMMHOFtkXoAGHcjti3bJ60cX6OkCBVz+BSer+fn2Qeg NeWdQG/KizMEKl2PKDZtpPbrKwN4dZvauxwrh2AK+pJvBq/R4GCGwkao3h+a02fDHQl7 B1Sw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=j1UdRNLK; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=o0UcQCf9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id l10-20020a65560a000000b00577f65baa3esi26475249pgs.775.2023.10.02.06.12.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 06:12:41 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=j1UdRNLK; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=o0UcQCf9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id EF06A8039879; Mon, 2 Oct 2023 05:01:38 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236898AbjJBMBA (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236953AbjJBMA0 (ORCPT ); Mon, 2 Oct 2023 08:00:26 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C7DD710C7 for ; Mon, 2 Oct 2023 05:00:06 -0700 (PDT) Message-ID: <20231002115903.489900814@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248005; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8hntDVXvdbfrMrv3R4oy13cuwBY//aEeCSC8iMVq/cg=; b=j1UdRNLK1BzsW8/YnZsbunhSovPs9xWF+qMh5by7nrG3qVyqBUEqvGgW/63Dsv40LyJg8/ mM6r9lCX5j3QPMwML5DLzfvi7o08Chjtj0UCazreAJP7/6wsBWwqO15awKq1t0fBGiSFAW KsyEVMXj7vECRuHJonQvjAiy0/20KZk/sfcbIY+0QAuW5gkGJwMpiKXPkmHtvHl/q7dZmQ d8U4k/vxPH9+aRymuQliBIb5thukLtXk9ay5a2+pU5quvXi+MDocKphUYDzG1EC6I901yD WSUa/oIHcG9YIt8RiZD4+fGuKrvy1EoePazSXnOd8goE8byR6ElAx70b+Fvx0Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248005; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8hntDVXvdbfrMrv3R4oy13cuwBY//aEeCSC8iMVq/cg=; b=o0UcQCf96Lr4FjTVJMozT4xtO11RnpwsSfO/yqwXmwXPs4BYCotXryB1HAvIvZzaYwVBFx hyrgHrNMy2ZMfXCg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 25/30] x86/microcode: Rendezvous and load in NMI References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:05 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:41 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778649516171008629 X-GMAIL-MSGID: 1778649516171008629 From: Thomas Gleixner stop_machine() does not prevent the spin-waiting sibling from handling an NMI, which is obviously violating the whole concept of rendezvous. Implement a static branch right in the beginning of the NMI handler which is NOOPed except when enabled by the late loading mechanism. The late loader enables the static branch before stop_machine() is invoked. Each CPU has an nmi_enable in its control structure which indicates whether the CPU should go into the update routine. This is required to bridge the gap between enabling the branch and actually being at the point where it is required to enter the loader wait loop. Each CPU which arrives in the stopper thread function sets that flag and issues a self NMI right after that. If the NMI function sees the flag clear, it returns. If it's set it clears the flag and enters the rendezvous. This is safe against a real NMI which hits in between setting the flag and sending the NMI to itself. The real NMI will be swallowed by the microcode update and the self NMI will then let stuff continue. Otherwise this would end up with a spurious NMI. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 12 ++++++++ arch/x86/kernel/cpu/microcode/core.c | 42 ++++++++++++++++++++++++++++--- arch/x86/kernel/cpu/microcode/intel.c | 1 arch/x86/kernel/cpu/microcode/internal.h | 3 +- arch/x86/kernel/nmi.c | 4 ++ 5 files changed, 57 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -70,4 +70,16 @@ static inline u32 intel_get_microcode_re } #endif /* !CONFIG_CPU_SUP_INTEL */ +bool microcode_nmi_handler(void); + +#ifdef CONFIG_MICROCODE_LATE_LOADING +DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); +static __always_inline bool microcode_nmi_handler_enabled(void) +{ + return static_branch_unlikely(µcode_nmi_handler_enable); +} +#else +static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } +#endif + #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include +#include #include #include #include @@ -294,8 +296,10 @@ struct microcode_ctrl { enum sibling_ctrl ctrl; enum ucode_state result; unsigned int ctrl_cpu; + bool nmi_enabled; }; +DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in; @@ -311,7 +315,8 @@ static bool wait_for_cpus(atomic_t *cnt) udelay(1); - if (!(timeout % USEC_PER_MSEC)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) touch_nmi_watchdog(); } /* Prevent the late comers from making progress and let them time out */ @@ -327,7 +332,8 @@ static bool wait_for_ctrl(void) if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } return false; @@ -403,7 +409,7 @@ static void load_primary(unsigned int cp } } -static int load_cpus_stopped(void *unused) +static bool microcode_update_handler(void) { unsigned int cpu = smp_processor_id(); @@ -412,7 +418,29 @@ static int load_cpus_stopped(void *unuse else load_secondary(cpu); - /* No point to wait here. The CPUs will all wait in stop_machine(). */ + touch_nmi_watchdog(); + return true; +} + +bool microcode_nmi_handler(void) +{ + if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + return false; + + this_cpu_write(ucode_ctrl.nmi_enabled, false); + return microcode_update_handler(); +} + +static int load_cpus_stopped(void *unused) +{ + if (microcode_ops->use_nmi) { + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + } else { + /* Just invoke the handler directly */ + microcode_update_handler(); + } return 0; } @@ -433,8 +461,14 @@ static int load_late_stop_cpus(void) */ store_cpu_caps(&prev_info); + if (microcode_ops->use_nmi) + static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + if (microcode_ops->use_nmi) + static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { switch (per_cpu(ucode_ctrl.result, cpu)) { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -601,6 +601,7 @@ static struct microcode_ops microcode_in .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, + .use_nmi = IS_ENABLED(CONFIG_X86_64), }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,7 +31,8 @@ struct microcode_ops { enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); - unsigned int nmi_safe : 1; + unsigned int nmi_safe : 1, + use_nmi : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -343,6 +344,9 @@ static noinstr void default_do_nmi(struc instrumentation_begin(); + if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) + goto out; + handled = nmi_handle(NMI_LOCAL, regs); __this_cpu_add(nmi_stats.normal, handled); if (handled) { From patchwork Mon Oct 2 12:00:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147409 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1599459vqb; Mon, 2 Oct 2023 11:04:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGT8DIts4emBXAgSyhIEZZKYBAb34VWJ70dy2+gR2/bi21gGdfPaNbwFsRsSeDDwAPqd44a X-Received: by 2002:a05:6a00:1f0f:b0:68f:b5a3:5ec6 with SMTP id be15-20020a056a001f0f00b0068fb5a35ec6mr466520pfb.0.1696269847590; Mon, 02 Oct 2023 11:04:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696269847; cv=none; d=google.com; s=arc-20160816; b=LfcR2/Pg9gbCS2y0B04MwYn3JtFiydqCj9c7u8DDOtS+uDjZmE+JiyHhuCFpJIjE0F wdA0lfYr6/AyL+72aUnA09Jmk0OB5h2OdyHfsfyLwQiVKsHbWa+WMz2v0ZRRVAEgPGRt xiyur8dHqA9fR6N0dY7q3Ak+u2DdPNEs5ABUsiSgqcxgX43I4gmVr/EDhqAe5CzClqx+ leHSjgnAbmRvqikYqO3FtVjlpPw8M2v4H1sJfYUyfjOSb6QkIV/HBhtkJrRRBcxH/m6/ 6ON0iHDi6iuthHUvtyXUWdHpP1iUf0nun4lJnLz2TweucezWstCT+O+EQQaWoXaeHU09 EcLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=BZYJfmyEkcEUrvO2SGy5jScmTWgbT5L9UgtF0YXKdoY=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=gT8O1v9p2wH9dGCbdhoYuCg6ZqEsV8tXXd8m1dBXUSjBMSYPsXIXK2hLukepWbXomD 0TeG8ML1lbkYPqSSaNaDC/3o8ZrognfOh8Tf8vGB9AZtMTcimJDMV23dPfixCsLGT6rH HWA5HDX16FuE+VEVvF/UdY2IBhWKIXuUeSHC9wyUzjRd48Xoodc2sdYyyCU4yytn3iBp N8qFY+33g/ALnmO0Ci3H+Q6B9Y17aDVAfkrpanN3VaquNVU1r4Y6CaU6Efp6LJOY5AlG h/QrUXLmBsUltYGVNudJY6ccRhT1IXiDHrehA2z5ypx9r7yeFwPzPhlRsZ2EWWoeQEq0 0VfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IF6PEv6o; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id ay42-20020a056a00302a00b0068c7033a5f5si27931427pfb.74.2023.10.02.11.04.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 11:04:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=IF6PEv6o; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9E7BC81121F8; Mon, 2 Oct 2023 05:02:15 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237001AbjJBMBI (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236955AbjJBMA1 (ORCPT ); Mon, 2 Oct 2023 08:00:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4411810D9 for ; Mon, 2 Oct 2023 05:00:08 -0700 (PDT) Message-ID: <20231002115903.545969323@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248006; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BZYJfmyEkcEUrvO2SGy5jScmTWgbT5L9UgtF0YXKdoY=; b=IF6PEv6oZJQwZyYqk/0hWecJqpLTSDyDZDHCr9F2Kh/jZ6wx3hjJyftauZ9oMUvT9yj2a2 tFOpzvN5VDhQuMsKlOL3MuUl5oaP1PjiDqP7EAqSODYA940lmCP+WixS20h2WH7qKP5Mkb xdeGJo3THpTHMbL/I0T+hU06tI0HBchN+JrIMoEZ8bfUb3iU66D1LPJI+5uyn7psSrjsF4 G3NxMSHOWubsUwTjWeoGaZ65AKIq7ZPmJ5r1peuYArOAhjswXLM9Rfhe3yWN1Hoi4v0gvb 6imh62cs3BQ4I+uaqbb4whdRVeeBwTKgvZ5Qb+UCUKgW0fSnp5buFR/ONGjIWQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248006; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=BZYJfmyEkcEUrvO2SGy5jScmTWgbT5L9UgtF0YXKdoY=; b=OZ5XG5hLbib6kqtcQi41zT0OPxlQJf20vlyyLoZ+Vt/glLTf++xmWdRRfI9elYcvbZDBZ7 LKb2psvzadyA2VDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 26/30] x86/microcode: Protect against instrumentation References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:06 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:02:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778667852013679379 X-GMAIL-MSGID: 1778667852013679379 From: Thomas Gleixner The wait for control loop in which the siblings are waiting for the microcode update on the primary thread must be protected against instrumentation as instrumentation can end up in #INT3, #DB or #PF, which then returns with IRET. That IRET reenables NMI which is the opposite of what the NMI rendezvouz is trying to achieve. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 110 ++++++++++++++++++++++++++--------- 1 file changed, 82 insertions(+), 28 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -301,54 +301,65 @@ struct microcode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); +static unsigned int loops_per_usec; static atomic_t late_cpus_in; -static bool wait_for_cpus(atomic_t *cnt) +static noinstr bool wait_for_cpus(atomic_t *cnt) { - unsigned int timeout; + unsigned int timeout, loops; - WARN_ON_ONCE(atomic_dec_return(cnt) < 0); + WARN_ON_ONCE(raw_atomic_dec_return(cnt) < 0); for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (!atomic_read(cnt)) + if (!raw_atomic_read(cnt)) return true; - udelay(1); + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } /* Prevent the late comers from making progress and let them time out */ - atomic_inc(cnt); + raw_atomic_inc(cnt); return false; } -static bool wait_for_ctrl(void) +static noinstr bool wait_for_ctrl(void) { - unsigned int timeout; + unsigned int timeout, loops; for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + if (raw_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } return false; } -static void load_secondary(unsigned int cpu) +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr bool load_secondary_wait(unsigned int ctrl_cpu) { - unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); - enum ucode_state ret; - /* Initial rendezvouz to ensure that all CPUs have arrived */ if (!wait_for_cpus(&late_cpus_in)) { - pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return; + raw_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return false; } /* @@ -358,9 +369,33 @@ static void load_secondary(unsigned int * scheduler, watchdogs etc. There is no way to safely evacuate the * machine. */ - if (!wait_for_ctrl()) - panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + if (wait_for_ctrl()) + return true; + + instrumentation_begin(); + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + instrumentation_end(); +} +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr void load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = raw_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + if (!load_secondary_wait(ctrl_cpu)) { + instrumentation_begin(); + pr_err_once("Microcode load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + instrumentation_end(); + return; + } + + /* Primary thread completed. Allow to invoke instrumentable code */ + instrumentation_begin(); /* * If the primary succeeded then invoke the apply() callback, * otherwise copy the state from the primary thread. @@ -372,6 +407,7 @@ static void load_secondary(unsigned int this_cpu_write(ucode_ctrl.result, ret); this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + instrumentation_end(); } static void load_primary(unsigned int cpu) @@ -409,25 +445,42 @@ static void load_primary(unsigned int cp } } -static bool microcode_update_handler(void) +static noinstr bool microcode_update_handler(void) { - unsigned int cpu = smp_processor_id(); + unsigned int cpu = raw_smp_processor_id(); - if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + if (raw_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) { + instrumentation_begin(); load_primary(cpu); - else + instrumentation_end(); + } else { load_secondary(cpu); + } + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); return true; } -bool microcode_nmi_handler(void) +/* + * Protection against instrumentation is required for CPUs which are not + * safe against an NMI which is delivered to the secondary SMT sibling + * while the primary thread updates the microcode. Instrumentation can end + * up in #INT3, #DB and #PF. The IRET from those exceptions reenables NMI + * which is the opposite of what the NMI rendevouz is trying to achieve. + * + * The primary thread is safe versus instrumentation as the actual + * microcode update handles this correctly. It's only the sibling code + * path which must be NMI safe until the primary thread completed the + * update. + */ +bool noinstr microcode_nmi_handler(void) { - if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) return false; - this_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.nmi_enabled, false); return microcode_update_handler(); } @@ -454,6 +507,7 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* * Take a snapshot before the microcode update in order to compare and From patchwork Mon Oct 2 12:00:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147271 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1393275vqb; Mon, 2 Oct 2023 05:34:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJIa1WccDEzN1SPwrHMBO33JkUJBJG6g8j9XN5UPS5nWUwtPzF43/bi9/jHjItwUVGuYDd X-Received: by 2002:a05:6a20:9385:b0:15a:13f3:49ca with SMTP id x5-20020a056a20938500b0015a13f349camr14806231pzh.9.1696250051497; Mon, 02 Oct 2023 05:34:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696250051; cv=none; d=google.com; s=arc-20160816; b=gFalsbvDkcmjH9GwF4YWamyvFWc1MteKuaJCy+zTd59ocr6d5R8exwEQpLKC4cUnXo Ox4YwLuYMMxB657LE1b1kBCWDSPiW6DUfKaaFyZyNjNh/3pOT1wiVp4fBvV2xzfBcqJh G4LdNbTm+ogS9M0HRRl6qBpybeJwALe9xEmLw8M+bwLak9wUDOj04WhhWtZ9yQs5oZ0n NixJLRVOUV3GGXhmDaOGx6MyGLTtxrarP+rWF2E7W8AUKidLsi1HtMYe8ZiCpBLj9iQe Lou73pW0Ze5hO7fT6xt/pshBKFj1EFIagczd6ukn3fQecz/Tab0wDorX+Z9gNEdzAoGU fytQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=5EsTuHLRMt+mh9/+wwjfJDEI240zRMwQu4qtcC7nL1o=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=nlozPnblPBWgM1jRJTCx1ZBT1u0xLir6UMTpkXdToTUh0iajCS0tIq/SK02whG10z2 Xj4baz0KOrX6ECJdfmWv9Y2mz9JMMLjpuKcYw3HrndAUdoo7RDJHl0O1nLpJSTZ3W9CJ euVh41o+eai3/IePmdgQt3MdxP4YVTZamCgormF5KHIvMzS2BIl70HI1FxzkMTDFjZmL dbqWOc9L5gBRvvOS++q2xffY3s02fHJGa2o5tohR6cOdzORQujKMW//CEbXgKlZlhGE1 mdU99soLiRJgj8OYzCAEse/mKs8k6gScADrXrM2f+Vgut0+6V9VUC69UnVOFfBXZGH3S JJfQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="qd/2H/aF"; dkim=neutral (no key) header.i=@linutronix.de header.b="ryCH/3Xg"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id j191-20020a6380c8000000b00573ff1f360bsi27336661pgd.479.2023.10.02.05.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 05:34:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="qd/2H/aF"; dkim=neutral (no key) header.i=@linutronix.de header.b="ryCH/3Xg"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id D7A7A8056995; Mon, 2 Oct 2023 05:01:36 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237029AbjJBMBE (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236913AbjJBMA1 (ORCPT ); Mon, 2 Oct 2023 08:00:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6006310DF for ; Mon, 2 Oct 2023 05:00:09 -0700 (PDT) Message-ID: <20231002115903.603100036@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248007; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5EsTuHLRMt+mh9/+wwjfJDEI240zRMwQu4qtcC7nL1o=; b=qd/2H/aFUJYfk8KibD6cLXHb5wEHvYX+MnYSKe/WS5NDDePcCyAY4LHkPjB7Z3vOc4ZLEe YwL3e61xl1Io+zXV4c49mtYPSCSgPsTKs1OgsieKcendVlcG8I8M/TA1orXwYltxMWbbPr dcRxzQkwCGV2bcOrGiQTOtynWbU9OwkziUh1P1tytFqDsoqGuwdBVgXyEkl08CLgUm6PsE fXFmmlN4GbmwpGEa0VvCNE1Fv8EaNGGNAIAWJrSnbbTU5vDxCBzySCoChTXy7nm+2JSGAz 6MAwQa2ZoJkdTRk6DJnotYdh4LEQNSURjVJFthThMzmhJijKhNs9W+/vVq8YAw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248007; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5EsTuHLRMt+mh9/+wwjfJDEI240zRMwQu4qtcC7nL1o=; b=ryCH/3XgkECu6G8UUOUuZ1zNz5hXCqWApEXN64Zbqbbn/wJywPUDwPctd4dIXEEB4fqprk bINwDxRREKmPcBCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 27/30] x86/apic: Provide apic_force_nmi_on_cpu() References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:07 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778647093604779153 X-GMAIL-MSGID: 1778647093604779153 From: Thomas Gleixner When SMT siblings are soft-offlined and parked in one of the play_dead() variants they still react on NMI, which is problematic on affected Intel CPUs. The default play_dead() variant uses MWAIT on modern CPUs, which is not guaranteed to be safe when updated concurrently. Right now late loading is prevented when not all SMT siblings are online, but as they still react on NMI, it is possible to bring them out of their park position into a trivial rendevouz handler. Provide a function which allows to do that. I does sanity checks whether the target is in the cpus_booted_once_mask and whether the APIC driver supports it. Mark X2APIC and XAPIC as capable, but exclude 32bit and the UV and NUMACHIP variants as that needs feedback from the relevant experts. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 ++++- arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/ipi.c | 8 ++++++++ arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + 5 files changed, 16 insertions(+), 1 deletion(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -276,7 +276,8 @@ struct apic { u32 disable_esr : 1, dest_mode_logical : 1, - x2apic_set_max_apicid : 1; + x2apic_set_max_apicid : 1, + nmi_to_offline_cpu : 1; u32 (*calc_dest_apicid)(unsigned int cpu); @@ -542,6 +543,8 @@ extern bool default_check_apicid_used(ph extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); extern int default_cpu_present_to_apicid(int mps_cpu); +void apic_send_nmi_to_offline_cpu(unsigned int cpu); + #else /* CONFIG_X86_LOCAL_APIC */ static inline unsigned int read_apic_id(void) { return 0; } --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -103,6 +103,7 @@ static struct apic apic_flat __ro_after_ .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_mem_read, .write = native_apic_mem_write, @@ -175,6 +176,7 @@ static struct apic apic_physflat __ro_af .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_mem_read, .write = native_apic_mem_write, --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -97,6 +97,14 @@ void native_send_call_func_ipi(const str __apic_send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } +void apic_send_nmi_to_offline_cpu(unsigned int cpu) +{ + if (WARN_ON_ONCE(!apic->nmi_to_offline_cpu)) + return; + if (WARN_ON_ONCE(!cpumask_test_cpu(cpu, &cpus_booted_once_mask))) + return; + apic->send_IPI(cpu, NMI_VECTOR); +} #endif /* CONFIG_SMP */ static inline int __prepare_ICR2(unsigned int mask) --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -251,6 +251,7 @@ static struct apic apic_x2apic_cluster _ .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_msr_read, .write = native_apic_msr_write, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -166,6 +166,7 @@ static struct apic apic_x2apic_phys __ro .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_msr_read, .write = native_apic_msr_write, From patchwork Mon Oct 2 12:00:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147319 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1469096vqb; Mon, 2 Oct 2023 07:33:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGIz3cYYT6J/6UntdC/JDIqtObuXoM1nR21xsQMPnMgzRVGeEd54rgj/Yo8CWJXWXVR8cXq X-Received: by 2002:a05:6a20:4311:b0:138:60e:9c4 with SMTP id h17-20020a056a20431100b00138060e09c4mr11540016pzk.23.1696257222602; Mon, 02 Oct 2023 07:33:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696257222; cv=none; d=google.com; s=arc-20160816; b=BZHPxI14RNpW/EpgBpVotknQGuI54kC3+Nvld9aFA4OB4WcldPhxb6OxEL1ug0SeJv vmEcSb/bidIy6J6UPW/b2RQE/2mPC4MGAvNDctqeGZLYgq/CguZYyvjL1kyoclgTkKax gEctj/h+SP7spa94PMea+DuZyVK1cbcvW6gKiiprnKca5tFKkbziCNdOOoPz2BCt6+xZ feXm99erSHXoGasHxBGVKdhzyx/imssSrRXhgbcB1eq4/1lXtdY8zK9OGEHrlLcE5qW5 g9iSC97u1AfCxjGOf8azvWXx4lVcOx4vujgvf7lOEYkndwSFb4g13Ry2U7at3r5xMuqj UUcQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=8oYiegpRfX5SvjECHLUXTmkD7rHh3hPJZTf21wfE6Kk=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=IWgb23tiJDvRFXp4fmY6zcKIGcho9DXu0CabQc93K/9ptgujx1CCyLkzXSF1a++YJZ 0MqFbQ8PxoqGFy6Nr9hexAqSvNEtfhLyFNqQOcOgF4Y0sHiWu5+clhQ38nC0zrTYX7Cu PiXVrboQOfcR8+pSHCdFCis7FOl7l/+n/9W3+ylJHRA0wQxqYq/02ycm75jK/LHx00FY W69uALIRYkQVx1GE+Vm172XiNvXlP7FAjIBzUGpW14QpnGVZOvpTsHcLZIo+7xaWNAcW BozYUztmQWdhX+Qrouy7qY9hUGXZSkbD1686DvDCfS7DxB4YU+cT5XxE+7t08FutBNhs peQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="KIHw/Je8"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id q15-20020a056a00084f00b0068fc8b33074si29065246pfk.161.2023.10.02.07.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 07:33:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="KIHw/Je8"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 70C0B80384E8; Mon, 2 Oct 2023 05:01:38 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237082AbjJBMBN (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33638 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236964AbjJBMAb (ORCPT ); Mon, 2 Oct 2023 08:00:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C0D1410EF for ; Mon, 2 Oct 2023 05:00:10 -0700 (PDT) Message-ID: <20231002115903.660850472@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8oYiegpRfX5SvjECHLUXTmkD7rHh3hPJZTf21wfE6Kk=; b=KIHw/Je8LgRtCOdy7impvyQpuIP0OJ4OliSlqIznc9mkZDzXyn0kXpddE+AnoiGgy+vR0d wQRoVZwCB/0Y81ltYBOYOwbrAqo+ehxygLX+NNAu5czU7yxXB+apPhpobs/jI+KjGi5NxM ZMcZoENQ6YgrmmKkuyYsVYVws1CqfUXYpA9t6qJuVv38q3pzVKdQIaitR3Y+ty0xSonRX6 qAs5J9jlu5r+Fpkxf+yfFH22PI2VREZPJbqxoF/2wWuGwD16U5x4N5e+q+4x32xr8k3aum cmKM4azN7rj14l6ktvCbYD25+3G1zjpMfmGDEZoQH9N/OZqVY7WVZieEul+FoA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248009; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=8oYiegpRfX5SvjECHLUXTmkD7rHh3hPJZTf21wfE6Kk=; b=tFoiQfLaM/eYyL92a2C8IQf2dLJFTRoHOCfN/B5qKJGiVj2cyPaeUtgB/D7TMOCVDpySqE HlKtZ0GG8EmUtGBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 28/30] x86/microcode: Handle "offline" CPUs correctly References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:08 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:01:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778654613382715327 X-GMAIL-MSGID: 1778654613382715327 From: Thomas Gleixner Offline CPUs need to be parked in a safe loop when microcode update is in progress on the primary CPU. Currently offline CPUs are parked in 'mwait_play_dead()', and for Intel CPUs, its not a safe instruction, because 'mwait' instruction can be patched in the new microcode update that can cause instability. - Adds a new microcode state 'UCODE_OFFLINE' to report status on per-cpu basis. - Force NMI on the offline CPUs. Wakeup offline CPUs while the update is in progress and then return them back to 'mwait_play_dead()' after microcode update is complete. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 1 arch/x86/kernel/cpu/microcode/core.c | 112 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 1 arch/x86/kernel/nmi.c | 5 + 4 files changed, 113 insertions(+), 6 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -71,6 +71,7 @@ static inline u32 intel_get_microcode_re #endif /* !CONFIG_CPU_SUP_INTEL */ bool microcode_nmi_handler(void); +void microcode_offline_nmi_handler(void); #ifdef CONFIG_MICROCODE_LATE_LOADING DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -301,8 +301,9 @@ struct microcode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); +static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; -static atomic_t late_cpus_in; +static cpumask_t cpu_offline_mask; static noinstr bool wait_for_cpus(atomic_t *cnt) { @@ -410,7 +411,7 @@ static noinstr void load_secondary(unsig instrumentation_end(); } -static void load_primary(unsigned int cpu) +static void __load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -445,6 +446,67 @@ static void load_primary(unsigned int cp } } +static bool kick_offline_cpus(unsigned int nr_offl) +{ + unsigned int cpu, timeout; + + for_each_cpu(cpu, &cpu_offline_mask) { + /* Enable the rendevouz handler and send NMI */ + per_cpu(ucode_ctrl.nmi_enabled, cpu) = true; + apic_send_nmi_to_offline_cpu(cpu); + } + + /* Wait for them to arrive */ + for (timeout = 0; timeout < (USEC_PER_SEC / 2); timeout++) { + if (atomic_read(&offline_in_nmi) == nr_offl) + return true; + udelay(1); + } + /* Let the others time out */ + return false; +} + +static void release_offline_cpus(void) +{ + unsigned int cpu; + + for_each_cpu(cpu, &cpu_offline_mask) + per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE; +} + +static void load_primary(unsigned int cpu) +{ + unsigned int nr_offl = cpumask_weight(&cpu_offline_mask); + bool proceed = true; + + /* Kick soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + proceed = kick_offline_cpus(nr_offl); + + /* If the soft-offlined CPUs did not respond, abort */ + if (proceed) + __load_primary(cpu); + + /* Unconditionally release soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + release_offline_cpus(); +} + +/* + * Minimal stub rendevouz handler for soft-offlined CPUs which participate + * in the NMI rendevouz to protect against a concurrent NMI on affected + * CPUs. + */ +void noinstr microcode_offline_nmi_handler(void) +{ + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) + return; + raw_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.result, UCODE_OFFLINE); + raw_atomic_inc(&offline_in_nmi); + wait_for_ctrl(); +} + static noinstr bool microcode_update_handler(void) { unsigned int cpu = raw_smp_processor_id(); @@ -500,6 +562,7 @@ static int load_cpus_stopped(void *unuse static int load_late_stop_cpus(void) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; @@ -507,6 +570,7 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&offline_in_nmi, 0); loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* @@ -529,6 +593,7 @@ static int load_late_stop_cpus(void) case UCODE_UPDATED: updated++; break; case UCODE_TIMEOUT: timedout++; break; case UCODE_OK: siblings++; break; + case UCODE_OFFLINE: offline++; break; default: failed++; break; } } @@ -540,6 +605,13 @@ static int load_late_stop_cpus(void) /* Nothing changed. */ if (!failed && !timedout) return 0; + + nr_offl = cpumask_weight(&cpu_offline_mask); + if (offline < nr_offl) { + pr_warn("%u offline siblings did not respond.\n", + nr_offl - atomic_read(&offline_in_nmi)); + return -EIO; + } pr_err("update failed: %u CPUs failed %u CPUs timed out\n", failed, timedout); return -EIO; @@ -573,19 +645,49 @@ static int load_late_stop_cpus(void) * modern CPUs uses MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. * - * 2) Initialize the per CPU control structure + * As soft-offlined CPUs still react on NMIs, the SMT sibling + * restriction can be lifted when the vendor driver signals to use NMI + * for rendevouz and the APIC provides a mechanism to send an NMI to a + * soft-offlined CPU. The soft-offlined CPUs are then able to + * participate in the rendezvouz in a trivial stub handler. + * + * 2) Initialize the per CPU control structure and create a cpumask + * which contains "offline"; secondary threads, so they can be handled + * correctly by a control CPU. */ static bool setup_cpus(void) { struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; + bool allow_smt_offline; unsigned int cpu; + allow_smt_offline = microcode_ops->nmi_safe || + (microcode_ops->use_nmi && apic->nmi_to_offline_cpu); + + cpumask_clear(&cpu_offline_mask); + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + /* + * Offline CPUs sit in one of the play_dead() functions + * with interrupts disabled, but they still react on NMIs + * and execute arbitrary code. Also MWAIT being updated + * while the offline CPU sits there is not necessarily safe + * on all CPU variants. + * + * Mark them in the offline_cpus mask which will be handled + * by CPU0 later in the update process. + * + * Ensure that the primary thread is online so that it is + * guaranteed that all cores are updated. + */ if (!cpu_online(cpu)) { - if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { - pr_err("CPU %u not online\n", cpu); + if (topology_is_primary_thread(cpu) || !allow_smt_offline) { + pr_err("CPU %u not online, loading aborted\n", cpu); return false; } + cpumask_set_cpu(cpu, &cpu_offline_mask); + per_cpu(ucode_ctrl, cpu) = ctrl; + continue; } /* --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -17,6 +17,7 @@ enum ucode_state { UCODE_NFOUND, UCODE_ERROR, UCODE_TIMEOUT, + UCODE_OFFLINE, }; struct microcode_ops { --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -502,8 +502,11 @@ DEFINE_IDTENTRY_RAW(exc_nmi) if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) raw_atomic_long_inc(&nsp->idt_calls); - if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) + if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) { + if (microcode_nmi_handler_enabled()) + microcode_offline_nmi_handler(); return; + } if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { this_cpu_write(nmi_state, NMI_LATCHED); From patchwork Mon Oct 2 12:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147522 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1721530vqb; Mon, 2 Oct 2023 15:16:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG+SB+kJKVIfkZxzyXEuqkyDT2gToGzM5cY/fzgEb03fGlbJaWqQ+hnEnkcDsFCHgk8mfgI X-Received: by 2002:a05:6870:14d3:b0:1be:ceca:c666 with SMTP id l19-20020a05687014d300b001bececac666mr16671654oab.14.1696284967204; Mon, 02 Oct 2023 15:16:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696284967; cv=none; d=google.com; s=arc-20160816; b=OqJeLfA8LrimgXPYiMLjGg3SaNm+1NxSJrsGHQdxECLrqBe70bc9rUMKSUhl6Qt23t HCqZ4niAUqqXkfJepOUm+Vxpt2LicSDJRUXBJmapkNYLWNf0tpfPZ6wjUBQ0BwIWcfke pYeLZ39+eMVyAvSdB3LEpeqgR2oYgAzKRbONQY2qp8NHbRCJUSd7lN0MfI61H3nDmtzG v0Vry8ZYMg2DIW1VnyX2h5xvh/Ofe6lDy4uVKrYMn+Iac4panhCxKsM7WHUGmJdC5FJ8 6Z5V39dcz6ZSDpb7YK48s5AM8IfVOjzlnh1JNn1pBmdjy/l259oeKXDtJft6Q/wAj41u mKGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=V/OOq2KAyHHYfMLCuDju6SeSAJDyubRVURMXRghdJgA=; fh=u57tXYamzTrJA+Ht8n1u7SfTMptrQaIb6LVW+jsaYf4=; b=wLKwkqX3tmraV83PfMRIQGphsb9ONIq5yE2/X/bc1OC+0b6NfuN49wf6bX4foEUQnc EdLWzuAyTIzEmr9eYllJ8HQe7/hw1zo6sXAn0t12kogh/wIDUcnlVseubA5tPLC5z6SW 1H8YL+Lr1ykNnPCUOQLjUxa4A/ZBQcfdSqzsepfiXxZQB2SSvZtlTth0PQL/DwaPxwFH TTNNQfJyu3Ic8FXYN+JTS8flFhARWJ1UK/HnMKaJPLfki30bKsCbPfPddQWFXeKwv9v+ CGOQQ+Q3xRGfNkkixvVEIh+lqu952G3skSqQsK2jCnyeJsJ8PBt/vhPTnfiKIE1FP0hu 19Jg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=iUKPW7+j; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=GLXHRCyj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id q16-20020a656850000000b0056b4065299esi28265946pgt.621.2023.10.02.15.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 15:16:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=iUKPW7+j; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=GLXHRCyj; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id AD5BF8116E51; Mon, 2 Oct 2023 05:02:16 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237077AbjJBMBK (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33666 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237016AbjJBMAb (ORCPT ); Mon, 2 Oct 2023 08:00:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3FB510F4 for ; Mon, 2 Oct 2023 05:00:11 -0700 (PDT) Message-ID: <20231002115903.718904225@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248010; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=V/OOq2KAyHHYfMLCuDju6SeSAJDyubRVURMXRghdJgA=; b=iUKPW7+jEsDTmAeR403a0/4LRdQrAgGH020OOHBfDSdpn6e86vGhUyfCfV+Pj/0+2/dwnR NgOsky2JIE28q3KA2Ou+qYI5EbeTYwTWATVx4tnVcKhj7FgR1lG8KPqe1JqPeWqFdjmZdA NhnGZfMHrbJL7zNmHDUnKVNwwaQa+vP/h5WSrbG8CcWI4pJEk2IzOIGAlJg4Mx/vbBvhnI x7XRzhR8f5tTu8vcIJekr+FDVrPWEHCOVME1On6G11KEdQAVNbYECH6f4Nr3DHrXVYkAoK 4zQWvuHBzNu6jXtIjbRO6WOyHERQAB62eD2P0Qz/TtUJGXR34j3dvvxcnJR2hQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248010; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=V/OOq2KAyHHYfMLCuDju6SeSAJDyubRVURMXRghdJgA=; b=GLXHRCyjcwhMb1wA1xHTSHbZllj7X0IL0+BYobm2G4h2AZgv2xprP6xYeTG3rHRZH3/EWK f9RMzgwqFvumQTAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov Subject: [patch V4 29/30] x86/microcode: Prepare for minimal revision check References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:10 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:02:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778683705630743033 X-GMAIL-MSGID: 1778683705630743033 From: Thomas Gleixner Applying microcode late can be fatal for the running kernel when the update changes functionality which is in use already in a non-compatible way, e.g. by removing a CPUID bit. There is no way for admins which do not have access to the vendors deep technical support to decide whether late loading of such a microcode is safe or not. Intel has added a new field to the microcode header which tells the minimal microcode revision which is required to be active in the CPU in order to be safe. Provide infrastructure for handling this in the core code and a command line switch which allows to enforce it. If the update is considered safe the kernel is not tainted and the annoying warning message not emitted. If it's enforced and the currently loaded microcode revision is not safe for late loading then the load is aborted. Signed-off-by: Thomas Gleixner --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ arch/x86/Kconfig | 23 ++++++++++++++++++++++- arch/x86/kernel/cpu/microcode/amd.c | 3 +++ arch/x86/kernel/cpu/microcode/core.c | 19 ++++++++++++++----- arch/x86/kernel/cpu/microcode/intel.c | 3 +++ arch/x86/kernel/cpu/microcode/internal.h | 3 +++ 6 files changed, 50 insertions(+), 6 deletions(-) --- --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3275,6 +3275,11 @@ mga= [HW,DRM] + microcode.force_minrev= [X86] + Format: + Enable or disable the microcode minimal revision + enforcement for the runtime microcode loader. + min_addr=nn[KMG] [KNL,BOOT,IA-64] All physical memory below this physical address is ignored. --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1322,7 +1322,28 @@ config MICROCODE_LATE_LOADING is a tricky business and should be avoided if possible. Just the sequence of synchronizing all cores and SMT threads is one fragile dance which does not guarantee that cores might not softlock after the loading. Therefore, - use this at your own risk. Late loading taints the kernel too. + use this at your own risk. Late loading taints the kernel unless the + microcode header indicates that it is safe for late loading via the + minimal revision check. This minimal revision check can be enforced on + the kernel command line with "microcode.minrev=Y". + +config MICROCODE_LATE_FORCE_MINREV + bool "Enforce late microcode loading minimal revision check" + default n + depends on MICROCODE_LATE_LOADING + help + To prevent that users load microcode late which modifies already + in use features, newer microcodes have a minimum revision field + in the microcode header, which tells the kernel which minimum + revision must be active in the CPU to safely load that new microcode + late into the running system. If disabled the check will not + be enforced but the kernel will be tainted when the minimal + revision check fails. + + This minimal revision check can also be controlled via the + "microcode.minrev" parameter on the kernel command line. + + If unsure say Y. config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -880,6 +880,9 @@ static enum ucode_state request_microcod enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; + if (force_minrev) + return UCODE_NFOUND; + if (c->x86 >= 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,6 +46,9 @@ static struct microcode_ops *microcode_ops; static bool dis_ucode_ldr = true; +bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV); +module_param(force_minrev, bool, S_IRUSR | S_IWUSR); + bool initrd_gone; /* @@ -559,15 +562,17 @@ static int ucode_load_cpus_stopped(void return 0; } -static int load_late_stop_cpus(void) +static int load_late_stop_cpus(bool is_safe) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); + if (!is_safe) { + pr_err("Late microcode loading without minimal revision check.\n"); + pr_err("You should switch to early loading, if possible.\n"); + } atomic_set(&late_cpus_in, num_online_cpus()); atomic_set(&offline_in_nmi, 0); @@ -617,7 +622,9 @@ static int load_late_stop_cpus(void) return -EIO; } - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + if (!is_safe || failed || timedout) + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("load: updated on %u primary CPUs with %u siblings\n", updated, siblings); if (failed || timedout) { pr_err("load incomplete. %u CPUs timed out or failed\n", @@ -707,7 +714,9 @@ static int load_late_locked(void) switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return load_late_stop_cpus(); + return load_late_stop_cpus(false); + case UCODE_NEW_SAFE: + return load_late_stop_cpus(true); case UCODE_NFOUND: return -ENOENT; default: --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -470,6 +470,9 @@ static enum ucode_state parse_microcode_ unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; + if (force_minrev) + return UCODE_NFOUND; + while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -13,6 +13,7 @@ struct device; enum ucode_state { UCODE_OK = 0, UCODE_NEW, + UCODE_NEW_SAFE, UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, @@ -36,6 +37,8 @@ struct microcode_ops { use_nmi : 1; }; +extern bool force_minrev; + extern struct ucode_cpu_info ucode_cpu_info[]; struct cpio_data find_microcode_in_initrd(const char *path); From patchwork Mon Oct 2 12:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 147363 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp1537323vqb; Mon, 2 Oct 2023 09:20:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHe8Bf84Xc+Ug9d5+GgtSaMWqOPRz+lS3OWqBcpn0AeL5n7Ux6+qNyKq8DVoq5dJfKzvBv3 X-Received: by 2002:a05:6a21:6811:b0:161:2bed:6b3a with SMTP id wr17-20020a056a21681100b001612bed6b3amr2647053pzb.17.1696263607641; Mon, 02 Oct 2023 09:20:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696263607; cv=none; d=google.com; s=arc-20160816; b=uEhJPseKy5H+Wgp9fKDzV55VP/uBFAP/TKU1CAY0Zh8OEL9Ds/E6mHaSWnI/C2GpFn VuP6tC9JVKhpilMDSPU2ZfGC4xwIQR9MrSJ5MAIHxlfIZaTz+rxcM1ZY9k7u4zYcWpGI K+mCHO2LhMcfuPPuNhgwh61pd4tjIxU8FWT+lS2DsWV6hBMGco0mLWk15hqk016iS1hJ OKUk3Ki4ii0FM4fPrGKqKAV8MY51MuByvSVZTWJnCbLn7+65zP5xquJAn5OOhyCdC8P6 Nsai34TFp4rh+RePYl9ktwR0dyeSYwCnueBr1t+u2cd7meDjwzOyeo4KDn10rDDtRUIX idqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=XoE7TiDQteSLrCQRHgJsABz3dix8qDu4/P0GvYZKzRs=; fh=Fw4dspu3lEWS7xf2bQx5+rNTgFONiGLilI8487/7QuM=; b=or0bCTc9fKSbqyHvfWzfa6Brv1JztRigXM0ZlUiUAd9vzgu13LEeVNg5DjMM1lsSnv vGV+B6T66CdTLQSeEeKG5CqMh8qJNAZHQ1gQx2M1ugfTobmYt7hKEKraoiiYR/+lR7b0 54dLklktFCSDGNJNbZNlu/mrtYCtG+HVLv0b+qO+G9O3DICYQmdt988LOWv+sNKPCAne HeR6ZA1jF7Tco6c1Bgwxb+qzj/WR6uj+ThhCOiT8n+Gv8UcSFhMYW011jBrc5Se30vby hs97TTUcat3YIj9c8nau8wEtvYFdBGm9C0/bOKSUc5LYm521V+bXzgP+sAwmP2exb+VG xqbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=irvTR4sH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=dFRt+way; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id h12-20020a056a00230c00b006934390d0casi13226953pfh.36.2023.10.02.09.20.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Oct 2023 09:20:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=irvTR4sH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=dFRt+way; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 99A8080CFD14; Mon, 2 Oct 2023 05:03:08 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236998AbjJBMBQ (ORCPT + 18 others); Mon, 2 Oct 2023 08:01:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33720 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236966AbjJBMAc (ORCPT ); Mon, 2 Oct 2023 08:00:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E396110FD for ; Mon, 2 Oct 2023 05:00:12 -0700 (PDT) Message-ID: <20231002115903.776467264@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1696248011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XoE7TiDQteSLrCQRHgJsABz3dix8qDu4/P0GvYZKzRs=; b=irvTR4sHHgh1UZ38/SgCh4jtEYh2L50NahHblK6dy7VyYdokrEaf0huo0AAw+SMB2ksh0z ILoa7nzjoQv2NXXlqSSlvmfTF/fpHB7asmV9fRLcYirJ4BgGWv+IylVnmiJG4ZNwIdGKOb ILuxX+s/P9Lh8qhDZXh0vdrdIcZ9JkaS9Ui9JRa46YefbnH7VAHwAjl6mZuCpsIOVLxGHN x9KtbUVbfhqJyYMVWMoYdEj+UNlOQbALp8Yw0e30LpwbHCypf8GzGVVXHtRjWRYBzj6eSk civSTknjmchaS5rxyDuZcabpRZIjRbYc+4TA9ph674nRiHZod79RNN91Qgb48g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1696248011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=XoE7TiDQteSLrCQRHgJsABz3dix8qDu4/P0GvYZKzRs=; b=dFRt+way33Pp0Ua1ppbl+f4fVRnAvEyriC/Jc6A1keoMEYbRfJ6vlErwu+iWzL9s0gGqHr DuL1cWj8OU39EnAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , "Chang S. Bae" , Arjan van de Ven , Nikolay Borisov , Ashok Raj Subject: [patch V4 30/30] x86/microcode/intel: Add a minimum required revision for late-loads References: <20231002115506.217091296@linutronix.de> MIME-Version: 1.0 Date: Mon, 2 Oct 2023 14:00:11 +0200 (CEST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 02 Oct 2023 05:03:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778661308366235823 X-GMAIL-MSGID: 1778661308366235823 From: Ashok Raj In general users don't have the necessary information to determine whether late loading of a new microcode version is safe and does not modify anything which the currently running kernel uses already, e.g. removal of CPUID bits or behavioural changes of MSRs. To address this issue, Intel has added a "minimum required version" field to a previously reserved field in the microcode header. Microcode updates should only be applied if the current microcode version is equal to, or greater than this minimum required version. Thomas made some suggestions on how meta-data in the microcode file could provide Linux with information to decide if the new microcode is suitable candidate for late loading. But even the "simpler" option requires a lot of metadata and corresponding kernel code to parse it, so the final suggestion was to add the 'minimum required version' field in the header. When microcode changes visible features, microcode will set the minimum required version to its own revision which prevents late loading. Old microcode blobs have the minimum revision field always set to 0, which indicates that there is no information and the kernel considers it as unsafe. This is a pure OS software mechanism. The hardware/firmware ignores this header field. For early loading there is no restriction because OS visible features are enumerated after the early load and therefor a change has no effect. The check is always enabled, but by default not enforced. It can be enforced via Kconfig or kernel command line. If enforced, the kernel refuses to late load microcode with a minium required version field which is zero or when the currently loaded microcode revision is smaller than the minimum required revision. If not enforced the load happens independent of the revision check to stay compatible with the existing behaviour, but it influences the decision whether the kernel is tainted or not. If the check signals that the late load is safe, then the kernel is not tainted. Early loading is not affected by this. [ tglx: Massaged changelog and fixed up the implementation ] Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 3 +- arch/x86/kernel/cpu/microcode/intel.c | 37 ++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -36,7 +36,8 @@ struct microcode_header_intel { unsigned int datasize; unsigned int totalsize; unsigned int metasize; - unsigned int reserved[2]; + unsigned int min_req_ver; + unsigned int reserved; }; struct microcode_intel { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -463,16 +463,40 @@ static enum ucode_state apply_microcode_ return ret; } +static bool ucode_validate_minrev(struct microcode_header_intel *mc_header) +{ + int cur_rev = boot_cpu_data.microcode; + + /* + * When late-loading, ensure the header declares a minimum revision + * required to perform a late-load. The previously reserved field + * is 0 in older microcode blobs. + */ + if (!mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Microcode header does not specify a required min version\n"); + return false; + } + + /* + * Check whether the minimum revision specified in the header is either + * greater or equal to the current revision. + */ + if (cur_rev < mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Current revision 0x%x too old\n", cur_rev); + pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver); + return false; + } + return true; +} + static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; + bool is_safe, new_is_safe = false; int cur_rev = uci->cpu_sig.rev; unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; - if (force_minrev) - return UCODE_NFOUND; - while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; @@ -515,9 +539,14 @@ static enum ucode_state parse_microcode_ if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; + is_safe = ucode_validate_minrev(&mc_header); + if (force_minrev && !is_safe) + continue; + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; + new_is_safe = is_safe; mc = NULL; } @@ -529,7 +558,7 @@ static enum ucode_state parse_microcode_ return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; - return UCODE_NEW; + return new_is_safe ? UCODE_NEW_SAFE : UCODE_NEW; fail: kvfree(mc);