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Sun, 01 Oct 2023 03:34:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778556979267260223 X-GMAIL-MSGID: 1778556979267260223 Add description for the LX2160A second SerDes block. It is functionally identical to the first one already added in commit 3cbe93a1f540 ("arch: arm64: dts: lx2160a: describe the SerDes block #1"). The SerDes driver currently updates the registers of all 8 lanes by default during probe. Because currently this driver only supports configuration of network protocols, this can lead to problems with certain configurations. Set status property to "disabled" by default so that existing boards are not impacted. Signed-off-by: Josua Mayer --- V4 -> V5: expand commit hash reference in commit message V5 -> V6: status disabled by default arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index ea6a94b57aeb..f176ca2e244e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -626,6 +626,13 @@ serdes_1: phy@1ea0000 { #phy-cells = <1>; }; + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; From patchwork Sun Oct 1 10:32:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 147137 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp960359vqb; Sun, 1 Oct 2023 09:40:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFCHvyDxbPpvb1TFw4UnfY6lofiTYKMOFs5KJgsl3dMhYjSg9qchOO8g8Pa5+zc/XruynuQ X-Received: by 2002:a05:6808:1413:b0:3ae:13fd:fa93 with SMTP id w19-20020a056808141300b003ae13fdfa93mr12320542oiv.15.1696178443206; Sun, 01 Oct 2023 09:40:43 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696178443; cv=pass; d=google.com; s=arc-20160816; b=VOW7BjRKW0oimZpRs8drR41zqmCbusWxC+dS86jWFTUm1m0SFcm6Ikfo5lCGPJW22w 8ruBlGFdpZ6qIDQc3JamZdaBRiCW1o3ein2ZV9vCDYswjq5IvHEMwjrPXOmxAFn0bf9R 1wdA0AKSsTDvtOEL5DTEpan3rlEExOvFcJMyK+N3NHXyloTF+40DPE+pYUd5U+jcqTOz X12RzkiNsskeNFXdL16+QT/K/LPmmHzK+qPTxviACyQzxTWYoBjvaLWs4lTqPFHhQ05B IN3JFNqnvc5vJzkt0WSKDN3zCZwmnvmWAsfTrg8A6wiGtW3Ufed9ef73tpHjKWdlRPiI D7oA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K0B3b/ucyjOAYWlQFGDQjlTeWZr8CxeOTg0uej/vw2o=; fh=/2YCB1ppwQW2mbOFAlOieSQrvDkCLfW7YfdxkD1bnpY=; b=BEE4Ojlrcqhppa9Xvaif3MynwfVxYUt9ruUyNwi7WNFlKInrn6TP3FbvFA7DX5f06v GMNB1HhEaZLUFl6EQFW5WKYGmrr6DifA9IBUxILoUtikR/4tisowFdElmRVxSZGAmYJM +28A0ceOdhlO6cllZBd8faZ5wmbvSzvObv6TgPH2uthmmDGkrIiF3iHAGfjPgx7I5lem vhShCLN76d6oWsmH2FIhy894MxEwsNMwVxhtusPdZFxDS24EdcE9ITYJwHmUzXbo3UMx wKbwoTWM/o6Lk9tpZsjJ5Hbw3fzTgXDh4R3FKQ0eQCNsf31mRj4LNc6ZQ/Z+ql7760fV bI6w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=pW03eRS4; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Sun, 01 Oct 2023 03:34:43 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778572007130254594 X-GMAIL-MSGID: 1778572007130254594 dpaa2 mac supports runtime configuration of network protocols on a generic phy object specified via the "phys" property. It is currently used with the SerDes28G driver to switch SerDes protocol between SGMII and USXGMII at runtime. Support was introduced with: f978fe8 "dpaa2-mac: configure the SerDes phy on a protocol change" Add bindings description for the missing "phys" property, to fix dtc_chk errors present in various layerscape based dts: 'phys' does not match any of the regexes: 'pinctrl-[0-9]+' Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- V1 -> V2: this patch is newly added to patch-set Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml index a1b71b35319e..a40c7a84af2a 100644 --- a/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml +++ b/Documentation/devicetree/bindings/net/fsl,qoriq-mc-dpmac.yaml @@ -24,6 +24,10 @@ properties: maxItems: 1 description: The DPMAC number + phys: + maxItems: 1 + description: Generic PHY for SerDes runtime configuration. + phy-handle: true phy-connection-type: true From patchwork Sun Oct 1 10:32:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 147092 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp864688vqb; Sun, 1 Oct 2023 06:11:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGx6VtYQzR0oLhNum34V0TxSRWwMr0eoLkC015AuICn2yiJ1kkOdsCuFZUewViB0T6VzumJ X-Received: by 2002:a05:6a00:17a3:b0:690:28d0:b7b3 with SMTP id s35-20020a056a0017a300b0069028d0b7b3mr11056285pfg.13.1696165861666; Sun, 01 Oct 2023 06:11:01 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696165861; cv=pass; d=google.com; s=arc-20160816; b=Wx9VKfxaVljnd7CvOyoExuzJQINwwKAswSf8KFNx7F1EHtpqnWzVzfW09gyjhx5HgZ ea6ztCa3TkHCn4htBmQhcEpkRdKXY+0Zhokz35rRfmeYQdwxfYjNGiY9j4sGUdx4OfL2 m7Vtiiiw2ji2R3eH8Lay1vuUqhs5n+Jxm22g2bNCzdbrue8G+44dX+cS6NkRem88n5a5 9ZivcPXyRqVcsGHRkEL9KTYP1loGod8t9rSex2LZ7tv4siCQKpiOEsPRPlUPgke9oE/i 0aKCisxF/rBl9dd8vEcSOk4opN8ktFQSJaDXVHm/jfCrSgSm4Yn7HzoTiB1XjF+5Hmde Nc+g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6/kMZRWg37MsrhxB0ve8V8H3Ak3czJa/x43C8INCvUg=; fh=WKMNwxFfzK8HM30/YCnnkh6GnqiKp5BsmYprv0EYK2Y=; b=BSiUcpAfRikTuKxoHiYSIvujTspQdaM/WDWrEg+ziwFe9hv14AQBzlK8SIG9ceVlpu /jtZORUF665HWzTslx9xAha5v2ZUHQq4jGecf8zzQakIWcev4tzZS0N90p4VlmLftttY WoOeCKno3142l7hs1hHXhXGfOi/HQ4YC8Tz5JDeAwq3jMpZTFXkyRd1r/0RWlMlVfIRl ojuFMKv9lLB9cTlRgOtr/7ll+q7D0OpqW0noFDtfsvXMw1jgc8JrAd/scBs+0i8XD0x7 6tOerSR4kQKQP5/1ImJo3DzYW0hJ4GILjHAaqOXh8nkokqBhORbydRiVC4O+WtyjochU guzw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=qz4Ic4KR; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Sun, 01 Oct 2023 03:34:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778558814595566481 X-GMAIL-MSGID: 1778558814595566481 SolidRun now have 2 product lines around NXP Layerscape SoC: - LX2160A COM Express 7 - LX2162A System on Module LX2162 is a smaller package and reduced feature set to LX2160A; LX2162 SoM is also a smaller form factor and reduced feature set to CEX. Since both product lines are physically incompatible, the existing group "SolidRun LX2160A based Boards" has been renamed to include "CEX" in its name, meaning products based on LX2160A COM Express Module, following this pattern: "solidrun,", "solidrun,lx2160a-cex", "fsl,lx2160a" Add DT compatible for both SolidRun LX2162A SoM, and LX2162 Clearfog boards to a new group based on LX2162A SoM, following this pattern: "solidrun,", "solidrun,lx2162a-som", "fsl,lx2160a" Signed-off-by: Josua Mayer Reviewed-by: Krzysztof Kozlowski --- V1 -> V2: fixed to not break existing boards V1 -> V2: explained new board / som DT binding in commit message Documentation/devicetree/bindings/arm/fsl.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 2510eaa8906d..ff9bf9956972 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1384,7 +1384,7 @@ properties: - fsl,lx2162a-qds - const: fsl,lx2160a - - description: SolidRun LX2160A based Boards + - description: SolidRun LX2160A CEX-7 based Boards items: - enum: - solidrun,clearfog-cx @@ -1392,6 +1392,13 @@ properties: - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a + - description: SolidRun LX2162A SoM based Boards + items: + - enum: + - solidrun,lx2162a-clearfog + - const: solidrun,lx2162a-som + - const: fsl,lx2160a + - description: S32G2 based Boards items: - enum: From patchwork Sun Oct 1 10:32:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Josua Mayer X-Patchwork-Id: 147068 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp803608vqb; Sun, 1 Oct 2023 03:35:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGBPkane8W3FGVfqo84FA5AoE4qqbDGB3wpJKeWXUImUqmqptksGA6QIh8HCbwfBR4awV80 X-Received: by 2002:a05:6830:4cc:b0:6b9:1917:b2f3 with SMTP id s12-20020a05683004cc00b006b91917b2f3mr9589949otd.33.1696156521394; Sun, 01 Oct 2023 03:35:21 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1696156521; cv=pass; d=google.com; s=arc-20160816; b=J5Xghv7Ytv49Lpi9Hni/4lZ8QZ1fI49eFKKxdp/SiOJK8VU+hBdsZbXgsisNWk/KQS BKMWbcdInOIpzrNkt1CGRFARJiJmT4rgy15lTXeoeLIXCBl7UZLi/ACctUy6prFSUV7l mUqCB+MAL/6+4UK9KMzNQq4VHd7KuMTgS1/iK5oVeV916RXN9YX1yP3js9y0K0B0YgX4 tzXfpHS805EMWBP+cMURInYISX5XL1+nL7Zs3DIQtOsYyg+ppR9aq964+KiCHSG3bg5t 4SysfHY7RUfXUcN5WcykaLCjstbeETd6VTrnN7Ra7cLZlc+G2mN11vPVDdmGpCW1Gagt AeQQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=UCidCsCnAfr5ei5K0UOQ36OqMvouTZeaxqOFkQ9gYQs=; fh=EqfyfQ+59njdc516ESfSnumkVPBEbfmOsy910lTB3GA=; b=YJzUqYr6WkgBXdIVxCV1HHKhELC0NXeOMw0H5IZO5e8xj0i7RW96Kkb112xHw3OWyl wCtVJYIkaY79aG+FJyWE4/XHfxown+eQCLy7yVFtXv6LCZfI6HilWWKnQeX3etHOThM3 u8/ahPPXnww21tyP9zikC3nwfrSqRGFvfOZsefVWJwl9VOPfxd0frLTp25OJYoNRvNg4 JGM2yCNEYMtibWNVxX3AiYvTO0WqDvHSpkFH8ImRvbWmkak5r9DNcl0bWaMy1eM3LboR Hqy/M+keXEw7hw4KcV53St2k7vHAY2kHBnSkRDG7nPtUNaGViPum4Rok5F3XjgH0Y8OV Q5nA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@solidrn.onmicrosoft.com header.s=selector1-solidrn-onmicrosoft-com header.b=HFtCdSe4; arc=pass (i=1 spf=pass spfdomain=solid-run.com dkim=pass dkdomain=solid-run.com dmarc=pass fromdomain=solid-run.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Sun, 01 Oct 2023 03:34:50 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778549020127928301 X-GMAIL-MSGID: 1778549020127928301 Add support for the SolidRun LX2162A System on Module (SoM), and the Clearfog evaluation board. The SoM has few software-controllable features: - AR8035 Ethernet PHY - eMMC - SPI Flash - fan controller - various eeproms The Clearfog evaluation board provides: - microSD connector - USB-A - 2x 10Gbps SFP+ - 2x 25Gbps SFP+ with a retimer - 8x 2.5Gbps RJ45 - 2x mPCI (assembly option / disables 2xRJ45) The 8x RJ45 ports are connected with an 8-port PHY: Marvell 88E2580 supporting up to 5Gbps, while SoC and magnetics are limited to 2.5Gbps. However 2500 speed is untested due to documentation and drivier limitations. To avoid confusion the phy nodes have been explicitly limited to 1000 for now. The PCI nodes are disabled, but explicitly added to mark that this board can have pci. It is expected that the bootloader will patch the status property "okay" and disable 2x RJ45 ports, according to active serdes configuration. Signed-off-by: Josua Mayer --- V1 -> V2: reordered "compatible" and "reg" properties V1 -> V2: replaced chip-specific DT node names with generic ones V1 -> V2: removed dead code from fspi node V2 -> V3: dropped deprecated address-cells, address-size props from flash node V3 -> V4: reordered dt properties such that status is last V3 -> V4: changed ethernet-phy on som from /delete-node/ to disabled V5 -> V6: reordered status property in esdhc1 node V5 -> V6: moved i2c2 node by alphabetical order V5 -> V6: added empty lines between led nodes arch/arm64/boot/dts/freescale/Makefile | 1 + .../dts/freescale/fsl-lx2162a-clearfog.dts | 376 ++++++++++++++++++ .../dts/freescale/fsl-lx2162a-sr-som.dtsi | 73 ++++ 3 files changed, 450 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts create mode 100644 arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index a750be13ace8..50574f711bec 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -33,6 +33,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts new file mode 100644 index 000000000000..9f88583aa25e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A Clearfog +// +// Copyright 2023 Josua Mayer + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" +#include "fsl-lx2162a-sr-som.dtsi" + +/ { + model = "SolidRun LX2162A Clearfog"; + compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + i2c0 = &i2c0; + i2c1 = &i2c2; + i2c2 = &i2c4; + i2c3 = &sfp_i2c0; + i2c4 = &sfp_i2c1; + i2c5 = &sfp_i2c2; + i2c6 = &sfp_i2c3; + i2c7 = &mpcie1_i2c; + i2c8 = &mpcie0_i2c; + i2c9 = &pcieclk_i2c; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_sfp_at: led-sfp-at { + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ + default-state = "off"; + }; + + led_sfp_ab: led-sfp-ab { + gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ + default-state = "off"; + }; + + led_sfp_bt: led-sfp-bt { + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ + default-state = "off"; + }; + + led_sfp_bb: led-sfp-bb { + gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ + default-state = "off"; + }; + }; + + sfp_at: sfp-at { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c0>; + mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */ + maximum-power-milliwatt = <2000>; + }; + + sfp_ab: sfp-ab { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c1>; + mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bt: sfp-bt { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c2>; + mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bb: sfp-bb { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c3>; + mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */ + maximum-power-milliwatt = <2000>; + }; +}; + +&dpmac3 { + sfp = <&sfp_at>; + managed = "in-band-status"; + phys = <&serdes_1 7>; +}; + +&dpmac4 { + sfp = <&sfp_ab>; + managed = "in-band-status"; + phys = <&serdes_1 6>; +}; + +&dpmac5 { + sfp = <&sfp_bt>; + managed = "in-band-status"; + phys = <&serdes_1 5>; +}; + +&dpmac6 { + sfp = <&sfp_bb>; + managed = "in-band-status"; + phys = <&serdes_1 4>; +}; + +&dpmac11 { + phys = <&serdes_2 0>; + phy-handle = <ðernet_phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac12 { + phys = <&serdes_2 1>; + phy-handle = <ðernet_phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac13 { + phys = <&serdes_2 6>; + phy-handle = <ðernet_phy6>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac14 { + phys = <&serdes_2 7>; + phy-handle = <ðernet_phy8>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac15 { + phys = <&serdes_2 4>; + phy-handle = <ðernet_phy4>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac16 { + phys = <&serdes_2 5>; + phy-handle = <ðernet_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac17 { + /* override connection to on-SoM phy */ + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + + phys = <&serdes_2 2>; + phy-handle = <ðernet_phy5>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac18 { + phys = <&serdes_2 3>; + phy-handle = <ðernet_phy7>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&emdio1 { + ethernet_phy1: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + max-speed = <1000>; + }; + + ethernet_phy2: ethernet-phy@9 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <9>; + max-speed = <1000>; + }; + + ethernet_phy3: ethernet-phy@10 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <10>; + max-speed = <1000>; + }; + + ethernet_phy4: ethernet-phy@11 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <11>; + max-speed = <1000>; + }; + + ethernet_phy5: ethernet-phy@12 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <12>; + max-speed = <1000>; + }; + + ethernet_phy6: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <13>; + max-speed = <1000>; + }; + + ethernet_phy7: ethernet-phy@14 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <14>; + max-speed = <1000>; + }; + + ethernet_phy8: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + max-speed = <1000>; + }; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +ðernet_phy0 { + /* + * SoM has a phy at address 1 connected to SoC Ethernet Controller 1. + * It competes for WRIOP MAC17, and no connector has been wired. + */ + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* retimer@18 */ + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + sfp_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfp_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sfp_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sfp_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + mpcie1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + mpcie0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcieclk_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* clock-controller@6b */ + }; + }; +}; + +&pcie3 { + status = "disabled"; +}; + +&pcie4 { + status = "disabled"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio11 { + status = "okay"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio15 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; + +&pcs_mdio17 { + status = "okay"; +}; + +&pcs_mdio18 { + status = "okay"; +}; + +&serdes_1 { + status = "okay"; +}; + +&serdes_2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi new file mode 100644 index 000000000000..0580ea30cfbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A-SOM +// +// Copyright 2021 Rabeeh Khoury +// Copyright 2023 Josua Mayer + +&crypto { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <ðernet_phy0>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; + + ethernet_phy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&esdhc1 { + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + + fan-controller@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + ddr_spd: eeprom@51 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x51>; + read-only; + }; + + config_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +&i2c4 { + status = "okay"; + + variable_eeprom: eeprom@54 { + compatible = "st,24c2048", "atmel,24c2048"; + reg = <0x54>; + }; +};