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[88.207.96.216]) by smtp.googlemail.com with ESMTPSA id j25-20020a170906255900b0099bcf1c07c6sm13716547ejb.138.2023.09.30.03.22.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 03:22:20 -0700 (PDT) From: Robert Marko To: ilia.lin@kernel.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, rafael@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Robert Marko Subject: [PATCH v5 1/4] cpufreq: qcom-nvmem: add support for IPQ8074 Date: Sat, 30 Sep 2023 12:21:16 +0200 Message-ID: <20230930102218.229613-1-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Sat, 30 Sep 2023 03:23:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778478259228217447 X-GMAIL-MSGID: 1778478259228217447 IPQ8074 comes in 2 families: * IPQ8070A/IPQ8071A (Acorn) up to 1.4GHz * IPQ8072A/IPQ8074A/IPQ8076A/IPQ8078A (Hawkeye) up to 2.2GHz So, in order to be able to share one OPP table lets add support for IPQ8074 family based of SMEM SoC ID-s as speedbin fuse is always 0 on IPQ8074. IPQ8074 compatible is blacklisted from DT platdev as the cpufreq device will get created by NVMEM CPUFreq driver. Signed-off-by: Robert Marko Acked-by: Konrad Dybcio --- Changes in v4: * Add support for IPQ8174 (Oak) family Changes in v3: * Use enum for SoC versions Changes in v2: * Print an error if SMEM ID is not part of the IPQ8074 family and restrict the speed to Acorn variant (1.4GHz) drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/qcom-cpufreq-nvmem.c | 45 ++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c index 2016d47889c0..157c91b9962c 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -180,6 +180,7 @@ static const struct of_device_id blocklist[] __initconst = { { .compatible = "ti,am62a7", }, { .compatible = "qcom,ipq8064", }, + { .compatible = "qcom,ipq8074", }, { .compatible = "qcom,apq8064", }, { .compatible = "qcom,msm8974", }, { .compatible = "qcom,msm8960", }, diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 84d7033e5efe..ba9e1d60e5b5 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -30,6 +30,11 @@ #include +enum ipq8074_versions { + IPQ8074_HAWKEYE_VERSION = 0, + IPQ8074_ACORN_VERSION, +}; + struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { @@ -203,6 +208,41 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + u32 msm_id; + int ret; + *pvs_name = NULL; + + ret = qcom_smem_get_soc_id(&msm_id); + if (ret) + return ret; + + switch (msm_id) { + case QCOM_ID_IPQ8070A: + case QCOM_ID_IPQ8071A: + drv->versions = BIT(IPQ8074_ACORN_VERSION); + break; + case QCOM_ID_IPQ8072A: + case QCOM_ID_IPQ8074A: + case QCOM_ID_IPQ8076A: + case QCOM_ID_IPQ8078A: + drv->versions = BIT(IPQ8074_HAWKEYE_VERSION); + break; + default: + dev_err(cpu_dev, + "SoC ID %u is not part of IPQ8074 family, limiting to 1.4GHz!\n", + msm_id); + drv->versions = BIT(IPQ8074_ACORN_VERSION); + break; + } + + return 0; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -217,6 +257,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const struct qcom_cpufreq_match_data match_data_ipq8074 = { + .get_version = qcom_cpufreq_ipq8074_name_version, +}; + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -360,6 +404,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, + { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, { .compatible = "qcom,apq8064", .data = &match_data_krait }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, From patchwork Sat Sep 30 10:21:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 146947 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp473012vqb; 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[88.207.96.216]) by smtp.googlemail.com with ESMTPSA id j25-20020a170906255900b0099bcf1c07c6sm13716547ejb.138.2023.09.30.03.22.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 03:22:22 -0700 (PDT) From: Robert Marko To: ilia.lin@kernel.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, rafael@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Christian Marangi , Robert Marko Subject: [PATCH v5 2/4] dt-bindings: opp: opp-v2-kryo-cpu: Document named opp-microvolt property Date: Sat, 30 Sep 2023 12:21:17 +0200 Message-ID: <20230930102218.229613-2-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230930102218.229613-1-robimarko@gmail.com> References: <20230930102218.229613-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Sat, 30 Sep 2023 03:24:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778480210908874567 X-GMAIL-MSGID: 1778480210908874567 From: Christian Marangi Document named opp-microvolt property for opp-v2-kryo-cpu schema. This property is used to declare multiple voltage ranges selected on the different values read from efuses. The selection is done based on the speed pvs values and the named opp-microvolt property is selected by the qcom-cpufreq-nvmem driver. Signed-off-by: Christian Marangi Signed-off-by: Robert Marko Reviewed-by: Rob Herring --- Changes v5: * Fix typo in opp items Changes v4: * Address comments from Rob (meaning of pvs, drop of driver specific info, drop of legacy single voltage OPP, better specify max regulators supported) .../bindings/opp/opp-v2-kryo-cpu.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 27ea7eca73e5..8d2a47e9a854 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -65,6 +65,12 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused + + Bitmap for IPQ806X SoC: + 0: IPQ8062 + 1: IPQ8064/IPQ8066/IPQ8068 + 2: IPQ8065/IPQ8069 + 3-31: unused enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x9, 0xd, 0xe, 0xf, 0x10, 0x20, 0x30, 0x70] @@ -73,6 +79,23 @@ patternProperties: required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': + description: | + Named opp-microvolt property following the same generic + binding for named opp-microvolt. + + The correct voltage range is selected based on the values + in the efuse for the speed and the pvs (power variable + scaling). + minItems: 1 + maxItems: 4 # Up to 4 regulators: Core, Mem, Dig and HFPLL + items: + items: + - description: nominal voltage + - description: minimum voltage + - description: maximum voltage + required: - opp-hz @@ -258,6 +281,22 @@ examples: }; }; + /* Dummy opp table to give example for named opp-microvolt */ + opp-table-2 { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + }; + smem { compatible = "qcom,smem"; memory-region = <&smem_mem>; From patchwork Sat Sep 30 10:21:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 146968 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp545185vqb; Sat, 30 Sep 2023 12:21:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEPWBzom2zbYg/Xcc0+eObv+O3rLybxhFpFVVeqUnVlliN5AlEQpZQrXxSAu10POG4hVgEf X-Received: by 2002:a05:6a21:60f:b0:160:c1b9:a754 with SMTP id ll15-20020a056a21060f00b00160c1b9a754mr6363385pzb.45.1696101671669; Sat, 30 Sep 2023 12:21:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696101671; cv=none; d=google.com; s=arc-20160816; b=HkeqA+XXsX1JVSYYawejTNb2YbPCnDt7NpipzabT7nBiZ7KE66TdcXRx3XZdbHTrUW m5m8dBNSloi0TQvVRPeWFgg6tsCAfxH0PHYwLatabmUyH3kkh0LgbGLKSMuBKiArfPuw 0PndSNP4lT3VBtZ6ByjGc6HGiqzCgbkB1rTJ0mp6TX4naD4C/Eyrzqaeo5YCoWQAFCCm 9P5cMkCfDC4NLt2uowVecs+DOJ1TRnZqXYfIuFyx9IkI5sqWW6UXc3o09Uj0Sh8N/y/8 pQE7bLWeaFr9zYPVT75k5B5pgLkq3iod1LpwDV6uQ+3BZlJQmjX8z3hCEhyYoz+YJF/j jIHw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=At6mV+t12HD5fi2eom0kJSJcVqs7Y5KHuO03wN8Mx64=; fh=tIvQt8p5p62lUiQIgcyo1Qt2qWcFvCCPAhYjZMcUcZw=; b=uMVpMaYhlJ4ViwZiazvfJPlUp1Zlm0hUGz1+RpvaznutqJZ/kj8m8a+ShZrIpAVaW+ ClMOIQvjkR4D6QMNlAIm3HOkbvKskY42FUfYdwwPfAkpQdtAgZjJ6hREnxvwCCQnniRX hsJtc3CphTflcQ2ZBH+jzMdI0xNoEQeZNZ+RbiVU0rzxAPeCbwSFhnYpHbZfNZUF1O9z G8dHw59zwIMuypO4Ne/6yHR73I3wjLHSlHsMOdb66o0XHSPiczJWrlTeJhahDQqFST+Y SX8s49yA6K2pmudI7dnWOqPI0t9lsmz0YN14SsD9/97TvowTAXQNs7uyJ6s5JBR8ykg9 zgbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=abfsP9cM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from pete.vger.email (pete.vger.email. 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[88.207.96.216]) by smtp.googlemail.com with ESMTPSA id j25-20020a170906255900b0099bcf1c07c6sm13716547ejb.138.2023.09.30.03.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 03:22:23 -0700 (PDT) From: Robert Marko To: ilia.lin@kernel.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, rafael@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Christian Marangi , Robert Marko Subject: [PATCH v5 3/4] cpufreq: qcom-nvmem: add support for IPQ8064 Date: Sat, 30 Sep 2023 12:21:18 +0200 Message-ID: <20230930102218.229613-3-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230930102218.229613-1-robimarko@gmail.com> References: <20230930102218.229613-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Sat, 30 Sep 2023 03:24:51 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778491506583669763 X-GMAIL-MSGID: 1778491506583669763 From: Christian Marangi IPQ8064 comes in 3 families: * IPQ8062 up to 1.0GHz * IPQ8064/IPQ8066/IPQ8068 up to 1.4GHz * IPQ8065/IPQ8069 up to 1.7Ghz So, in order to be able to support one OPP table, add support for IPQ8064 family based of SMEM SoC ID-s and correctly set the version so opp-supported-hw can be correctly used. Bit are set with the following logic: * IPQ8062 BIT 0 * IPQ8064/IPQ8066/IPQ8068 BIT 1 * IPQ8065/IPQ8069 BIT 2 speed is never fused, only pvs values are fused. IPQ806x SoC doesn't have pvs_version so we drop and we use the new pattern: opp-microvolt-speed0-pvs Example: - for ipq8062 psv2 opp-microvolt-speed0-pvs2 = < 925000 878750 971250> Signed-off-by: Christian Marangi Signed-off-by: Robert Marko --- Changes in v4: * Free speedbin in case of an error Changes in v3: * Use enum for SoC version * Dont evaluate speed as its not fused, only pvs Changes in v2: * Include IPQ8064 support drivers/cpufreq/qcom-cpufreq-nvmem.c | 68 +++++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index ba9e1d60e5b5..3d93b511db86 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -35,6 +35,12 @@ enum ipq8074_versions { IPQ8074_ACORN_VERSION, }; +enum ipq806x_versions { + IPQ8062_VERSION = 0, + IPQ8064_VERSION, + IPQ8065_VERSION, +}; + struct qcom_cpufreq_drv; struct qcom_cpufreq_match_data { @@ -208,6 +214,62 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_ipq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0, pvs_ver = 0; + int msm_id, ret = 0; + u8 *speedbin; + size_t len; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) { + dev_err(cpu_dev, "Unable to read nvmem data. Defaulting to 0!\n"); + kfree(speedbin); + return -ENODEV; + } + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, speedbin); + + ret = qcom_smem_get_soc_id(&msm_id); + if (ret) + return ret; + + switch (msm_id) { + case QCOM_ID_IPQ8062: + drv->versions = BIT(IPQ8062_VERSION); + break; + case QCOM_ID_IPQ8064: + case QCOM_ID_IPQ8066: + case QCOM_ID_IPQ8068: + drv->versions = BIT(IPQ8064_VERSION); + break; + case QCOM_ID_IPQ8065: + case QCOM_ID_IPQ8069: + drv->versions = BIT(IPQ8065_VERSION); + break; + default: + dev_err(cpu_dev, + "SoC ID %u is not part of IPQ8064 family, limiting to 1.0GHz!\n", + msm_id); + drv->versions = BIT(IPQ8062_VERSION); + break; + } + + /* IPQ8064 speed is never fused. Only pvs values are fused. */ + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + kfree(speedbin); + return ret; +} + static int qcom_cpufreq_ipq8074_name_version(struct device *cpu_dev, struct nvmem_cell *speedbin_nvmem, char **pvs_name, @@ -257,6 +319,10 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +static const struct qcom_cpufreq_match_data match_data_ipq8064 = { + .get_version = qcom_cpufreq_ipq8064_name_version, +}; + static const struct qcom_cpufreq_match_data match_data_ipq8074 = { .get_version = qcom_cpufreq_ipq8074_name_version, }; @@ -403,7 +469,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,apq8096", .data = &match_data_kryo }, { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, - { .compatible = "qcom,ipq8064", .data = &match_data_krait }, + { .compatible = "qcom,ipq8064", .data = &match_data_ipq8064 }, { .compatible = "qcom,ipq8074", .data = &match_data_ipq8074 }, { .compatible = "qcom,apq8064", .data = &match_data_krait }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, From patchwork Sat Sep 30 10:21:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Marko X-Patchwork-Id: 146955 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2a8e:b0:403:3b70:6f57 with SMTP id in14csp500656vqb; Sat, 30 Sep 2023 10:19:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOoPufusR5SdjQGxkfRPsyaePOM5YRMWk9IKX73mpop61DO3MNJo1ro0Oaeccik6AQ87zM X-Received: by 2002:a17:90b:890:b0:276:785f:7edd with SMTP id bj16-20020a17090b089000b00276785f7eddmr6876389pjb.25.1696094356640; Sat, 30 Sep 2023 10:19:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696094356; cv=none; d=google.com; s=arc-20160816; b=gDgCDuOH9DGP3FsPFtaNYmqguMzNBumrdJ2hgReQXRg9P0b6xFe7eritF6w0KkbdqJ TLzXy2WyQ/e4xLuy76ilF75+TOcyxADiz2d+89jmQjiDYfOSacwQFGTPqvHlTFKSqVC8 6TyJGU2r/wK8aS5daMGsnIHOPdzboPHKNVfosPcLRaMNOfd6EqHIErmZvgDIn5I5NSTZ nx1RFPU7YBbJD/NoCXpf0NkNy2IeqislTzxWK+8sY8BQ4YdYkmddAsCJnMVaEIBAIHBu RWDudFr7Y1TCSn0Fk9tladBBbmZPtS3ojrqDGIc7pkO+vjLEpNrRXtYY+YrbUPvqI1Jn W7tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=upvkOshm+Utk6b+l4TjTOIuE/7SOxFRjndlDlP7Geug=; fh=tIvQt8p5p62lUiQIgcyo1Qt2qWcFvCCPAhYjZMcUcZw=; b=nfcvzgqGgznpfiyXDjS99WHlJLaMihGjuMgdUq+Ahm08ZT/o1bPALbfV+27XsteU3Z PxFlY4q8H3gwiLzCuzot9mkApZ6pFocwBjTmmk06b/niadMgxNYi3+IQnQVEql620o6S OLIIWfN29YhIseSFni87WYLEks8s8l2b7o2Ofet/2urq7O1O8yK2h4p7nBsKbfoLYrad rcfxy4l3OYoISoWJd7fY40sCDGpbqFyXI+zDqzVH13TXJnASieXBfOr7rUF3AzfYFlYx piheoUz4vv+AniyY9WUHg8AolryOWB7UtZHPTYsmCyGzAbYxQlYHlJ9kXPFt26dPIxo3 cn4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=BteT6fkt; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from snail.vger.email (snail.vger.email. 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[88.207.96.216]) by smtp.googlemail.com with ESMTPSA id j25-20020a170906255900b0099bcf1c07c6sm13716547ejb.138.2023.09.30.03.22.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Sep 2023 03:22:24 -0700 (PDT) From: Robert Marko To: ilia.lin@kernel.org, vireshk@kernel.org, nm@ti.com, sboyd@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, rafael@kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Cc: Christian Marangi , Robert Marko Subject: [PATCH v5 4/4] ARM: dts: qcom: ipq8064: Add CPU OPP table Date: Sat, 30 Sep 2023 12:21:19 +0200 Message-ID: <20230930102218.229613-4-robimarko@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230930102218.229613-1-robimarko@gmail.com> References: <20230930102218.229613-1-robimarko@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sat, 30 Sep 2023 03:25:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778483836084210279 X-GMAIL-MSGID: 1778483836084210279 From: Christian Marangi Add CPU OPP table for IPQ8062, IPQ8064 and IPQ8065 SoC. Use opp-supported-hw binding to correctly enable and disable the frequency as IPQ8062 supports up to 1.0Ghz, IPQ8064 supports up to 1.4GHz with 1.2GHz as an additional frequency and IPQ8065 supports 1.7GHZ but doesn't have 1.2GHZ frequency and has to be disabled. Signed-off-by: Christian Marangi Signed-off-by: Robert Marko --- Changes v4: * Add OPP DTS patch for IPQ8064 arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi | 30 +++++++++++ arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 67 ++++++++++++++++++++++++ arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi | 65 +++++++++++++++++++++++ 3 files changed, 162 insertions(+) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi index 5d3ebd3e2e51..72d9782c3d6f 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8062.dtsi @@ -6,3 +6,33 @@ / { model = "Qualcomm Technologies, Inc. IPQ8062"; compatible = "qcom,ipq8062", "qcom,ipq8064"; }; + +&opp_table_cpu { + opp-384000000 { + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <850000 807500 892500>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <995000 945250 1044750>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3 = <950000 902500 997500>; + }; +}; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 6198f42f6a9c..cbbd28b43dc4 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -30,6 +30,7 @@ cpu0: cpu@0 { next-level-cache = <&L2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; + operating-points-v2 = <&opp_table_cpu>; }; cpu1: cpu@1 { @@ -40,6 +41,7 @@ cpu1: cpu@1 { next-level-cache = <&L2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; + operating-points-v2 = <&opp_table_cpu>; }; L2: l2-cache { @@ -49,6 +51,71 @@ L2: l2-cache { }; }; + opp_table_cpu: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&speedbin_efuse>; + + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <925000 878750 971250>; + opp-microvolt-speed0-pvs2 = <875000 831250 918750>; + opp-microvolt-speed0-pvs3 = <800000 760000 840000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <850000 807500 892500>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <995000 945250 1044750>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt-speed0-pvs0 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs3 = <950000 902500 997500>; + opp-supported-hw = <0x7>; + clock-latency-ns = <100000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt-speed0-pvs0 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs1 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs2 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs3 = <1000000 950000 1050000>; + opp-supported-hw = <0x2>; + clock-latency-ns = <100000>; + }; + + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt-speed0-pvs0 = <1250000 1187500 1312500>; + opp-microvolt-speed0-pvs1 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs2 = <1125000 1068750 1181250>; + opp-microvolt-speed0-pvs3 = <1050000 997500 1102500>; + opp-supported-hw = <0x6>; + clock-latency-ns = <100000>; + }; + }; + thermal-zones { sensor0-thermal { polling-delay-passive = <0>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi index ea49f6cc416d..d9ead31b897b 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8065.dtsi @@ -6,3 +6,68 @@ / { model = "Qualcomm Technologies, Inc. IPQ8065"; compatible = "qcom,ipq8065", "qcom,ipq8064"; }; + +&opp_table_cpu { + opp-384000000 { + opp-microvolt-speed0-pvs0 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs1 = <950000 902500 997500>; + opp-microvolt-speed0-pvs2 = <925000 878750 971250>; + opp-microvolt-speed0-pvs3 = <900000 855000 945000>; + opp-microvolt-speed0-pvs4 = <875000 831250 918750>; + opp-microvolt-speed0-pvs5 = <825000 783750 866250>; + opp-microvolt-speed0-pvs6 = <775000 736250 813750>; + }; + + opp-600000000 { + opp-microvolt-speed0-pvs0 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs1 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs2 = <950000 902500 997500>; + opp-microvolt-speed0-pvs3 = <925000 878750 971250>; + opp-microvolt-speed0-pvs4 = <900000 855000 945000>; + opp-microvolt-speed0-pvs5 = <850000 807500 892500>; + opp-microvolt-speed0-pvs6 = <800000 760000 840000>; + }; + + opp-800000000 { + opp-microvolt-speed0-pvs0 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs1 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs2 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs3 = <975000 926250 1023750>; + opp-microvolt-speed0-pvs4 = <950000 902500 997500>; + opp-microvolt-speed0-pvs5 = <900000 855000 945000>; + opp-microvolt-speed0-pvs6 = <850000 807500 892500>; + }; + + opp-1000000000 { + opp-microvolt-speed0-pvs0 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs1 = <1075000 1021250 1128750>; + opp-microvolt-speed0-pvs2 = <1050000 997500 1102500>; + opp-microvolt-speed0-pvs3 = <1025000 973750 1076250>; + opp-microvolt-speed0-pvs4 = <1000000 950000 1050000>; + opp-microvolt-speed0-pvs5 = <950000 902500 997500>; + opp-microvolt-speed0-pvs6 = <900000 855000 945000>; + }; + + opp-1400000000 { + opp-microvolt-speed4-pvs0 = <1175000 1116250 1233750>; + opp-microvolt-speed4-pvs1 = <1150000 1092500 1207500>; + opp-microvolt-speed4-pvs2 = <1125000 1068750 1181250>; + opp-microvolt-speed4-pvs3 = <1100000 1045000 1155000>; + opp-microvolt-speed4-pvs4 = <1075000 1021250 1128750>; + opp-microvolt-speed4-pvs5 = <1025000 973750 1076250>; + opp-microvolt-speed4-pvs6 = <975000 926250 1023750>; + }; + + opp-1725000000 { + opp-hz = /bits/ 64 <1725000000>; + opp-microvolt-speed0-pvs0 = <1262500 1199375 1325625>; + opp-microvolt-speed0-pvs1 = <1225000 1163750 1286250>; + opp-microvolt-speed0-pvs2 = <1200000 1140000 1260000>; + opp-microvolt-speed0-pvs3 = <1175000 1116250 1233750>; + opp-microvolt-speed0-pvs4 = <1150000 1092500 1207500>; + opp-microvolt-speed0-pvs5 = <1100000 1045000 1155000>; + opp-microvolt-speed0-pvs6 = <1050000 997500 1102500>; + opp-supported-hw = <0x4>; + clock-latency-ns = <100000>; + }; +};