From patchwork Thu Sep 28 13:26:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Ball X-Patchwork-Id: 146112 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3311881vqu; Thu, 28 Sep 2023 06:28:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEacwDQeWSaIhgwMShPnVSd5iMPlu5ZOsbTA7FwCv9tZW6bBeeWVXiVwD/AeBOVTtfnwpnL X-Received: by 2002:a17:906:eb82:b0:9ae:69b3:3e18 with SMTP id mh2-20020a170906eb8200b009ae69b33e18mr1349377ejb.25.1695907727544; Thu, 28 Sep 2023 06:28:47 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id k7-20020a1709061c0700b009ae4e1743f6si12176197ejg.641.2023.09.28.06.28.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 06:28:47 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=eJhsOu8L; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=eJhsOu8L; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2767138618FA for ; Thu, 28 Sep 2023 13:28:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2054.outbound.protection.outlook.com [40.107.21.54]) by sourceware.org (Postfix) with ESMTPS id D21623858D20 for ; Thu, 28 Sep 2023 13:28:12 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D21623858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hkmTIACbk7RDvkR4YCsPc9/6VO2nCqw2GzIwjKtHQBw=; b=eJhsOu8LhvNcIzz34Lf3tyMmMQphjJtFEOeMqqE6wZ0oYREwLnECpKfmKWbqUbKnToJch1RcPnkO7bxxMpTtpHj/SB31hcFy7GkqvM4LU1OtQLV8WgS5aOPxAJWKyqpbDRIwWjiM5talabguZpQSLNeoR/9Om53lDATFUObAdm0= Received: from DUZPR01CA0188.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b6::27) by AS8PR08MB8136.eurprd08.prod.outlook.com (2603:10a6:20b:561::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.21; Thu, 28 Sep 2023 13:28:10 +0000 Received: from DBAEUR03FT004.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:4b6:cafe::da) by DUZPR01CA0188.outlook.office365.com (2603:10a6:10:4b6::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.23 via Frontend Transport; Thu, 28 Sep 2023 13:28:09 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT004.mail.protection.outlook.com (100.127.142.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.21 via Frontend Transport; Thu, 28 Sep 2023 13:28:09 +0000 Received: ("Tessian outbound 9aeaca65ec26:v211"); Thu, 28 Sep 2023 13:28:09 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 92f15cf0cfc4a1eb X-CR-MTA-TID: 64aa7808 Received: from 704b30f63e47.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id BD18F017-2CE3-4A8A-B051-25DFCC037EFA.1; Thu, 28 Sep 2023 13:27:09 +0000 Received: from EUR05-DB8-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 704b30f63e47.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 28 Sep 2023 13:27:09 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=GlfFHx/8ALFx5ccJ7tlM7+VvhgtaCeORBgz2kXltIads96FpFy41pNZOemsDvbF4+qWgSKJX1zaco/gRUES5dOdP/FINOXlM04HV/9RvZtkiSGFB3swOIKtxnwploDA+9l/DrIfMCVpvLjWRKtD++1QN2V4rlB47ZgRI/EQK+ekNfACWHLj+ztsQGuqFKuo/hSLOEM1XcOnw9MSJm/h1lyx8B5t/ljaSXoG/WTBMIvl4Myw2RtmF6Q87v+3KCG6S2qdNWfIecOUZ61cLTG3E9GC1Z93st06rorMdg4bVFCObaDSskFOl5vB+t3rpUgVB0Xucsn1x56DERuzsnKcKWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=hkmTIACbk7RDvkR4YCsPc9/6VO2nCqw2GzIwjKtHQBw=; b=khNY3kXmVshKceORURnNJaSvW/ir516Cy55tX+g9rTLBSZAHlNELEak2Ve+A0jpUi/6VgzK6uk9l2miXaPRhc0JNUyts3GNg0u7RdgWOwurOZCbrGkRr+3G5xxtpwxPA/VdxwZaqzBhdJ83kSuIya7bs9hqNLk0315+9u3zKRzBEBmcqAD4Vnib+zUmOImRFdybl9HtYnb8kyWYUa3VhPJMGYoExZibt99C5mb8pInJ97lJRqi74SZ1cMmL3EDRKOaCxYFlAEjbGfJnKsEFtCZBT0T9f3/Hlkc0TBdZlKzTnBHMbHPdZMVgbKfgLuFZ4dydw3npwyU8YU54LvhWzCw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hkmTIACbk7RDvkR4YCsPc9/6VO2nCqw2GzIwjKtHQBw=; b=eJhsOu8LhvNcIzz34Lf3tyMmMQphjJtFEOeMqqE6wZ0oYREwLnECpKfmKWbqUbKnToJch1RcPnkO7bxxMpTtpHj/SB31hcFy7GkqvM4LU1OtQLV8WgS5aOPxAJWKyqpbDRIwWjiM5talabguZpQSLNeoR/9Om53lDATFUObAdm0= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DB9PR08MB6957.eurprd08.prod.outlook.com (2603:10a6:10:2bc::10) by AS8PR08MB7885.eurprd08.prod.outlook.com (2603:10a6:20b:508::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.28; Thu, 28 Sep 2023 13:27:07 +0000 Received: from DB9PR08MB6957.eurprd08.prod.outlook.com ([fe80::466d:46ab:e188:aead]) by DB9PR08MB6957.eurprd08.prod.outlook.com ([fe80::466d:46ab:e188:aead%3]) with mapi id 15.20.6813.027; Thu, 28 Sep 2023 13:27:07 +0000 Message-ID: <67cc0ed4-bb90-932f-10d6-5dc76ec46561@arm.com> Date: Thu, 28 Sep 2023 14:26:30 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 From: Richard Ball Content-Language: en-US To: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Kyrylo Tkachov , ramana.gcc@gmail.com, Nick Clifton Subject: [PATCH 1/2] arm: Use deltas for Arm switch tables X-ClientProxiedBy: LO4P265CA0023.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2ae::13) To DB9PR08MB6957.eurprd08.prod.outlook.com (2603:10a6:10:2bc::10) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR08MB6957:EE_|AS8PR08MB7885:EE_|DBAEUR03FT004:EE_|AS8PR08MB8136:EE_ X-MS-Office365-Filtering-Correlation-Id: 0deeb7b8-a9a2-4f81-e456-08dbc026c1f9 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: UgfetprWVXOehnaNFMk04IyguUJsNUcJubWd+2zSDJHxkb0To/0FYmSDsdJ7b4nMQB7OhlVkzAyuER6YN5yKJViK9mlx2SSYPk8ObObgrL3Idj0eGQoJDuOQ1jo5oTG3JYAx/4nYESrygKruTrcG+EKz/w+VbuPWZY8RBIKPpsPZSNFaG99BRmvg0viSBVapRtMt/vZAfmOJEV3ehjOruRsCC2eILvXmiOb7R+DUcDPipCf1hz2EOb8GkHHgCpuY1Ij6jm0/rYErCqdx5vA2h+hxmlgRhCPs9Il8lskFxu53YBA7oy5TpQUGSlTJEu2UPdK6V/x/VDJXUdfscCKoS3fkjRcro7I2EFMtb6NrFNO0SP+f8gnBhip9l9OSuk8RctRL/Wp+mVbRB4P3QDVicMLXrl30ziWZEsnX0yaAYWxd3VuBPdX8ZSoGiGRaOd6gmDJyOOP5e6gsfmVvVV33IOccpJjdFriv+1hwq/Z3taYS0d1aVzshENoe2PCERk0XOPoxbempCen/4xkjb7g0HNIWUYXImJwuLXh9arVlhNf/giT+w9Hmk9MNcPt33L7+mZq/d/6/waTon7DBwOHM9ptFHBcL/8E8P0y3hnHHlC0ahFyXApanfgR8rXj5B+5ti5O4XTKBQq5U4DyYCYG3Ew== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DB9PR08MB6957.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(346002)(366004)(376002)(396003)(39860400002)(136003)(230922051799003)(64100799003)(451199024)(1800799009)(186009)(84970400001)(235185007)(31686004)(66946007)(5660300002)(2906002)(41300700001)(316002)(8936002)(44832011)(6506007)(8676002)(36756003)(66556008)(110136005)(86362001)(2616005)(478600001)(33964004)(26005)(6486002)(6666004)(6512007)(38100700002)(31696002)(66476007)(43740500002)(45980500001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB7885 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 2dd5df96-f54a-4dfe-b9c0-08dbc0269c78 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ibimoI0uZzKn4tR1+11a+H9BxrjgaVFIa1rgttEoS/U+zMOXLeAiujdfWnysfWzf9xD0VkvWq+e7+4mREETLS4WUEf2T3Sxaa6Y2DrvuZpGZ3vlDShQ4xFpp/eK560hxrZ967VK8BPEWN47uirKraKSW6m+AbxqVm6v5KDb9uG+lbNPOTmig0PCkA2I1epGk8kRom/gHguuG4wSHpLtwvaz8Jo8TPLIuyqNIMpwKf/viW/7jfWccr+hrP6Z20N/jgeAZUuNOUCPzEs1vgJb7HSoI7GYLGnRsaEF2HwPF8MwrIOp/bjPc9AQwSws/T9VcGGEacWXJXLNxO60Q8RdWlXNYG3GQHSFbhUUf4nvKySEOxUql1bhrpF3s5U7CV8yVBNM2a+A58Sv6zHPLkK/IcgP96FRut2Z7co/8y4ahugqkSqKWYhnuUnsAfBV5TuUIG9vnP2cVE3TPOSrhTRJue9d7tw6r2xmFn0z8STYWjK6onOsQKdkdC6z7WCIn6N4Bs3ezn+hU5r/SpUpHCI64N/u1tFjidj0w/v6OqKbpOZ+LLBfmigIXkvoKCDFG7jpmK3RXiHVNzqbuc+HZAmz6sZCmvXkb7vssqGRh1/HKyiDTV/M2TxPg+TgEnKKEbHYmNRMnDfJQBTSA73qbhcmyk5dcKz/r+LZzURW/Y1B2li7E/OIao1dx2xgGv6uJ6+DBnCwQkJmzNBZuTQ/RHf33VpPTezkzsaaTR5Tw0dKcW900LvZZz1sdU769HJo6uKt8Hmyjw/v7oYN6frPKBQDHGg== X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(136003)(376002)(396003)(39860400002)(346002)(230922051799003)(82310400011)(64100799003)(1800799009)(451199024)(186009)(40470700004)(46966006)(36840700001)(84970400001)(2906002)(235185007)(31686004)(44832011)(8936002)(8676002)(5660300002)(36756003)(336012)(2616005)(41300700001)(316002)(70206006)(70586007)(40460700003)(110136005)(26005)(6666004)(33964004)(6506007)(6512007)(6486002)(47076005)(478600001)(36860700001)(40480700001)(81166007)(356005)(31696002)(82740400003)(86362001)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2023 13:28:09.8726 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0deeb7b8-a9a2-4f81-e456-08dbc026c1f9 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT004.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8136 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778288141303888324 X-GMAIL-MSGID: 1778288141303888324 For normal optimization for the Arm state in gcc we get an uncompressed table of jump targets. This is in the middle of the text segment far larger than necessary, especially at -Os. This patch compresses the table to use deltas in a similar manner to Thumb code generation. Similar code is also used for -fpic where we currently generate a jump to a jump. In this format the jumps are too dense for the hardware branch predictor to handle accurately, so execution is likely to be very expensive. Changes to switch statements for arm include a new function to handle the assembly generation for different machine modes. This allows for more optimisation to be performed in aout.h where arm has switched from using ASM_OUTPUT_ADDR_VEC_ELT to using ASM_OUTPUT_ADDR_DIFF_ELT. In ASM_OUTPUT_ADDR_DIFF_ELT new assembly generation options have been added to utilise the different machine modes. Additional changes made to the casesi expand and insn, CASE_VECTOR_PC_RELATIVE, CASE_VECTOR_SHORTEN_MODE and LABEL_ALIGN_AFTER_BARRIER are all to accomodate this new approach to switch statement generation. New tests have been added and no regressions on arm-none-eabi. gcc/ChangeLog: * config/arm/aout.h (ASM_OUTPUT_ADDR_DIFF_ELT): Add table output for different machine modes for arm. * config/arm/arm-protos.h (arm_output_casesi): New prototype. * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Make arm use ASM_OUTPUT_ADDR_DIFF_ELT. (CASE_VECTOR_SHORTEN_MODE): Change table size calculation for TARGET_ARM. (LABEL_ALIGN_AFTER_BARRIER): Change to accommodate .p2align 2 for TARGET_ARM. * config/arm/arm.cc (arm_output_casesi): New function. * config/arm/arm.md (arm_casesi_internal): Change casesi expand and insn. for arm to use new function arm_output_casesi. gcc/testsuite/ChangeLog: * gcc.target/arm/arm-switchstatement.c: New test. Reviewed-by: rearnsha@arm.com diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index 57c3b9b7b8b02f15e191ffcb9446f0edf27bbce6..6a4c8da5f6d5a1695518f42830b9d045888eeed6 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -183,7 +183,28 @@ do \ { \ if (TARGET_ARM) \ - asm_fprintf (STREAM, "\tb\t%LL%d\n", VALUE); \ + { \ + switch (GET_MODE (body)) \ + { \ + case E_QImode: \ + asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d-4)/4\n", \ + VALUE, REL); \ + break; \ + case E_HImode: \ + asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d-4)/4\n", \ + VALUE, REL); \ + break; \ + case E_SImode: \ + if (flag_pic) \ + asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d-4\n", \ + VALUE, REL); \ + else \ + asm_fprintf (STREAM, "\t.word\t%LL%d\n", VALUE); \ + break; \ + default: \ + gcc_unreachable (); \ + } \ + } \ else if (TARGET_THUMB1) \ { \ if (flag_pic || optimize_size) \ diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 77e76336e94096975093c0c7c72a005993a4c27d..2f5ca79ed8ddd647b212782a0454ee4fefc07257 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -261,6 +261,7 @@ extern void thumb_expand_cpymemqi (rtx *); extern rtx arm_return_addr (int, rtx); extern void thumb_reload_out_hi (rtx *); extern void thumb_set_return_address (rtx, rtx); +extern const char *arm_output_casesi (rtx *); extern const char *thumb1_output_casesi (rtx *); extern const char *thumb2_output_casesi (rtx *); #endif diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 4f54530adcb616413bf210dff8c43f0f2046fd3d..3063e3489094f04ecf03a52952c185d4a75da645 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2092,7 +2092,7 @@ enum arm_auto_incmodes for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE Pmode -#define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ +#define CASE_VECTOR_PC_RELATIVE ((TARGET_ARM || TARGET_THUMB2 \ || (TARGET_THUMB1 \ && (optimize_size || flag_pic))) \ && (!target_pure_code)) @@ -2109,9 +2109,19 @@ enum arm_auto_incmodes : min >= -4096 && max < 4096 \ ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ : SImode) \ - : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ - : (max >= 0x200) ? HImode \ - : QImode)) + : (TARGET_THUMB2 \ + ? ((min > 0 && max < 0x200) ? QImode \ + : (min > 0 && max <= 0x20000) ? HImode \ + : SImode) \ + : ((min >= 0 && max < 1024) \ + ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ + : (min >= -512 && max <= 508) \ + ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ + :(min >= 0 && max < 262144) \ + ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ + : (min >= -131072 && max <=131068) \ + ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ + : SImode))) /* signed 'char' is most compatible, but RISC OS wants it unsigned. unsigned is probably best, but may break some code. */ @@ -2301,7 +2311,7 @@ extern int making_const_table; #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ - ? 1 : 0) + ? (TARGET_ARM ? 2 : 1) : 0) #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ arm_declare_function_name ((STREAM), (NAME), (DECL)); diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 6e933c801838bb8fad32fa42d3eb32a817cdaf22..4e5e6997ed555372683e01b2aff5c25265f4e50c 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -30464,6 +30464,51 @@ arm_output_iwmmxt_tinsr (rtx *operands) return ""; } +/* Output an arm casesi dispatch sequence. Used by arm_casesi_internal insn. + Responsible for the handling of switch statements in arm. */ +const char * +arm_output_casesi (rtx *operands) +{ + rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[2]))); + + gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); + + output_asm_insn ("cmp\t%0, %1", operands); + output_asm_insn ("bhi\t%l3", operands); + switch (GET_MODE (diff_vec)) + { + case E_QImode: + output_asm_insn ("adr\t%4, %l2", operands); + if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) + output_asm_insn ("ldrb\t%4, [%4, %0]", operands); + else + output_asm_insn ("ldrsb\t%4, [%4, %0]", operands); + return "add\t%|pc, %|pc, %4, lsl #2"; + + case E_HImode: + output_asm_insn ("adr\t%4, %l2", operands); + output_asm_insn ("add\t%4, %4, %0", operands); + if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) + output_asm_insn ("ldrh\t%4, [%4, %0]", operands); + else + output_asm_insn ("ldrsh\t%4, [%4, %0]", operands); + return "add\t%|pc, %|pc, %4, lsl #2"; + + case E_SImode: + if (flag_pic) + { + output_asm_insn ("adr\t%4, %l2", operands); + output_asm_insn ("ldr\t%4, [%4, %0, lsl #2]", operands); + return "add\t%|pc, %|pc, %4"; + } + output_asm_insn ("adr\t%4, %l2", operands); + return "ldr\t%|pc, [%4, %0, lsl #2]"; + + default: + gcc_unreachable (); + } +} + /* Output a Thumb-1 casesi dispatch sequence. */ const char * thumb1_output_casesi (rtx *operands) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 2ac97232ffd2c030cc3f231cb21e4fcc42f5d5b8..0b2eb4bce92bb7e8b1ca0c5a04b1a52e9c16b64a 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -9556,6 +9556,8 @@ (match_dup 4) (label_ref:SI (match_operand 3 "")))) (clobber (reg:CC CC_REGNUM)) + (clobber (match_scratch:SI 5)) + (clobber (match_scratch:SI 6)) (use (label_ref:SI (match_operand 2 "")))])] "TARGET_ARM" { @@ -9576,15 +9578,15 @@ (label_ref:SI (match_operand 2 "" "")))) (label_ref:SI (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM)) + (clobber (match_scratch:SI 4 "=&r")) + (clobber (match_scratch:SI 5 "=r")) (use (label_ref:SI (match_dup 2)))])] "TARGET_ARM" - "* - if (flag_pic) - return \"cmp\\t%0, %1\;addls\\t%|pc, %|pc, %0, asl #2\;b\\t%l3\"; - return \"cmp\\t%0, %1\;ldrls\\t%|pc, [%|pc, %0, asl #2]\;b\\t%l3\"; - " + { + return arm_output_casesi (operands); + } [(set_attr "conds" "clob") - (set_attr "length" "12") + (set_attr "length" "24") (set_attr "type" "multiple")] ) diff --git a/gcc/testsuite/gcc.target/arm/arm-switchstatement.c b/gcc/testsuite/gcc.target/arm/arm-switchstatement.c new file mode 100644 index 0000000000000000000000000000000000000000..a7aa9d45c7634db6c8192072019e497db969b681 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/arm-switchstatement.c @@ -0,0 +1,151 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --param case-values-threshold=1 -fno-reorder-blocks -fno-tree-dce" } */ +/* { dg-require-effective-target arm_nothumb } */ +/* { dg-final { check-function-bodies "**" "" "" } } */ + +#define NOP "nop;" +#define NOP2 NOP NOP +#define NOP4 NOP2 NOP2 +#define NOP8 NOP4 NOP4 +#define NOP16 NOP8 NOP8 +#define NOP32 NOP16 NOP16 +#define NOP64 NOP32 NOP32 +#define NOP128 NOP64 NOP64 +#define NOP256 NOP128 NOP128 +#define NOP512 NOP256 NOP256 +#define NOP1024 NOP512 NOP512 +#define NOP2048 NOP1024 NOP1024 +#define NOP4096 NOP2048 NOP2048 +#define NOP8192 NOP4096 NOP4096 +#define NOP16384 NOP8192 NOP8192 +#define NOP32768 NOP16384 NOP16384 +#define NOP65536 NOP32768 NOP32768 +#define NOP131072 NOP65536 NOP65536 + +enum z +{ + a = 1, + b, + c, + d, + e, + f = 7, +}; + +inline void QIFunction (const char* flag) +{ + asm volatile (NOP32); + return; +} + +inline void HIFunction (const char* flag) +{ + asm volatile (NOP512); + return; +} + +inline void SIFunction (const char* flag) +{ + asm volatile (NOP131072); + return; +} + +/* +**QImode_test: +** ... +** adr (r[0-9]+), .L[0-9]+ +** ldrb \1, \[\1, r[0-9]+\] +** add pc, pc, \1, lsl #2 +** ... +*/ +__attribute__ ((noinline)) __attribute__ ((noclone)) const char* QImode_test(enum z x) +{ + switch (x) + { + case d: + QIFunction("QItest"); + return "InlineASM"; + case f: + return "TEST"; + default: + return "Default"; + } +} + +/* { dg-final { scan-assembler ".byte" } } */ + +/* +**HImode_test: +** ... +** adr (r[0-9]+), .L[0-9]+ +** add \1, \1, (r[0-9]+) +** ldrh \1, \[\1, \2\] +** add pc, pc, \1, lsl #2 +** ... +*/ +__attribute__ ((noinline)) __attribute__ ((noclone)) const char* HImode_test(enum z x) +{ + switch (x) + { + case d: + HIFunction("HItest"); + return "InlineASM"; + case f: + return "TEST"; + default: + return "Default"; + } +} + +/* { dg-final { scan-assembler ".2byte" } } */ + +/* +**SImode_test: +** ... +** adr (r[0-9]+), .L[0-9]+ +** ldr pc, \[\1, r[0-9]+, lsl #2\] +** ... +*/ +__attribute__ ((noinline)) __attribute__ ((noclone)) const char* SImode_test(enum z x) +{ + switch (x) + { + case d: + SIFunction("SItest"); + return "InlineASM"; + case f: + return "TEST"; + default: + return "Default"; + } +} + +/* { dg-final { scan-assembler ".word" } } */ + +/* +**backwards_branch_test: +** ... +** adr (r[0-9]+), .L[0-9]+ +** add \1, \1, (r[0-9]+) +** ldrsh \1, \[\1, \2\] +** add pc, pc, \1, lsl #2 +** ... +*/ +__attribute__ ((noinline)) __attribute__ ((noclone)) const char* backwards_branch_test(enum z x, int flag) +{ + if (flag == 5) + { + backwards: + asm volatile (NOP512); + return "ASM"; + } + switch (x) + { + case d: + goto backwards; + case f: + return "TEST"; + default: + return "Default"; + } +} \ No newline at end of file From patchwork Thu Sep 28 13:29:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Ball X-Patchwork-Id: 146115 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3313694vqu; Thu, 28 Sep 2023 06:31:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHUt3rGkymAeGdWHXagYmSG0TWIzO+N5gskNV3XyB7XxnANfxIwOg+lKzoCJ/x13yfN5P3c X-Received: by 2002:a17:907:8692:b0:9ad:e62c:4517 with SMTP id qa18-20020a170907869200b009ade62c4517mr1456198ejc.34.1695907882094; Thu, 28 Sep 2023 06:31:22 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id l12-20020a170906078c00b00993ebae9929si16181461ejc.708.2023.09.28.06.31.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 06:31:22 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=jl+XoRFd; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=jl+XoRFd; arc=fail (signature failed); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4871038654A3 for ; Thu, 28 Sep 2023 13:31:13 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR05-VI1-obe.outbound.protection.outlook.com (mail-vi1eur05on2063.outbound.protection.outlook.com [40.107.21.63]) by sourceware.org (Postfix) with ESMTPS id 7FC753858D20 for ; Thu, 28 Sep 2023 13:30:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7FC753858D20 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vijm2qySmNM1g3JY5xSJ+QkWNqOUVWPLbcq86x29ESc=; b=jl+XoRFdjtvL1mQEilbnWahBGhrhR2Tx71TpliOiuEH2lfrZpBg9sN7DeeLsGYrgpY9H8frCOZbtTOR3W8PngeUzT1DMIRDXLWx5xpTFsGLNpCocTP7M0QYt2ofbHEcdiAaPg0/Wp7tTvfcUSAiCZGIOjMFbhtX+jVBVNlUucQw= Received: from DB8PR03CA0035.eurprd03.prod.outlook.com (2603:10a6:10:be::48) by AS8PR08MB8875.eurprd08.prod.outlook.com (2603:10a6:20b:5b7::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.28; Thu, 28 Sep 2023 13:30:45 +0000 Received: from DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com (2603:10a6:10:be:cafe::99) by DB8PR03CA0035.outlook.office365.com (2603:10a6:10:be::48) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.21 via Frontend Transport; Thu, 28 Sep 2023 13:30:44 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by DBAEUR03FT005.mail.protection.outlook.com (100.127.142.81) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6838.25 via Frontend Transport; Thu, 28 Sep 2023 13:30:44 +0000 Received: ("Tessian outbound 6d14f3380669:v211"); Thu, 28 Sep 2023 13:30:44 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: a99f246f08777e10 X-CR-MTA-TID: 64aa7808 Received: from b8b3f2c9b942.2 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 3DF0B10D-FBA1-441F-8862-4B2D7483C15A.1; Thu, 28 Sep 2023 13:30:08 +0000 Received: from EUR02-VI1-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id b8b3f2c9b942.2 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Thu, 28 Sep 2023 13:30:08 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=XXXKlKycmL2T0Fnoy8ftNdT6sQBgtVtwOXKdvJOHMy4LwBbxSENgBrUEXYWlI6alnBqYzKAnvrMbFPIRvOd5j6Xc39qpzr13N7hd6q9xWDPhKghdY3JLQQG7AxkBS3Od5kfHWVCqbCQfMuq+OgI6wvGHO4noBbyAmn/RHn35djDXu7nD0bQONhgrrH/MYdnbLMyl1CK4q8Ei5Jq1rbDk6DpDiTcKef3lEYaUUuqe1lOx4lEyxz/TuZiyUe9+UNrAQBz5ru74QfSTk0YR1eGZDEc5aTFI9buxfNykxPu/PRGbk5bAraRgUw/tic0Nk9WgGFw2TSmunYgomnQMOCg9QQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=vijm2qySmNM1g3JY5xSJ+QkWNqOUVWPLbcq86x29ESc=; b=K/NZsrHZ+C5KH7+T60Wa/cpjrNpP+DTI5VDiJsjGm9cDCjEnTeFiMAnPO+czCUF3acD88gFnzMNSIWxmgxJxx1NaTgpFDK0r8lCqjpNdfM4PMj8p9zRWJH26LwEN5NQpc+MPnMOxcO+9ybz04NCMWJ6dNrHH0lKK/D+1AzE14EHYCFCuyS4nxpEi760g9UG0ktp7Z837EOscsQb/fcLv2q/PpGGi4fXqzbUFN2cxkI6QklFnWn4c6M22pLmrD3FCqxeb+kxyGxRfAR6YKmZ/SDl2NU3F1a6mCuS0Nr2CeaYgPD4Yh/5OSicB6ysshyQOao70Bu4kkoC1+QEq+7JDKw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=vijm2qySmNM1g3JY5xSJ+QkWNqOUVWPLbcq86x29ESc=; b=jl+XoRFdjtvL1mQEilbnWahBGhrhR2Tx71TpliOiuEH2lfrZpBg9sN7DeeLsGYrgpY9H8frCOZbtTOR3W8PngeUzT1DMIRDXLWx5xpTFsGLNpCocTP7M0QYt2ofbHEcdiAaPg0/Wp7tTvfcUSAiCZGIOjMFbhtX+jVBVNlUucQw= Authentication-Results-Original: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; Received: from DB9PR08MB6957.eurprd08.prod.outlook.com (2603:10a6:10:2bc::10) by AS8PR08MB8327.eurprd08.prod.outlook.com (2603:10a6:20b:56e::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6813.20; Thu, 28 Sep 2023 13:30:05 +0000 Received: from DB9PR08MB6957.eurprd08.prod.outlook.com ([fe80::466d:46ab:e188:aead]) by DB9PR08MB6957.eurprd08.prod.outlook.com ([fe80::466d:46ab:e188:aead%3]) with mapi id 15.20.6813.027; Thu, 28 Sep 2023 13:30:05 +0000 Message-ID: <0058d74e-70ba-9b8e-adef-2df01569885d@arm.com> Date: Thu, 28 Sep 2023 14:29:28 +0100 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 From: Richard Ball Content-Language: en-US To: "gcc-patches@gcc.gnu.org" , Richard Earnshaw , Kyrylo Tkachov , Nick Clifton , ramana.gcc@gmail.com Subject: [PATCH 2/2] arm: move the switch tables for Arm to the RO data section. X-ClientProxiedBy: LO2P265CA0399.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:f::27) To DB9PR08MB6957.eurprd08.prod.outlook.com (2603:10a6:10:2bc::10) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: DB9PR08MB6957:EE_|AS8PR08MB8327:EE_|DBAEUR03FT005:EE_|AS8PR08MB8875:EE_ X-MS-Office365-Filtering-Correlation-Id: a657c2ad-69c7-4562-da0c-08dbc0271e62 X-LD-Processed: f34e5979-57d9-4aaa-ad4d-b122a662184d,ExtAddr x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: 0eRT1RUFmNLXp3bqrHD7bhhwz7fjziArdrFYcxb20fTaLEIFbKbZcli7jlGdrQG/1FkmhHfT9tuAw91Y2cvZn11+znhcQAqwwMQ+E0KI0ggubiEpi3io38cFsF7GM01KGCf8PZE6AgONZ53KA0JqYGgn4kU6u9idBOa3qX7/2QtSTIOqhwU1lGA5Wo5uyWhMe1Ftlran3ntYCrLa0ARQeTkn8tDg+haiCSp4g/Bh8mDcklHwV+QFnTitUgwNC7w6gxCbeOilyS/JXTItC9JQ2rWgsoho9uwmCcFxDOyz+8wUQJ6RQbS7DOEDDFVHdTQxopkA44HqBy48a/BYDZoZYXYr5T9azAX2267FRxBQDiHRPHvjTT3O+bo/lqOdql3MFvIzd6Q/7Mrs/q3GNpnaB1BpdgWQigcuRmTIHGXF6etkUYO26IEXPAWWgJ3t0Dz5IMIRgAFm5AYdp0/OOfs9vF45GZtviiH6moQCUPUPEEzZV60fs39NMjuaN6Mwc5J11j3A+12HOvhyihaOuC25Q644y4OGxvBK/eG7P5XQTNLckjsCXKBQfCjU6h831kDe82w+F50VK6FwFjHZdbStBDUjafiYQk4gazBD6PXgbB782JL+oaExy9jmT9cMOxux7rz8CKn59po4HovzwSn6dg== X-Forefront-Antispam-Report-Untrusted: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:DB9PR08MB6957.eurprd08.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230031)(396003)(376002)(136003)(366004)(346002)(39860400002)(230922051799003)(64100799003)(451199024)(1800799009)(186009)(6486002)(6506007)(6666004)(36756003)(33964004)(66476007)(2906002)(110136005)(8936002)(8676002)(316002)(235185007)(44832011)(66946007)(41300700001)(5660300002)(26005)(66556008)(6512007)(38100700002)(86362001)(478600001)(2616005)(31696002)(84970400001)(31686004)(43740500002)(45980500001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8327 Original-Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=arm.com; X-EOPAttributedMessage: 0 X-MS-Exchange-Transport-CrossTenantHeadersStripped: DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 06e7c2b3-acf9-49ac-9704-08dbc0270703 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MffBIgoVaFFhavIBk8vQHY5lENdwFo5p+wUORTcczFEsGyfM3THCkMP2+NAOKGH3gLWExhnD3j94l+gXIDzrNbDqH0NfsNs8dcYvl178QpnBycPUPf/mlxKvxBWq7/OghiVveBDskujt4ugt4wRQ4CbEc4IoXxZIpK1cInLpL+FFBUR35AYtbqPAi7t7WQoNLCjXDtYfg4swvrrcsZCrqUDWqRDorSpuYO00CCazRVkDZy6dhfZaYJChd5t67L0o1nsZkUZEgEpRtK52T3/At/X4x3BNungKfLGhqbHdv/wQgoha12CCGEjhRHXtz/WMM1zjXv+fg0rQK8b2VJeeSCZJaq/Y2TyEyxYntcCdVYo8npYUqNKVdhJ+humy6laTKeJCNbTuodUvjfUN5UxBWqiqTHAIZtPKTZz2o32qmgu2rWB+zicWDsoMUo+GBCU8zDVVGkOBzRZzvDPoTk6jo6pQ0ocopv7l5itCZEqCc47/ePkQvmW40RVh8rCSbvdvxlAurwGWp8XP1zRMym98Otn/iu/hLECzQEwjPi6yJT9LuEUOqsRr4CqvzS/j8uH4kiFkIHcadnmmUFrrLhM8aS+ZNoULU1zy3xbTZ7w4AVIAuisAJ5I7wU1JTU288ZHfcYak3UHejmJA31DczZjWTgbuIj+LSkTkxz3+ylDPMAMqdZ/weAKMg7fG0UAfEeFi5RmsK3E7XLStStNbznzm6ponTlUKJMpSwmOJZ8h7nNXbGdsmP3wNtwarDQ5gNPWp X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(376002)(136003)(346002)(396003)(39860400002)(230922051799003)(451199024)(186009)(64100799003)(1800799009)(82310400011)(36840700001)(40470700004)(46966006)(110136005)(8676002)(316002)(41300700001)(31686004)(84970400001)(235185007)(70206006)(70586007)(40480700001)(6512007)(8936002)(2906002)(44832011)(478600001)(40460700003)(6666004)(26005)(5660300002)(6486002)(33964004)(47076005)(6506007)(81166007)(336012)(2616005)(86362001)(36860700001)(356005)(82740400003)(31696002)(36756003)(43740500002); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2023 13:30:44.8953 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a657c2ad-69c7-4562-da0c-08dbc0271e62 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DBAEUR03FT005.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB8875 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778288303333635354 X-GMAIL-MSGID: 1778288303333635354 Follow up patch to arm: Use deltas for Arm switch tables This patch moves the switch tables for Arm from the .text section into the .rodata section. gcc/ChangeLog: * config/arm/aout.h: Change to use the Lrtx label. * config/arm/arm.h (CASE_VECTOR_PC_RELATIVE): Remove arm targets from (!target_pure_code) condition. (ADDR_VEC_ALIGN): Add align for tables in rodata section. * config/arm/arm.cc (arm_output_casesi): Alter the function to include .Lrtx label and remove adr instructions. * config/arm/arm.md (arm_casesi_internal): Use force_reg to generate ldr instructions that would otherwise be out of range, and change rtl to accommodate force reg. Additionally remove unnecessary register temp. (casesi): Remove pure code check for Arm. * config/arm/elf.h (JUMP_TABLES_IN_TEXT_SECTION): Remove arm targets from JUMP_TABLES_IN_TEXT_SECTION definition. gcc/testsuite/ChangeLog: * gcc.target/arm/arm-switchstatement.c: Alter the tests to change adr instruction to ldr. diff --git a/gcc/config/arm/aout.h b/gcc/config/arm/aout.h index 6a4c8da5f6d5a1695518f42830b9d045888eeed6..49896bb962081a5ee4b5328029813c681c489a9e 100644 --- a/gcc/config/arm/aout.h +++ b/gcc/config/arm/aout.h @@ -187,16 +187,16 @@ switch (GET_MODE (body)) \ { \ case E_QImode: \ - asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LL%d-4)/4\n", \ + asm_fprintf (STREAM, "\t.byte\t(%LL%d-%LLrtx%d-4)/4\n", \ VALUE, REL); \ break; \ case E_HImode: \ - asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LL%d-4)/4\n", \ + asm_fprintf (STREAM, "\t.2byte\t(%LL%d-%LLrtx%d-4)/4\n", \ VALUE, REL); \ break; \ case E_SImode: \ if (flag_pic) \ - asm_fprintf (STREAM, "\t.word\t%LL%d-%LL%d-4\n", \ + asm_fprintf (STREAM, "\t.word\t%LL%d-%LLrtx%d-4\n", \ VALUE, REL); \ else \ asm_fprintf (STREAM, "\t.word\t%LL%d\n", VALUE); \ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 3063e3489094f04ecf03a52952c185d4a75da645..ba61cf6fb9e4969776b49b499ce2205a940385d0 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2092,10 +2092,10 @@ enum arm_auto_incmodes for the index in the tablejump instruction. */ #define CASE_VECTOR_MODE Pmode -#define CASE_VECTOR_PC_RELATIVE ((TARGET_ARM || TARGET_THUMB2 \ +#define CASE_VECTOR_PC_RELATIVE (TARGET_ARM || ((TARGET_THUMB2 \ || (TARGET_THUMB1 \ && (optimize_size || flag_pic))) \ - && (!target_pure_code)) + && (!target_pure_code))) #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ @@ -2301,8 +2301,14 @@ extern int making_const_table; asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ } while (0) -#define ADDR_VEC_ALIGN(JUMPTABLE) \ - ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) +/* If the switch table is in the code segment, additional alignment is + needed for Thumb SImode tables. Otherwise, tables in RO data have + natural alignment. */ +#define ADDR_VEC_ALIGN(TABLE) \ + (JUMP_TABLES_IN_TEXT_SECTION \ + ? ((TARGET_THUMB && GET_MODE (PATTERN (TABLE)) == SImode) ? 2 : 0) \ + : (exact_log2 (GET_MODE_ALIGNMENT (GET_MODE (PATTERN (TABLE))) \ + / BITS_PER_UNIT))) /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the default alignment from elfos.h. */ diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 4e5e6997ed555372683e01b2aff5c25265f4e50c..c3a5ef274276cdef1b41690eb0ad7fd4f4218ecf 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -30469,44 +30469,58 @@ arm_output_iwmmxt_tinsr (rtx *operands) const char * arm_output_casesi (rtx *operands) { + char buf[100]; + char label[100]; rtx diff_vec = PATTERN (NEXT_INSN (as_a (operands[2]))); - gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC); - output_asm_insn ("cmp\t%0, %1", operands); output_asm_insn ("bhi\t%l3", operands); + ASM_GENERATE_INTERNAL_LABEL (label, "Lrtx", CODE_LABEL_NUMBER (operands[2])); switch (GET_MODE (diff_vec)) { case E_QImode: - output_asm_insn ("adr\t%4, %l2", operands); if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) - output_asm_insn ("ldrb\t%4, [%4, %0]", operands); + output_asm_insn ("ldrb\t%4, [%5, %0]", operands); else - output_asm_insn ("ldrsb\t%4, [%4, %0]", operands); - return "add\t%|pc, %|pc, %4, lsl #2"; - + output_asm_insn ("ldrsb\t%4, [%5, %0]", operands); + output_asm_insn ("add\t%|pc, %|pc, %4, lsl #2", operands);; + break; case E_HImode: - output_asm_insn ("adr\t%4, %l2", operands); - output_asm_insn ("add\t%4, %4, %0", operands); - if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) - output_asm_insn ("ldrh\t%4, [%4, %0]", operands); - else - output_asm_insn ("ldrsh\t%4, [%4, %0]", operands); - return "add\t%|pc, %|pc, %4, lsl #2"; - + if (REGNO (operands[4]) != REGNO (operands[5])) + { + output_asm_insn ("add\t%4, %0, %0", operands); + if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) + output_asm_insn ("ldrh\t%4, [%5, %4]", operands); + else + output_asm_insn ("ldrsh\t%4, [%5, %4]", operands); + } + else + { + output_asm_insn ("add\t%4, %5, %0", operands); + if (ADDR_DIFF_VEC_FLAGS (diff_vec).offset_unsigned) + output_asm_insn ("ldrh\t%4, [%4, %0]", operands); + else + output_asm_insn ("ldrsh\t%4, [%4, %0]", operands); + } + output_asm_insn ("add\t%|pc, %|pc, %4, lsl #2", operands); + break; case E_SImode: if (flag_pic) { - output_asm_insn ("adr\t%4, %l2", operands); - output_asm_insn ("ldr\t%4, [%4, %0, lsl #2]", operands); - return "add\t%|pc, %|pc, %4"; + output_asm_insn ("ldr\t%4, [%5, %0, lsl #2]", operands); + output_asm_insn ("add\t%|pc, %|pc, %4", operands); } - output_asm_insn ("adr\t%4, %l2", operands); - return "ldr\t%|pc, [%4, %0, lsl #2]"; - + else + { + output_asm_insn ("ldr\t%|pc, [%5, %0, lsl #2]", operands); + } + break; default: gcc_unreachable (); } + assemble_label (asm_out_file, label); + output_asm_insn ("nop;", operands); + return ""; } /* Output a Thumb-1 casesi dispatch sequence. */ diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 0b2eb4bce92bb7e8b1ca0c5a04b1a52e9c16b64a..810d862df7f343f2e4f5f11af3f6061b41ca3606 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -9514,7 +9514,8 @@ (match_operand:SI 2 "const_int_operand") ; total range (match_operand:SI 3 "" "") ; table label (match_operand:SI 4 "" "")] ; Out of range label - "(TARGET_32BIT || optimize_size || flag_pic) && !target_pure_code" + "TARGET_ARM || ((TARGET_THUMB2 || optimize_size || flag_pic) && + (!target_pure_code))" " { enum insn_code code; @@ -9557,13 +9558,13 @@ (label_ref:SI (match_operand 3 "")))) (clobber (reg:CC CC_REGNUM)) (clobber (match_scratch:SI 5)) - (clobber (match_scratch:SI 6)) (use (label_ref:SI (match_operand 2 "")))])] "TARGET_ARM" { + rtx tmp = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[2])); operands[4] = gen_rtx_MULT (SImode, operands[0], GEN_INT (4)); operands[4] = gen_rtx_PLUS (SImode, operands[4], - gen_rtx_LABEL_REF (SImode, operands[2])); + tmp); operands[4] = gen_rtx_MEM (SImode, operands[4]); MEM_READONLY_P (operands[4]) = 1; MEM_NOTRAP_P (operands[4]) = 1; @@ -9575,12 +9576,11 @@ (leu (match_operand:SI 0 "s_register_operand" "r") (match_operand:SI 1 "arm_rhs_operand" "rI")) (mem:SI (plus:SI (mult:SI (match_dup 0) (const_int 4)) - (label_ref:SI (match_operand 2 "" "")))) + (match_operand:SI 5 "s_register_operand" "r"))) (label_ref:SI (match_operand 3 "" "")))) (clobber (reg:CC CC_REGNUM)) - (clobber (match_scratch:SI 4 "=&r")) - (clobber (match_scratch:SI 5 "=r")) - (use (label_ref:SI (match_dup 2)))])] + (clobber (match_scratch:SI 4 "=r")) + (use (label_ref:SI (match_operand 2 "")))])] "TARGET_ARM" { return arm_output_casesi (operands); diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 5766cb4a9888512889334c48ccfbe46e9980f800..3e878f21350a008c363618599058f33ff759a5fa 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -91,11 +91,11 @@ /* Define this macro if jump tables (for `tablejump' insns) should be output in the text section, along with the assembler instructions. Otherwise, the readonly data section is used. */ -/* We put ARM and Thumb-2 jump tables in the text section, because it makes - the code more efficient, but for Thumb-1 it's better to put them out of +/* We put Thumb-2 jump tables in the text section, because it makes + the code more efficient, but for Thumb-1 and ARM it's better to put them out of band unless we are generating compressed tables. */ #define JUMP_TABLES_IN_TEXT_SECTION \ - ((TARGET_32BIT || (TARGET_THUMB && (optimize_size || flag_pic))) \ + ((TARGET_THUMB2 || (TARGET_THUMB && (optimize_size || flag_pic))) \ && !target_pure_code) #ifndef LINK_SPEC diff --git a/gcc/testsuite/gcc.target/arm/arm-switchstatement.c b/gcc/testsuite/gcc.target/arm/arm-switchstatement.c index a7aa9d45c7634db6c8192072019e497db969b681..803731c479c66e9e684cae532a6071335c042f0e 100644 --- a/gcc/testsuite/gcc.target/arm/arm-switchstatement.c +++ b/gcc/testsuite/gcc.target/arm/arm-switchstatement.c @@ -53,9 +53,10 @@ inline void SIFunction (const char* flag) /* **QImode_test: ** ... -** adr (r[0-9]+), .L[0-9]+ -** ldrb \1, \[\1, r[0-9]+\] -** add pc, pc, \1, lsl #2 +** ldr (r[0-9]+), .L[0-9]+ +** ... +** ldrb (r[0-9]+), \[\1, r[0-9]+\] +** add pc, pc, \2, lsl #2 ** ... */ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* QImode_test(enum z x) @@ -77,10 +78,11 @@ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* QImode_test(enu /* **HImode_test: ** ... -** adr (r[0-9]+), .L[0-9]+ -** add \1, \1, (r[0-9]+) -** ldrh \1, \[\1, \2\] -** add pc, pc, \1, lsl #2 +** ldr (r[0-9]+), .L[0-9]+ +** ... +** add r[0-9]+, r[0-9]+, r[0-9]+ +** ldrh (r[0-9]+), \[r[0-9]+, r[0-9]+] +** add pc, pc, \2, lsl #2 ** ... */ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* HImode_test(enum z x) @@ -102,7 +104,8 @@ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* HImode_test(enu /* **SImode_test: ** ... -** adr (r[0-9]+), .L[0-9]+ +** ldr (r[0-9]+), .L[0-9]+ +** ... ** ldr pc, \[\1, r[0-9]+, lsl #2\] ** ... */ @@ -125,10 +128,11 @@ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* SImode_test(enu /* **backwards_branch_test: ** ... -** adr (r[0-9]+), .L[0-9]+ -** add \1, \1, (r[0-9]+) -** ldrsh \1, \[\1, \2\] -** add pc, pc, \1, lsl #2 +** ldr (r[0-9]+), .L[0-9]+ +** ... +** add r[0-9]+, r[0-9]+, r[0-9]+ +** ldrsh (r[0-9]+), \[r[0-9]+, r[0-9]+] +** add pc, pc, \2, lsl #2 ** ... */ __attribute__ ((noinline)) __attribute__ ((noclone)) const char* backwards_branch_test(enum z x, int flag)