From patchwork Thu Sep 28 12:24:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146181 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3403726vqu; Thu, 28 Sep 2023 08:39:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9dIvA1wgRpyOBMZZcowXnzLdm4OG/8+UhOggB2ZoWW1FGt20EP8jSmWaozD8bEPqdh3My X-Received: by 2002:a05:6a00:80e:b0:666:e1f4:5153 with SMTP id m14-20020a056a00080e00b00666e1f45153mr1698326pfk.0.1695915565170; Thu, 28 Sep 2023 08:39:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695915565; cv=none; d=google.com; s=arc-20160816; b=a+GLXmhjRZjcVbaEWwr8xtys/JpW2tLzCQKLVUl/pJhZxW+7UiLWUZelpwG5Bnxv+M SOvW78BzRSb2DTGIJ79a6xk7HtOgsIb5xuc1E2/33dtDyAqMKqAyyuZS27D58KNVc+Nc uXrycJfLhbCklbkhYldrPyeDPg4aAy4N0Rd2A00eD/C0L8tyltFGNWveChGMQvtvuHgX yirBmm2bjt05tSVMxUoDFgYyI7bRwpn7BjjY2EfuQdBv8iJDP9ebALZYK7h0y058d7xb kPTx9zN6OZK5CHTCdJAzytkIm3JWFPDyN8+DtokDcEImNuuv1TuXpRws1Pne2rkTxZdl VMvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Murv1XK1UiktKIyTFV+yWE0qG+F/vgc4NPP2uXsTpV0=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=cYSD7ZkUKoADO+ev+7YUrVVrrU/5dEoW1YpRlwndsHf+pEOFraFvoSaky438ITGvWI ZM54UGRCSW/Q4rW6WGHQRidElF4ivPzW4aakPhDYnO19m/Wnc8VdFkUqrF3NFi8PGg5S eGr0JFyBjh04jd8yFINm5bnUK3Cd23+yP0Cu7fzpxF4X6jaGgnSrqpOZfZQyDZGIvCYs 2AfOymQ1jMDTJOPsfD+CYse8bSFZsAAtj+NwacBrXxLl9X5531+tvcgT2dGCxysRm0zZ e1eQ6cH5avjFHZhfukbQkc/7cjOqulkh4Q0WVMD90W4TE9D/Z0hlmO3DbvfBVAoA3v5V 3hQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=tf0b7t1h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id q83-20020a632a56000000b005702257f32esi18030387pgq.185.2023.09.28.08.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 08:39:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=tf0b7t1h; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 23DF58068971; Thu, 28 Sep 2023 05:25:23 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231804AbjI1MZS (ORCPT + 21 others); Thu, 28 Sep 2023 08:25:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33070 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230476AbjI1MZQ (ORCPT ); Thu, 28 Sep 2023 08:25:16 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 547EA191; Thu, 28 Sep 2023 05:25:15 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8T5Rp005266; Thu, 28 Sep 2023 14:24:46 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=Murv1XK1UiktKIyTFV+yWE0qG+F/vgc4NPP2uXsTpV0=; b=tf 0b7t1hQ4zJsQwtkMVzVK+xkVf7RkuBjEReBfUQKpE1IeYR05jI+CBLLJu6zlQ+OK GEITtXGeRiTpqFOHynK9PjVFPoCeP0IA+SrGofx4qslPJGGt+5mGsFPFgSfSGWtp vpHAbD3nxPRhHYkE1dNNZR4cNIgfXfGkOa5bcNWEO74hl8hIA2smWDkL7nq1IAJs Et6N3Yeh05vNImszFzLz+Y00iy1D//Tlq/tuM3WzzSSZt1CEB/jtVVpm2J/reee8 9YA4VZVHwKBdHUJ9Kj8erdnBXfnSVkWoay2po6tHnOJhk2wvInW/RCeQy3gFzGvo RqAChAa7wErlU4r4NxXA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3taayhvsxs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:24:46 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 60713100058; Thu, 28 Sep 2023 14:24:33 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 23CBB2309DA; Thu, 28 Sep 2023 14:24:33 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:24:32 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 01/12] dt-bindings: net: add STM32MP13 compatible in documentation for stm32 Date: Thu, 28 Sep 2023 14:24:16 +0200 Message-ID: <20230928122427.313271-2-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:25:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778296360068968860 X-GMAIL-MSGID: 1778296360068968860 New STM32 SOC have 2 GMACs instances. GMAC IP version is SNPS 4.20. Signed-off-by: Christophe Roullier --- .../devicetree/bindings/net/stm32-dwmac.yaml | 78 +++++++++++++++++-- 1 file changed, 70 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index fc8c96b08d7dc..ca976281bfc22 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -22,18 +22,17 @@ select: enum: - st,stm32-dwmac - st,stm32mp1-dwmac + - st,stm32mp13-dwmac required: - compatible -allOf: - - $ref: snps,dwmac.yaml# - properties: compatible: oneOf: - items: - enum: - st,stm32mp1-dwmac + - st,stm32mp13-dwmac - const: snps,dwmac-4.20a - items: - enum: @@ -74,13 +73,10 @@ properties: st,syscon: $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to the syscon node which encompases the glue register - - description: offset of the control register description: Should be phandle/offset pair. The phandle to the syscon node which - encompases the glue register, and the offset of the control register + encompases the glue register, the offset of the control register and + the mask to set bitfield in control register st,eth-clk-sel: description: @@ -101,6 +97,38 @@ required: unevaluatedProperties: false +allOf: + - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp1-dwmac + - st,stm32-dwmac + then: + properties: + st,syscon: + items: + items: + - description: phandle to the syscon node which encompases the glue register + - description: offset of the control register + + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp13-dwmac + then: + properties: + st,syscon: + items: + items: + - description: phandle to the syscon node which encompases the glue register + - description: offset of the control register + - description: field to set mask in register + examples: - | #include @@ -161,3 +189,37 @@ examples: snps,pbl = <8>; phy-mode = "mii"; }; + + - | + #include + #include + #include + #include + //Example 4 + ethernet3: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq", + "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "eth-ck", + "ptp_ref", + "ethstp"; + clocks = <&rcc ETHMAC>, + <&rcc ETHTX>, + <&rcc ETHRX>, + <&rcc ETHCK_K>, + <&rcc ETHPTP_K>, + <&rcc ETHSTP>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + phy-mode = "rmii"; + }; From patchwork Thu Sep 28 12:24:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146161 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3369892vqu; Thu, 28 Sep 2023 07:52:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBneAqdxDl4fPOJ4PsPpEe7k4ZMHiGgl6c2rhkGPpOXvktVFaKni9a1BgGCr6fVtaQpRRq X-Received: by 2002:a05:6e02:1c0e:b0:34c:c0ad:69e0 with SMTP id l14-20020a056e021c0e00b0034cc0ad69e0mr1500770ilh.1.1695912759751; Thu, 28 Sep 2023 07:52:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695912759; cv=none; d=google.com; s=arc-20160816; b=aqsx0G9Z77js8Lv3SPPP2IIHNEGn00zwzaSEC3rCfu2OPgu8c1a6nWSHdVGDtX6xj9 5aYFpHeISbaVNpMu6UMyNndwbT08UNYtf7PjdoEP54YqPm/pp3KOQWu+fdjA/IBYhCMA PpXsT54J7J/37zc5IB7eqv69eKVuEO1jKBdCzdGaozT/XNEg5xACL3F2dU9aGtZ9E0RP 04iBZnOR6JaxWc9E3iLNXmGSCLCwCvvThwODHmNqhDIaYlT6NjgfXMq3JlCTrRsPwvTL LAxQp3GrRW6EuNKlWLvTzo5i+NowkYVexCfPdTYlQZ7j2Nob1peEdMVKuKCd2IG47UJJ HY/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ijjidUf5dUcxUDIaXXOkidI02mty1qHfmNxNoZ5QfvA=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=I1n64Sv10DhX5VindMHa0/Wl1+pz6RNFXvu1mDZT0PEMKBv6Nz4faHUWRhkLV8oTXK SX3qQ1aJF5GLC2H0smc18Z7Xzn6hbBN04G9RTf0xhhgOCHsxlG40FflbKuKjm01OAqz5 MmVwTkMRh+w/KYNxBYc6lmwWyc9Fa2sBSj62hDGRGLWaU+DU3m68SoZ7H5Ck+ix+qSeF 0n1eHCmZ9gYYzWbYY9rEbuJGpVL8S4snKqPHHfGXexKGP4xTrCmVo2qYcMP1zWycLSt8 bKke/QeLL5q315eh8xyrl1vvhzHXkm8EJK0OsNxAx8alWLpLlz9rMJO+V5+QKEhHnyZ9 eDrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="Bq/q428k"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id f20-20020a63f114000000b00565db2812a0si19390221pgi.60.2023.09.28.07.52.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 07:52:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="Bq/q428k"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 1A77C8070E0B; Thu, 28 Sep 2023 05:25:35 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232200AbjI1MZU (ORCPT + 21 others); Thu, 28 Sep 2023 08:25:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33090 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230119AbjI1MZR (ORCPT ); Thu, 28 Sep 2023 08:25:17 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56D18194; Thu, 28 Sep 2023 05:25:15 -0700 (PDT) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38S8X9Cd030339; Thu, 28 Sep 2023 14:24:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=ijjidUf5dUcxUDIaXXOkidI02mty1qHfmNxNoZ5QfvA=; b=Bq /q428kK2E9yTZLHQv8Bl/2LpPFpYbNK450FDYQpCMMz4R7Yxd3Ty8in/N1jyPHxy OeSioxnAD1xlXsSlsorUMfGgi82G0Eb7nu+MZGRsMSqZcGPMvqcHumHWlaOKxFyA NqC6ojiJhNOdchm/ufIYHwhq37u3mMB5ojLUZxfkzmDYdp9Bzj5UScsUHK0G/+2y plhrPjrE+iLC0NlXx5zLt1ZZ9DiS3S6g5pY9GqRlcoUDI8SxDeXWzfcbhRM1+pHe Hs12fwqMkUalurRp1o6S4mzHj6w9oy4xnJvpgiJ6x0EIwc76RQrbOzR0Dc9nlS5o LQnox5jMzsi8PmF5G60g== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tcq63c3ss-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:24:40 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 90B9E100065; Thu, 28 Sep 2023 14:24:34 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 868E72309DA; Thu, 28 Sep 2023 14:24:34 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:24:33 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 02/12] dt-bindings: net: add new property st,ext-phyclk in documentation for stm32 Date: Thu, 28 Sep 2023 14:24:17 +0200 Message-ID: <20230928122427.313271-3-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:25:35 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778293417571347452 X-GMAIL-MSGID: 1778293417571347452 Add property st,ext-phyclk to manage cases when PHY have no cristal/quartz This property can be used with RMII phy without cristal 50Mhz and when we want to select RCC clock instead of ETH_REF_CLK Can be used also with RGMII phy with no cristal and we select RCC clock instead of ETH_CLK125 This new property replace st,eth-clk-sel and st,eth-ref-clk-sel Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index ca976281bfc22..54fda8b052abc 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -78,12 +78,21 @@ properties: encompases the glue register, the offset of the control register and the mask to set bitfield in control register + st,ext-phyclk: + description: + set this property in RMII mode when you have PHY without crystal 50MHz and want to + select RCC clock instead of ETH_REF_CLK. or in RGMII mode when you want to select + RCC clock instead of ETH_CLK125. + type: boolean + st,eth-clk-sel: + deprecated: true description: set this property in RGMII PHY when you want to select RCC clock instead of ETH_CLK125. type: boolean st,eth-ref-clk-sel: + deprecated: true description: set this property in RMII mode when you have PHY without crystal 50MHz and want to select RCC clock instead of ETH_REF_CLK. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 03/12] dt-bindings: net: add phy-supply property for stm32 Date: Thu, 28 Sep 2023 14:24:18 +0200 Message-ID: <20230928122427.313271-4-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778305760360967416 X-GMAIL-MSGID: 1778305760360967416 Phandle to a regulator that provides power to the PHY. This regulator will be managed during the PHY power on/off sequence. Signed-off-by: Christophe Roullier --- Documentation/devicetree/bindings/net/stm32-dwmac.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml index 54fda8b052abc..f96b1589224ba 100644 --- a/Documentation/devicetree/bindings/net/stm32-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/stm32-dwmac.yaml @@ -78,6 +78,9 @@ properties: encompases the glue register, the offset of the control register and the mask to set bitfield in control register + phy-supply: + description: PHY regulator + st,ext-phyclk: description: set this property in RMII mode when you have PHY without crystal 50MHz and want to From patchwork Thu Sep 28 12:24:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146210 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3446587vqu; Thu, 28 Sep 2023 09:43:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGWFhKe2D1M3VCR6GMgTMClp+9p9fT65Ufumu8+RdmhMnPwwTFPoHXBkFSwCbh7Oobt7AGN X-Received: by 2002:a17:902:c714:b0:1c0:6e92:8cbd with SMTP id p20-20020a170902c71400b001c06e928cbdmr1553659plp.28.1695919415007; Thu, 28 Sep 2023 09:43:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695919414; cv=none; d=google.com; s=arc-20160816; b=fWoo0zdHBlKbjnqccppsRL0fSrIpX/SI8F3t/CtkItztjjYpc0A3VUZfzviZ0i1Lru 8WmsgR5lkfIsG1SPgC7fTRKO5q4a4WZwXz9DodIoI6di7GNZ4mSF+Oy73IECnDFJnPpM +HWOUT/Kv2aUq2uv9ER4Ud7HSXer4gTi21VeQ6viHDHExgNI2EkGRIJJEQwUxCjH03AD A+vJH8i8lUyJAv9lU2SQhTt+kWO45juJwpczeoPckzkl9bjtatqjC6D+9V42A5vtuJGV bHxv0y7QHwWgvugb8S3CTKRPQW5gWPfQBye6JIoyeriZYM4mJrY22h6P8vtM6s28dK6s 7s1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=P3XV1IaVNFLkdLdID+Fpncm54gnI4v+2MxfVHgWirNY=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=rJaZeUtj/LJdVjAF+Cku92ezn9UjWRpS1W6X9Bg7Wr9frTfkKM46oqtQKi0bxkDgDx cc1KEEgR5ROeeu86aQpYl5CY4q/qZxtURWAUKi0VomSDXFFxVSZ43vvi5pdJeJjNDTMm +8XwHbvswH1Istz6NePxMzuq9raQtcXZVOZ08x4sF0lkTnwW0jGv9nsW4zyJZs3mNyRd gR5gIu0L0IQMp0/LrIE9tXZYpxu/w/DmBgqmxeQAc4pQzX2bnXXvAL/UDp0qcetSssSj jG0F1zFi5JpzD6VPOItBYc5KP8jvjw19Ka8vgvUdyYg8SpabM1ES/Dm9wVcJBKBOifUY 74iw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=dsyFU5uc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from snail.vger.email (snail.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 04/12] net: ethernet: stmmac: rework glue to simplify management for next stm32 Date: Thu, 28 Sep 2023 14:24:19 +0200 Message-ID: <20230928122427.313271-5-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:25:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778300396678115591 X-GMAIL-MSGID: 1778300396678115591 Change glue to be more generic and manage easily next stm32 products. The goal of this commit is to have one stm32mp1_set_mode function which can manage different STM32 SOC. SOC can have different SYSCFG register bitfields. so in pmcsetr we defined the bitfields corresponding to the SOC. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 70 +++++++++++++------ 1 file changed, 48 insertions(+), 22 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index ab4324ed46dac..52106e0d7359f 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -23,10 +23,6 @@ #define SYSCFG_MCU_ETH_MASK BIT(23) #define SYSCFG_MP1_ETH_MASK GENMASK(23, 16) -#define SYSCFG_PMCCLRR_OFFSET 0x40 - -#define SYSCFG_PMCR_ETH_CLK_SEL BIT(16) -#define SYSCFG_PMCR_ETH_REF_CLK_SEL BIT(17) /* CLOCK feed to PHY*/ #define ETH_CK_F_25M 25000000 @@ -46,9 +42,6 @@ * RMII | 1 | 0 | 0 | n/a | *------------------------------------------ */ -#define SYSCFG_PMCR_ETH_SEL_MII BIT(20) -#define SYSCFG_PMCR_ETH_SEL_RGMII BIT(21) -#define SYSCFG_PMCR_ETH_SEL_RMII BIT(23) #define SYSCFG_PMCR_ETH_SEL_GMII 0 #define SYSCFG_MCU_ETH_SEL_MII 0 #define SYSCFG_MCU_ETH_SEL_RMII 1 @@ -90,12 +83,25 @@ struct stm32_dwmac { int eth_ref_clk_sel_reg; int irq_pwr_wakeup; u32 mode_reg; /* MAC glue-logic mode register */ + u32 mode_mask; struct regmap *regmap; u32 speed; const struct stm32_ops *ops; struct device *dev; }; +struct stm32_syscfg_pmcsetr { + u32 eth1_clk_sel; + u32 eth1_ref_clk_sel; + u32 eth1_selmii; + u32 eth1_sel_rgmii; + u32 eth1_sel_rmii; + u32 eth2_clk_sel; + u32 eth2_ref_clk_sel; + u32 eth2_sel_rgmii; + u32 eth2_sel_rmii; +}; + struct stm32_ops { int (*set_mode)(struct plat_stmmacenet_data *plat_dat); int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare); @@ -103,7 +109,8 @@ struct stm32_ops { void (*resume)(struct stm32_dwmac *dwmac); int (*parse_data)(struct stm32_dwmac *dwmac, struct device *dev); - u32 syscfg_eth_mask; + u32 syscfg_clr_off; + struct stm32_syscfg_pmcsetr pmcsetr; }; static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) @@ -175,7 +182,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_MII: if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) dwmac->enable_eth_ck = true; - val = SYSCFG_PMCR_ETH_SEL_MII; + val = dwmac->ops->pmcsetr.eth1_selmii; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: @@ -183,16 +190,17 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) if (clk_rate == ETH_CK_F_25M && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_CLK_SEL; + val |= dwmac->ops->pmcsetr.eth1_clk_sel; } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: - val = SYSCFG_PMCR_ETH_SEL_RMII; + val = dwmac->ops->pmcsetr.eth1_sel_rmii | dwmac->ops->pmcsetr.eth2_sel_rmii; if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; + val |= dwmac->ops->pmcsetr.eth1_ref_clk_sel; + val |= dwmac->ops->pmcsetr.eth2_ref_clk_sel; } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); break; @@ -200,11 +208,12 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_ID: case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: - val = SYSCFG_PMCR_ETH_SEL_RGMII; + val = dwmac->ops->pmcsetr.eth1_sel_rgmii | dwmac->ops->pmcsetr.eth2_sel_rgmii; if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; - val |= SYSCFG_PMCR_ETH_CLK_SEL; + val |= dwmac->ops->pmcsetr.eth1_clk_sel; + val |= dwmac->ops->pmcsetr.eth2_clk_sel; } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); break; @@ -216,12 +225,12 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) } /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, - dwmac->ops->syscfg_eth_mask); + regmap_write(dwmac->regmap, reg + dwmac->ops->syscfg_clr_off, + dwmac->mode_mask); /* Update PMCSETR (set register) */ return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val); + dwmac->mode_mask, val); } static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) @@ -247,7 +256,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) } return regmap_update_bits(dwmac->regmap, reg, - dwmac->ops->syscfg_eth_mask, val << 23); + SYSCFG_MCU_ETH_MASK, val << 23); } static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac) @@ -290,10 +299,17 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, return PTR_ERR(dwmac->regmap); err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); + if (err) { + dev_err(dev, "Can't get sysconfig register offset (%d)\n", err); + return err; + } + + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); if (err) - dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); + pr_debug("Warning sysconfig register mask not set\n"); - return err; + return 0; } static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, @@ -499,7 +515,6 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, static struct stm32_ops stm32mcu_dwmac_data = { .set_mode = stm32mcu_set_mode, .suspend = stm32mcu_suspend, - .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK }; static struct stm32_ops stm32mp1_dwmac_data = { @@ -508,7 +523,18 @@ static struct stm32_ops stm32mp1_dwmac_data = { .suspend = stm32mp1_suspend, .resume = stm32mp1_resume, .parse_data = stm32mp1_parse_data, - .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK + .syscfg_clr_off = 0x44, + .pmcsetr = { + .eth1_clk_sel = BIT(16), + .eth1_ref_clk_sel = BIT(17), + .eth1_selmii = BIT(20), + .eth1_sel_rgmii = BIT(21), + .eth1_sel_rmii = BIT(23), + .eth2_clk_sel = 0, + .eth2_ref_clk_sel = 0, + .eth2_sel_rgmii = 0, + .eth2_sel_rmii = 0 + } }; static const struct of_device_id stm32_dwmac_match[] = { From patchwork Thu Sep 28 12:24:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146311 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3608495vqu; Thu, 28 Sep 2023 14:25:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFAcMdLDfarUDszFeGugFp/d9IEH2Y6r7jMETLa5RjjcQljFjnDn8tzK/t8vzQtzBOdjv3I X-Received: by 2002:a9d:6b99:0:b0:6bd:c865:a618 with SMTP id b25-20020a9d6b99000000b006bdc865a618mr2608665otq.13.1695936311514; Thu, 28 Sep 2023 14:25:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695936311; cv=none; d=google.com; s=arc-20160816; b=ZqUlZy4sT7fdzcLsrXZ8wZvROsUUqUWm6kDr6lMdCsOizoK4+XGXxGrF851GqTsCdF lJ6STBSOYKwk4Qb0ohcR94nQK1lD7IdWZSIPIFZU8TK5TK2IwoHPEQ2rjk0kYKY23sC5 D4ht3r3FgQ0bmroR4S3oEe5h9RL+5k04/efqCEZPtmKjS/CfY29jBjG5MN+h1AVwJpKT 6nZriwMuh0UyRXdT+ylO1FXQ20RhgUPAG8SdCd96zbXvZf9zpavy1QWssJg6B98TiyLC 2VPaD5AKF9v/Gbe+vA2s9+OBq9UDCdJNcJJpMNWMj0avOMyS81hRN6EZU0FyCr/EFv/S gGAQ== ARC-Message-Signature: i=1; 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[23.128.96.33]) by mx.google.com with ESMTPS id by7-20020a056a00400700b0069022a03d42si2034767pfb.283.2023.09.28.14.25.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 14:25:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=3ThKsGtN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 281988359B40; Thu, 28 Sep 2023 05:26:21 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231793AbjI1M0L (ORCPT + 21 others); Thu, 28 Sep 2023 08:26:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232345AbjI1M0J (ORCPT ); Thu, 28 Sep 2023 08:26:09 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 663A2198; Thu, 28 Sep 2023 05:26:07 -0700 (PDT) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 38S8kbbg029789; Thu, 28 Sep 2023 14:25:47 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=tCZxZAAY+Gn9wAA1qw22DEBm15B9XqamItmDNiDWxRA=; b=3T hKsGtN3FHsNkACWq8RTC+Eb//Ldd6YaKS2h5AWlZfUQQn/8GCAuA/1MNTDot/g0u jgy68t2kWg9lgiTXaL9o2RspXGDqVhtlGH2am2gjPTgEPl7TOqVBI0gajfbJlZ1y qp0GtBqaXDUHNx2S2XJ5cJ+lk58M5OGoPv1m+OPULIUHLG5PrGkl409S+l5kJ+og TyVJrW6V5y1bNZbQw1IgSHYKqhzt1/02hiRPX9+IqiC3tm3VbRQL3TgJ4pqYNI/H 1mKP/Ve0qPP2VGFpi/WF2hckTid1839AbESqi3RzaJzYOYZGjECTQ6eD1uCIzVgK L/Sj20hQhZxF8BMVFSHA== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3tcq63c405-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:25:47 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 0FA09100058; Thu, 28 Sep 2023 14:25:47 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 04E202309E5; Thu, 28 Sep 2023 14:25:47 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:25:46 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 05/12] net: ethernet: stmmac: add management of stm32mp13 for stm32 Date: Thu, 28 Sep 2023 14:24:20 +0200 Message-ID: <20230928122427.313271-6-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778318113950570196 X-GMAIL-MSGID: 1778318113950570196 From: Christophe Roullier Add Ethernet support for STM32MP13. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP version is SNPS 4.20. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 52106e0d7359f..a071dc6ffc95b 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -537,9 +537,30 @@ static struct stm32_ops stm32mp1_dwmac_data = { } }; +static struct stm32_ops stm32mp13_dwmac_data = { + .set_mode = stm32mp1_set_mode, + .clk_prepare = stm32mp1_clk_prepare, + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, + .syscfg_clr_off = 0x08, + .pmcsetr = { + .eth1_clk_sel = BIT(16), + .eth1_ref_clk_sel = BIT(17), + .eth1_selmii = 0, + .eth1_sel_rgmii = BIT(21), + .eth1_sel_rmii = BIT(23), + .eth2_clk_sel = BIT(24), + .eth2_ref_clk_sel = BIT(25), + .eth2_sel_rgmii = BIT(29), + .eth2_sel_rmii = BIT(31) + } +}; + static const struct of_device_id stm32_dwmac_match[] = { { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, + { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, { } }; MODULE_DEVICE_TABLE(of, stm32_dwmac_match); From patchwork Thu Sep 28 12:24:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146111 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3311642vqu; Thu, 28 Sep 2023 06:28:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHzfjTJLQ3RHZAaaVqxo8P4ZZ5fGU3RwmbvQnEB2Pl0CrwiSv3mr4MXvuzPqWjiRDXISV9i X-Received: by 2002:a05:6358:24a6:b0:13c:dc2e:3548 with SMTP id m38-20020a05635824a600b0013cdc2e3548mr1335572rwc.28.1695907697420; Thu, 28 Sep 2023 06:28:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695907697; cv=none; d=google.com; s=arc-20160816; b=nb98yfUnlym+3hKAt/jNyYs2D77cnwXBwKcQwoZbV5LPlOC7p/Ksh5LcgGx47gVj0b GUsW3rcviZypwMe/wI/DpTSlsO+NCcm/WoMDqjN7EfhRSitdzmlDL3DUHY7NcgzA80ru s73Gn0d6Q8NDqCLJiSzAnO2dSfEawfpmyF1bH7nYxw71gwpVuqrfj4PwEMHBRgxfz3uh DDGllFABQ0VxAejaZsKYFeQfSp0Re8sZlmhwi8QXo5f+3SxgJWBYNbbtB8KBv+2M4yrW 3xv3FOg/CYdmHuo03f/CErZkSE/md1bFbedJ4yN7JaWbXga64WD26ir3Ue7S2oRh8zzu OfCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RBXVmwb6jNT2iUShZk/ZgEGot9S1AER/3jhHyMGTE+c=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=dL4Wlz9hnBJLBUq6UR8nHRi8/N8K4joI6eDqc3pCVO4CT3p8MOgiO7ffEfGXuGpJIs 7syxhXaw4fFlHAv5XWPqFsWUbKVn8BEvEnTdLXfszX5o2JIbNBR7xpYGFuVoY14yQ8lt reToiOqz4hg4GljT0sVjeQBRkPOz0MV8Qm1mdnfx0hh+bfnNE+i7mjTxmucLuPHbQtUH yCex625W2g+bOlQ1nnb/bhV3dT6LLhij8IzqA/d7faIkL4sDbPdgaCr5c7CSeF1HLuwW pSHp2C+s03gED3/4HECcX51v3RgA363pvXbEpWjs6rDTfEEyivUpqTcckKJ0JzaAOkMJ t5zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b="6XIlU/PS"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from pete.vger.email (pete.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 06/12] net: ethernet: stmmac: stm32: update config management for phy wo cristal Date: Thu, 28 Sep 2023 14:24:21 +0200 Message-ID: <20230928122427.313271-7-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778288109778245914 X-GMAIL-MSGID: 1778288109778245914 From: Christophe Roullier Some cleaning because some Ethernet PHY configs do not need to add st,ext-phyclk property Change print info message "No phy clock provided" only when debug Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++--------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index a071dc6ffc95b..1210062f0832a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -55,17 +55,17 @@ *| | | 25MHz | 50MHz | | * --------------------------------------------------------------------------- *| MII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| GMII | - | eth-ck | n/a | n/a | - *| | | st,ext-phyclk | | | + *| | | | | | * --------------------------------------------------------------------------- *| RGMII | - | eth-ck | n/a | eth-ck | - *| | | st,ext-phyclk | | st,eth-clk-sel or| + *| | | | | st,eth-clk-sel or| *| | | | | st,ext-phyclk | * --------------------------------------------------------------------------- *| RMII | - | eth-ck | eth-ck | n/a | - *| | | st,ext-phyclk | st,eth-ref-clk-sel | | + *| | | | st,eth-ref-clk-sel | | *| | | | or st,ext-phyclk | | * --------------------------------------------------------------------------- * @@ -180,23 +180,22 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) dwmac->enable_eth_ck = false; switch (plat_dat->mac_interface) { case PHY_INTERFACE_MODE_MII: - if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; val = dwmac->ops->pmcsetr.eth1_selmii; pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); break; case PHY_INTERFACE_MODE_GMII: val = SYSCFG_PMCR_ETH_SEL_GMII; - if (clk_rate == ETH_CK_F_25M && - (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { + if (clk_rate == ETH_CK_F_25M) dwmac->enable_eth_ck = true; - val |= dwmac->ops->pmcsetr.eth1_clk_sel; - } pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); break; case PHY_INTERFACE_MODE_RMII: val = dwmac->ops->pmcsetr.eth1_sel_rmii | dwmac->ops->pmcsetr.eth2_sel_rmii; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_50M) && (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; val |= dwmac->ops->pmcsetr.eth1_ref_clk_sel; @@ -209,7 +208,9 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) case PHY_INTERFACE_MODE_RGMII_RXID: case PHY_INTERFACE_MODE_RGMII_TXID: val = dwmac->ops->pmcsetr.eth1_sel_rgmii | dwmac->ops->pmcsetr.eth2_sel_rgmii; - if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && + if (clk_rate == ETH_CK_F_25M) + dwmac->enable_eth_ck = true; + if ((clk_rate == ETH_CK_F_125M) && (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { dwmac->enable_eth_ck = true; val |= dwmac->ops->pmcsetr.eth1_clk_sel; @@ -225,7 +226,7 @@ static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) } /* Need to update PMCCLRR (clear register) */ - regmap_write(dwmac->regmap, reg + dwmac->ops->syscfg_clr_off, + regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, dwmac->mode_mask); /* Update PMCSETR (set register) */ @@ -332,7 +333,7 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, /* Get ETH_CLK clocks */ dwmac->clk_eth_ck = devm_clk_get(dev, "eth-ck"); if (IS_ERR(dwmac->clk_eth_ck)) { - dev_info(dev, "No phy clock provided...\n"); + dev_dbg(dev, "No phy clock provided...\n"); dwmac->clk_eth_ck = NULL; } From patchwork Thu Sep 28 12:24:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146267 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3549570vqu; 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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id n1-20020a63f801000000b00577549e67b9si19915008pgh.589.2023.09.28.12.31.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 12:31:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=iipr5Wev; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 495FC835B4D5; Thu, 28 Sep 2023 05:26:31 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232091AbjI1M0R (ORCPT + 21 others); Thu, 28 Sep 2023 08:26:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231752AbjI1M0P (ORCPT ); Thu, 28 Sep 2023 08:26:15 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EBF64180; Thu, 28 Sep 2023 05:26:12 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8Z1tb005056; Thu, 28 Sep 2023 14:25:51 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=YH09b5A6p7d6RqxQi7VNy0tTydxbVqJd3xWAAQdyLhA=; b=ii pr5WevPAmtdagJ1fW6TePKw4wlkJqErPNo46q14mAtE7NJN9astFpArNGckC8utH cQviZvQPn/Y+x9QgnvsvCHrNOgkwEVx2GJIH79wDiFRUgjIoXqsvwnftB77FJQTO iBYpGGBBJG5M5mJ7n40pakOMDsi+fLYGdZ2NsaRaobEPZ61l6FLqYtFS/9atLMZw Xf+pZ/nR7ukwE3PtVCxj8dkyoBuO4nVr5k2wq9cArZhr7MO2jSVK4+zL43WoL2K9 l5NQxtYvFuVvKQWXTZerAskX4KL0OfIr1iNNK0nJ4lOEjCHcmYhTbYLNGUzyoQKQ 3wN/3b2HQSnEXhOw3+Nw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3taayhvt5u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:25:51 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id B493E100058; Thu, 28 Sep 2023 14:25:50 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A951822F7B0; Thu, 28 Sep 2023 14:25:50 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:25:47 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 07/12] net: ethernet: stm32: clean the way to manage wol irqwake Date: Thu, 28 Sep 2023 14:24:22 +0200 Message-ID: <20230928122427.313271-8-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778310976661980736 X-GMAIL-MSGID: 1778310976661980736 From: Christophe Roullier On STM32 platforms it is no longer needed to use a dedicated wakeup to wake up system from CStop. This patch removes the dedicated wake up usage and clean the way to register the wake up irq. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 64 +++++++++---------- 1 file changed, 31 insertions(+), 33 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 1210062f0832a..72dda71850d75 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -81,7 +81,6 @@ struct stm32_dwmac { int enable_eth_ck; int eth_clk_sel_reg; int eth_ref_clk_sel_reg; - int irq_pwr_wakeup; u32 mode_reg; /* MAC glue-logic mode register */ u32 mode_mask; struct regmap *regmap; @@ -316,9 +315,7 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, struct device *dev) { - struct platform_device *pdev = to_platform_device(dev); struct device_node *np = dev->of_node; - int err = 0; /* Ethernet PHY have no crystal */ dwmac->ext_phyclk = of_property_read_bool(np, "st,ext-phyclk"); @@ -350,29 +347,24 @@ static int stm32mp1_parse_data(struct stm32_dwmac *dwmac, if (IS_ERR(dwmac->syscfg_clk)) dwmac->syscfg_clk = NULL; - /* Get IRQ information early to have an ability to ask for deferred - * probe if needed before we went too far with resource allocation. - */ - dwmac->irq_pwr_wakeup = platform_get_irq_byname_optional(pdev, - "stm32_pwr_wakeup"); - if (dwmac->irq_pwr_wakeup == -EPROBE_DEFER) - return -EPROBE_DEFER; - - if (!dwmac->clk_eth_ck && dwmac->irq_pwr_wakeup >= 0) { - err = device_init_wakeup(&pdev->dev, true); - if (err) { - dev_err(&pdev->dev, "Failed to init wake up irq\n"); - return err; - } - err = dev_pm_set_dedicated_wake_irq(&pdev->dev, - dwmac->irq_pwr_wakeup); - if (err) { - dev_err(&pdev->dev, "Failed to set wake up irq\n"); - device_init_wakeup(&pdev->dev, false); - } - device_set_wakeup_enable(&pdev->dev, false); + return 0; +} + +static int stm32_dwmac_wake_init(struct device *dev, + struct stmmac_resources *stmmac_res) +{ + int err; + + device_set_wakeup_capable(dev, true); + + err = dev_pm_set_wake_irq(dev, stmmac_res->wol_irq); + if (err) { + dev_err(dev, "Failed to set wake up irq\n"); + device_set_wakeup_capable(dev, false); + return err; } - return err; + + return 0; } static int stm32_dwmac_probe(struct platform_device *pdev) @@ -410,11 +402,17 @@ static int stm32_dwmac_probe(struct platform_device *pdev) return ret; } + if (stmmac_res.wol_irq && !dwmac->clk_eth_ck) { + ret = stm32_dwmac_wake_init(&pdev->dev, &stmmac_res); + if (ret) + goto err_wake_init_disable; + } + plat_dat->bsp_priv = dwmac; ret = stm32_dwmac_init(plat_dat); if (ret) - return ret; + goto err_wake_init_disable; ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); if (ret) @@ -424,7 +422,11 @@ static int stm32_dwmac_probe(struct platform_device *pdev) err_clk_disable: stm32_dwmac_clk_disable(dwmac); - +err_wake_init_disable: + if (stmmac_res.wol_irq && !dwmac->clk_eth_ck) { + dev_pm_clear_wake_irq(&pdev->dev); + device_set_wakeup_capable(&pdev->dev, false); + } return ret; } @@ -432,16 +434,12 @@ static void stm32_dwmac_remove(struct platform_device *pdev) { struct net_device *ndev = platform_get_drvdata(pdev); struct stmmac_priv *priv = netdev_priv(ndev); - struct stm32_dwmac *dwmac = priv->plat->bsp_priv; stmmac_dvr_remove(&pdev->dev); - stm32_dwmac_clk_disable(priv->plat->bsp_priv); - if (dwmac->irq_pwr_wakeup >= 0) { - dev_pm_clear_wake_irq(&pdev->dev); - device_init_wakeup(&pdev->dev, false); - } + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); } static int stm32mp1_suspend(struct stm32_dwmac *dwmac) From patchwork Thu Sep 28 12:24:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146333 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3645383vqu; Thu, 28 Sep 2023 15:42:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHgdzwmniaKobN65S5FCZ8dAFNh6F9vSXnWaeJL4i/y/NkzwcMOYOGQQj70uAB69z6ylSUi X-Received: by 2002:a05:6a00:1798:b0:68f:c078:b0c9 with SMTP id s24-20020a056a00179800b0068fc078b0c9mr4520094pfg.11.1695940967031; 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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id q22-20020a056a00151600b00690f49d9e44si20646637pfu.400.2023.09.28.15.42.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 15:42:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=y5J0Qg2p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id C3F258389DAD; Thu, 28 Sep 2023 05:26:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232450AbjI1M0c (ORCPT + 21 others); Thu, 28 Sep 2023 08:26:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47648 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232434AbjI1M0V (ORCPT ); Thu, 28 Sep 2023 08:26:21 -0400 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 973161A7; Thu, 28 Sep 2023 05:26:16 -0700 (PDT) Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8VIaf001998; Thu, 28 Sep 2023 14:25:50 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=qxcsFIRjXFLHKGA5nZCs9qGhJHkQP52WVsL1NenTq+Y=; b=y5 J0Qg2pa6afxG03gQN/EMfDY/vxkRD7xbaHTP4NJxVWa3GvNkqKNqhoYNZALjZSiS iFCCMLAfW14Kah47XXqltrnQlmPsBCnJQ08Wn6YK1xa6fgoFRtpxoDHM2vM/v0tY s02pAI5ISoxLaCXHyQ5ALUg2vj547e4Sh2ZXlMgNskgq2I1vbtms6W8qasQb6DN7 HmvcRjBqAOU1yESpdvhEiDDP74/T8+KCuG3CoKLnBz9xTsIYCifvlofsn8NJI8SV O7WrtUd9gQIO8aBRA2efwew4Mfc1OHnsBdmt6NIOM1PnmoowAPs8LjWAwjn6qiH0 tqOuLpOcMRlxTLmN2fyg== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3t9pwdf4a6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:25:50 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 7EB7C100058; Thu, 28 Sep 2023 14:25:49 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7395D22F7B0; Thu, 28 Sep 2023 14:25:49 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:25:48 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 08/12] net: ethernet: stmmac: stm32: support the phy-supply regulator binding Date: Thu, 28 Sep 2023 14:24:23 +0200 Message-ID: <20230928122427.313271-9-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778322995582679831 X-GMAIL-MSGID: 1778322995582679831 From: Christophe Roullier Configure the phy regulator if defined by the "phy-supply" DT phandle. Signed-off-by: Christophe Roullier --- .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++++++++++++++++++- 1 file changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c index 72dda71850d75..31e3abd2caeaa 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -84,6 +85,7 @@ struct stm32_dwmac { u32 mode_reg; /* MAC glue-logic mode register */ u32 mode_mask; struct regmap *regmap; + struct regulator *regulator; u32 speed; const struct stm32_ops *ops; struct device *dev; @@ -309,6 +311,16 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, if (err) pr_debug("Warning sysconfig register mask not set\n"); + dwmac->regulator = devm_regulator_get_optional(dev, "phy"); + if (IS_ERR(dwmac->regulator)) { + if (PTR_ERR(dwmac->regulator) == -EPROBE_DEFER) { + dev_dbg(dev, "phy regulator is not available yet, deferred probing\n"); + return -EPROBE_DEFER; + } + dev_dbg(dev, "no regulator found\n"); + dwmac->regulator = NULL; + } + return 0; } @@ -367,6 +379,27 @@ static int stm32_dwmac_wake_init(struct device *dev, return 0; } +static int phy_power_on(struct stm32_dwmac *bsp_priv, bool enable) +{ + int ret; + struct device *dev = bsp_priv->dev; + + if (!bsp_priv->regulator) + return 0; + + if (enable) { + ret = regulator_enable(bsp_priv->regulator); + if (ret) + dev_err(dev, "fail to enable phy-supply\n"); + } else { + ret = regulator_disable(bsp_priv->regulator); + if (ret) + dev_err(dev, "fail to disable phy-supply\n"); + } + + return 0; +} + static int stm32_dwmac_probe(struct platform_device *pdev) { struct plat_stmmacenet_data *plat_dat; @@ -414,12 +447,18 @@ static int stm32_dwmac_probe(struct platform_device *pdev) if (ret) goto err_wake_init_disable; - ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + ret = phy_power_on(plat_dat->bsp_priv, true); if (ret) goto err_clk_disable; + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + goto err_gmac_powerdown; + return 0; +err_gmac_powerdown: + phy_power_on(plat_dat->bsp_priv, false); err_clk_disable: stm32_dwmac_clk_disable(dwmac); err_wake_init_disable: @@ -440,6 +479,8 @@ static void stm32_dwmac_remove(struct platform_device *pdev) dev_pm_clear_wake_irq(&pdev->dev); device_init_wakeup(&pdev->dev, false); + + phy_power_on(priv->plat->bsp_priv, false); } static int stm32mp1_suspend(struct stm32_dwmac *dwmac) @@ -455,12 +496,20 @@ static int stm32mp1_suspend(struct stm32_dwmac *dwmac) if (dwmac->enable_eth_ck) clk_disable_unprepare(dwmac->clk_eth_ck); + /* Keep the PHY up if we use Wake-on-Lan. */ + if (!device_may_wakeup(dwmac->dev)) + phy_power_on(dwmac, false); + return ret; } static void stm32mp1_resume(struct stm32_dwmac *dwmac) { clk_disable_unprepare(dwmac->clk_ethstp); + + /* The PHY was up for Wake-on-Lan. */ + if (!device_may_wakeup(dwmac->dev)) + phy_power_on(dwmac, true); } static int stm32mcu_suspend(struct stm32_dwmac *dwmac) From patchwork Thu Sep 28 12:24:24 2023 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 09/12] ARM: dts: stm32: add ethernet1 and ethernet2 support on stm32mp13 Date: Thu, 28 Sep 2023 14:24:24 +0200 Message-ID: <20230928122427.313271-10-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:26:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778292689087016141 X-GMAIL-MSGID: 1778292689087016141 Both instances ethernet based on GMAC SNPS IP on stm32mp13. GMAC IP version is SNPS 4.20. STM32MP13 is STM32 SOC with 2 GMACs instances. GMAC IP configure with 1 RX and 1 TX queue. DMA HW capability register supported RX Checksum Offload Engine supported TX Checksum insertion supported Wake-Up On Lan supported TSO supported Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp131.dtsi | 31 ++++++++++++++++++++++++++++ arch/arm/boot/dts/st/stm32mp133.dtsi | 30 +++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp131.dtsi b/arch/arm/boot/dts/st/stm32mp131.dtsi index ac90fcbf0c091..d8339eea05d53 100644 --- a/arch/arm/boot/dts/st/stm32mp131.dtsi +++ b/arch/arm/boot/dts/st/stm32mp131.dtsi @@ -1296,6 +1296,37 @@ sdmmc2: mmc@58007000 { status = "disabled"; }; + ethernet1: ethernet@5800a000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, + <&exti 68 1>; + interrupt-names = "macirq", "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH1MAC>, + <&rcc ETH1TX>, + <&rcc ETH1RX>, + <&rcc ETH1STP>, + <&rcc ETH1CK_K>; + st,syscon = <&syscfg 0x4 0xff0000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_1>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_1: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; + usbh_ohci: usb@5800c000 { compatible = "generic-ohci"; reg = <0x5800c000 0x1000>; diff --git a/arch/arm/boot/dts/st/stm32mp133.dtsi b/arch/arm/boot/dts/st/stm32mp133.dtsi index df451c3c2a26d..aee855cd2f36b 100644 --- a/arch/arm/boot/dts/st/stm32mp133.dtsi +++ b/arch/arm/boot/dts/st/stm32mp133.dtsi @@ -64,5 +64,35 @@ channel@18 { }; }; }; + + ethernet2: ethernet@5800e000 { + compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800e000 0x2000>; + reg-names = "stmmaceth"; + interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "macirq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", + "ethstp", + "eth-ck"; + clocks = <&rcc ETH2MAC>, + <&rcc ETH2TX>, + <&rcc ETH2RX>, + <&rcc ETH2STP>, + <&rcc ETH2CK_K>; + st,syscon = <&syscfg 0x4 0xff000000>; + snps,mixed-burst; + snps,pbl = <2>; + snps,axi-config = <&stmmac_axi_config_2>; + snps,tso; + status = "disabled"; + + stmmac_axi_config_2: stmmac-axi-config { + snps,wr_osr_lmt = <0x7>; + snps,rd_osr_lmt = <0x7>; + snps,blen = <0 0 0 0 16 8 4>; + }; + }; }; }; From patchwork Thu Sep 28 12:24:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146324 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3626518vqu; Thu, 28 Sep 2023 15:03:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXcgFa9645G6WereCCS4QfJDm9BbmcRlmfo8o/KtZx77Byf9P9oErQUb9aGiKp48X76fIp X-Received: by 2002:a05:6a20:f397:b0:15e:dc75:66af with SMTP id qr23-20020a056a20f39700b0015edc7566afmr2285160pzb.59.1695938587885; Thu, 28 Sep 2023 15:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695938587; cv=none; d=google.com; s=arc-20160816; b=IcOqNC32kEWpX80WtPis1nNpBTUx38hjWLJK5UW09RvrXnxq57XbldMPTeqfElkqR1 bgKhEJ/SvwcbNM81E1u3nH1kOga3+Di7BCm8SR0ZmXVyNH1fiSr1m0ai3DiIMoRCwb2l HaDI3lq9Y4hs5XMgpw7iwd9HPe1jT4Q27m387fk2voqTzYJjbsU8BCxYcHhCUtzPx8CS BAPZyTad84bLzgg4Hp8jJ4Xjt+J6wdl/rlhFrAtazgPqzSEeHVmTw4T5G8VO/VwyRPM5 2QXH0V/XzErKBi+daXv1whjvRHRhB0dqf6CaHHN7cFyiCSq18bQ9LRJzP3bZ7pox4BJ5 haNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oEuv97N2UpfsnYNl32STo/S5ISOQdowcz3DPU656h8c=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=uA/DrE7wWcaJr7X0RU6uga8T2Qz3EKriNMjgRN9k4RvCmI3/mj2Ilc1jPyL+WJeJo7 DjlVSLlqye3vYOkf+HYigTfWVTDDN0siA1YN14dHUkvQA5gYj5AFnqC6xVpnZgoUulKV iy3rs9r4UOVFBUcDywSvQEjgoEqOOxM+haT+y0g2+LOAGwjXpFvy/ehfaW8nER3pOuG3 khgARQlTVHDC0O4oAWMtHE8LJjZ7ZIeSMnhwvWWPkI9gVLEMMHmstwVu9JUGk0V52ITM 9tEnBpEaKMvIzrXuB1aTALKEDuc7bpvGUqpIan4eSsYUHFIT0eFcUzpODM0M8bkPdt1/ +i/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=jdJNn+OR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id cp17-20020a056a00349100b00690fc88e4c4si19766710pfb.70.2023.09.28.15.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Sep 2023 15:03:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=jdJNn+OR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 292D080B18A5; Thu, 28 Sep 2023 05:27:46 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232434AbjI1M1a (ORCPT + 21 others); Thu, 28 Sep 2023 08:27:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54454 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229478AbjI1M1Z (ORCPT ); Thu, 28 Sep 2023 08:27:25 -0400 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F42E193; Thu, 28 Sep 2023 05:27:23 -0700 (PDT) Received: from pps.filterd (m0369457.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.22/8.17.1.22) with ESMTP id 38S8W5fH005085; Thu, 28 Sep 2023 14:27:02 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:content-type; s= selector1; bh=oEuv97N2UpfsnYNl32STo/S5ISOQdowcz3DPU656h8c=; b=jd JNn+ORBb6FGQvNdH9DOdRMz58bBt6E8lGD1ywlgnzq0Td65dZSzIDgGhzSVyViXD 0KsQrVg962kC/ubhqU5GrzXqeReSggl1F9zlWRzbQESRVg3jeg6k3wpbYc/g1cpT aoGkJQwN3GMOFZZiyi0112nrTiGGyApO4f75cBrYpqHzDChNjT7AyiN7tFtAAE2u RT5bGII3iAvPFDXWf+a4MW+0v+0nlhU7c/PGmRo2//DTujY0iw+9NlrizDl0LGt+ LRJh4WNoYwNr9JxugUmXsPx0LqnmyC7vAYTqxRHnvwqX2zvEdVD/VLH5QoxvtYcc sYKoS648keKMjg3zyDuw== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3taayhvtdg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 28 Sep 2023 14:27:02 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2A836100057; Thu, 28 Sep 2023 14:27:01 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 200AA2309EC; Thu, 28 Sep 2023 14:27:01 +0200 (CEST) Received: from localhost (10.201.21.249) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Thu, 28 Sep 2023 14:27:00 +0200 From: Christophe Roullier To: "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 10/12] ARM: dts: stm32: add ethernet1/2 RMII pins for STM32MP13F-DK board Date: Thu, 28 Sep 2023 14:24:25 +0200 Message-ID: <20230928122427.313271-11-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:27:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778320500857977740 X-GMAIL-MSGID: 1778320500857977740 Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. ethernet1: RMII with crystal. ethernet2: RMII without crystal. PHYs used are SMSC (LAN8742A) Add analog gpio pin configuration ("sleep") to manage power mode on stm32mp13. Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 71 +++++++++++++++++++++ 1 file changed, 71 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi index 27e0c3826789d..b2583df813af8 100644 --- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi @@ -13,6 +13,77 @@ pins { }; }; + eth1_rmii_pins_a: eth1-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + + }; + + eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_TX_EN */ + , /* ETH_RMII_REF_CLK */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + + eth2_rmii_pins_a: eth2-rmii-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + ; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <1>; + }; + + pins2 { + pinmux = , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + bias-disable; + }; + }; + + eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { + pins1 { + pinmux = , /* ETH_RMII_TXD0 */ + , /* ETH_RMII_TXD1 */ + , /* ETH_RMII_ETHCK */ + , /* ETH_RMII_TX_EN */ + , /* ETH_MDIO */ + , /* ETH_MDC */ + , /* ETH_RMII_RXD0 */ + , /* ETH_RMII_RXD1 */ + ; /* ETH_RMII_CRS_DV */ + }; + }; + i2c1_pins_a: i2c1-0 { pins { pinmux = , /* I2C1_SCL */ From patchwork Thu Sep 28 12:24:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146340 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3652081vqu; Thu, 28 Sep 2023 16:00:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFh9bnaggmlDfkZL1Eh1xvyqo3e+aY92yPI6S/X3Cy8+Kp2D7jhn8hCH8DTDgr8U8RKqz4o X-Received: by 2002:a54:4e07:0:b0:3ab:5e9e:51f8 with SMTP id a7-20020a544e07000000b003ab5e9e51f8mr2447633oiy.9.1695942052803; Thu, 28 Sep 2023 16:00:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695942052; cv=none; d=google.com; s=arc-20160816; b=pzdJtiHOw+EV731d7rdFlzXmu5kvPQSYX00AlyTZmdiCrWJrTZPaU95DkDYV68J8lA jCeqzIqK+hpOv1HrKOUlF0o20gtUh/nUmWGWkk9Rl63XGrIZpIYXmWyMip8+I5/vrFkC E8tdqTCrb1zphMXdxhMV39afyF/rBFoQ04YXgTtzyy5CKlUzBa485cyVd8xD5AK26jfM UZn4k3nh2b8Nci8hCdN0YSL/Aa5iVSi4Rg5sI9cfh7EdWb05hiiyP4tkntD5Pq6YCG0r ocG1gPhg3eg++Bb4kLneyFJZ8cGM+Gr6cRcUhSHZdovrMQlgeJsgOSZMToB4b+25/3c3 fs1A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cI/WmtnEw+3W8sSwXOwhncPTGGl8x+aav3Xbrt5l6oA=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=tQu730DTx/m9O73DNsYNMqILsmIV5FPbix5RD0TSetbxSSHQEkmTM2NIrHBIgHCP3f EjxKuVPBqwLbdUCypCbQM4PALJF/hqsT5ZoohkhSiBgyR/bndI86jJ+DBCY0Ke93tL/1 lD7sqkZMQJzO3AY3XCEnmRwARaXw9OA7qjAAN399TCBtRp8rqi6Kt1kwbOZrNhUHFUyT mxdT7rDmCol5P+y69+QNSWNdlf81eW1iMVa+tPui2RbHbCF+w1VlI6oYv6NEcqnqxgXg JLR2gtJaN9z2shxGwMl4bPiBZLR9teDm20CPR4moG2kOJLxmM1rax5/nablOQSqOdqIg wpKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=I+HsJdvK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from lipwig.vger.email (lipwig.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 11/12] ARM: dts: stm32: add ethernet1 and ethernet2 for STM32MP135F-DK board Date: Thu, 28 Sep 2023 14:24:26 +0200 Message-ID: <20230928122427.313271-12-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:28:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778324133782066774 X-GMAIL-MSGID: 1778324133782066774 Add dual Ethernet: -Ethernet1: RMII with crystal -Ethernet2: RMII without crystal PHYs used are SMSC (LAN8742A) With Ethernet1, we can performed WoL from PHY instead of GMAC point of view. (in this case IRQ for WoL is managed as wakeup pin and configured in OS secure). Signed-off-by: Christophe Roullier --- arch/arm/boot/dts/st/stm32mp135f-dk.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp135f-dk.dts b/arch/arm/boot/dts/st/stm32mp135f-dk.dts index eea740d097c72..1316cc16f8dd9 100644 --- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts @@ -19,6 +19,8 @@ / { compatible = "st,stm32mp135f-dk", "st,stm32mp135"; aliases { + ethernet0 = ðernet1; + ethernet1 = ðernet2; serial0 = &uart4; serial1 = &usart1; serial2 = &uart8; @@ -93,6 +95,52 @@ channel@12 { }; }; +ðernet1 { + status = "okay"; + pinctrl-0 = <ð1_rmii_pins_a>; + pinctrl-1 = <ð1_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth1>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0_eth1: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; + reg = <0>; + wakeup-source; + }; + }; +}; + +ðernet2 { + status = "okay"; + pinctrl-0 = <ð2_rmii_pins_a>; + pinctrl-1 = <ð2_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0_eth2>; + st,ext-phyclk; + phy-supply = <&scmi_v3v3_sw>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0_eth2: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c131"; + reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>; + reg = <0>; + }; + }; +}; + &i2c1 { pinctrl-names = "default", "sleep"; pinctrl-0 = <&i2c1_pins_a>; From patchwork Thu Sep 28 12:24:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Roullier X-Patchwork-Id: 146213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp3452882vqu; Thu, 28 Sep 2023 09:51:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2mAYuNWDBmvFu++z8KgePNDeHYtAHq8n9zfu2t6q5Y2MJym/K2I3drwmimiorn0dls2Ve X-Received: by 2002:a17:90a:de85:b0:268:2523:652c with SMTP id n5-20020a17090ade8500b002682523652cmr1672217pjv.31.1695919892461; Thu, 28 Sep 2023 09:51:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695919892; cv=none; d=google.com; s=arc-20160816; b=wde2JlqQXETrZcRZ1H58LTHRSuZNWysfvioDziCGOJchpxI2Zxc0LMWI+t1pb3/zLS pDBOXpuPDa/sRYp7zNfKGZgwYqmuJn+SST+ee7LxA5T+q28ZxPwFDZsohf024IO/Si0X SoG0cIPlE/TMCJ4DL83SViHMoB/Mhq/A90m8SMo+H6KHK+UxCndV8Wfg5XxTU3F1CFf8 9IFJPVghFeJLdp5WEFAXB+3iOA+iBWZNF8SgUkx2BuaYqCWwLBnKQ048W8M1p6SuBAfk sLSvlDejKL5s4ma/fwoOynFVscwjL0LFifRqOK/M2u8y7mKYw/casA4l6R6nE8IgcMVj uzKw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zemeS+BhI32ZF8QdJ+UdBB3Jn6cezmIxj3rwJwlzC0U=; fh=Nrq3/ZyqAmcldX4TnYQJDytRSUiD1vJeQNniXh+eWjo=; b=mAAB1GSbpYJsr3uprdMeJ91LqYZXfsPgzIvdZewjronBLgGT6+i7IcovucKPaXOz+d BPOkl3W3fEVa8zGSBw1unYAlUxvIv/AsK++uHzHlIFGz5HNNXlgAHIgAQ6ZtBezk3zw+ WcyOx+RJv6lbPtcvzT88PqTZt+Q4wbgNUQcn6TFpHpX8FjmUwPyNgDgP4XSribTGGYtb K9MKeYcZ+LsqC7mULxoACHXFpv+dO4owh4T7jLLIBfbaV8NuFhdMFsmtN8IoX47yaNq0 QQIH56D0xw76tjNPIxrN5XSJLUD+Ta+j5kf7TkZnrQDbILXZD+zL94ZH957X4ejGAK+d 3kNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@foss.st.com header.s=selector1 header.b=y5pbBMOy; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=foss.st.com Received: from lipwig.vger.email (lipwig.vger.email. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Richard Cochran , Jose Abreu , Liam Girdwood , Mark Brown , Christophe Roullier CC: , , , , Subject: [PATCH v2 12/12] ARM: multi_v7_defconfig: Add MCP23S08 pinctrl support Date: Thu, 28 Sep 2023 14:24:27 +0200 Message-ID: <20230928122427.313271-13-christophe.roullier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230928122427.313271-1-christophe.roullier@foss.st.com> References: <20230928122427.313271-1-christophe.roullier@foss.st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.21.249] X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.267,Aquarius:18.0.980,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-09-28_11,2023-09-28_01,2023-05-22_02 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 28 Sep 2023 05:27:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778300896983042970 X-GMAIL-MSGID: 1778300896983042970 Need to enable MCP23S08 I/O expanders to manage Ethernet phy reset in STM32MP135F-DK board STMMAC driver defer is not silent, need to put this config in built-in to avoid huge of Ethernet messages Signed-off-by: Christophe Roullier --- arch/arm/configs/multi_v7_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index 23fc49f23d255..373f58f2d5b98 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -458,6 +458,7 @@ CONFIG_SPI_XILINX=y CONFIG_SPI_SPIDEV=y CONFIG_SPMI=y CONFIG_PINCTRL_AS3722=y +CONFIG_PINCTRL_MCP23S08=y CONFIG_PINCTRL_MICROCHIP_SGPIO=y CONFIG_PINCTRL_OCELOT=y CONFIG_PINCTRL_PALMAS=y