From patchwork Wed Sep 27 16:25:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 145461 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp2753800vqu; Wed, 27 Sep 2023 09:36:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE/a9w/mNUUl4eggXUd1Q73Jyr5P+cUiMnVpukRsUf2gHFL2StVp2UGYrkmVbTL2VYcJSEG X-Received: by 2002:a0d:d456:0:b0:59f:61b6:f584 with SMTP id w83-20020a0dd456000000b0059f61b6f584mr2857793ywd.9.1695832609091; Wed, 27 Sep 2023 09:36:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695832609; cv=none; d=google.com; s=arc-20160816; b=I4qJzlaa8mvDoN6Ghyjy2D96XOSsX0rM/wdUP3070voPU8LkETYL3JHkNxb+4oMQib acEjguWuh/m49afBD72BAQ6y9fYTB41ea4X/cRcGdEBEQlQkikbmNT+yhvliPAs1GzrR YSbdsgsAl/n1cP18R5mHwL4/EEoksbnsrOnshC9S55hHTkMo3n6ERTzA0InX5/GCtbFo EnrIMZwu0FAdbnU/4Lwd+AHqlWW4mDK2kNlVPbpQ6n6gDt2XmbOaGk3Li43n0NQ1tLlr sztrvgJe+SE1gjCfHXmvgRK09wMe6XezofnjVj7Fwgu47X6KWZe6MIT6XpRoix3Ilzwk 7aBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=LDCOC4NsY6mO1+zh4YaRAuvCeCZqeIQI86ED6pL+Lhw=; fh=RCG5UTJZL4x7EFXQRWT8toPnZJDmRxABMjXK1Kmzugw=; b=oyTgZ/aDv5flJyrKZ8ZC4HbHPaUsTI+b1pe8HOMZu4ABfhsPnou+4zkrAwDIsoExby Ahw0uuHdeRZycrgpC/SdKMRVAoH9+BufR3jovRIo7Tw6JDIZydmb3QC72FMJcuQMaGWQ K9Vk4BZe7NioHgT/T/cHJ3dHdoeOSYMpCfhz9POUAMSTsP9ACz05zpkULWTnNc8tXruc TI+fNG92ysfp1qAEayIyAnHD27+zY9QjKaPcDp+dKB491qsq5x8S+I4b6sWraP4rQt8M Ll7nYyFOB+9uiyCGsGxlX7l4SpAEOyUZ+0uZj2N8+pcsf3aiNCkB5xrtYUoWyKhyoRoa 5cXQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id j70-20020a638049000000b005777535a67bsi16336977pgd.746.2023.09.27.09.36.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 09:36:49 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id CFD0280A73E0; Wed, 27 Sep 2023 09:25:27 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbjI0QZY (ORCPT + 19 others); Wed, 27 Sep 2023 12:25:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229880AbjI0QZW (ORCPT ); Wed, 27 Sep 2023 12:25:22 -0400 Received: from relmlie6.idc.renesas.com (relmlor2.renesas.com [210.160.252.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id A474A91; Wed, 27 Sep 2023 09:25:20 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.03,181,1694703600"; d="scan'208";a="181181547" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie6.idc.renesas.com with ESMTP; 28 Sep 2023 01:25:20 +0900 Received: from mulinux.home (unknown [10.226.92.108]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id DD4FE401F564; Thu, 28 Sep 2023 01:25:15 +0900 (JST) From: Fabrizio Castro To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 1/2] spi: renesas,rzv2m-csi: Add CSI (SPI) target related property Date: Wed, 27 Sep 2023 17:25:07 +0100 Message-Id: <20230927162508.328736-2-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230927162508.328736-1-fabrizio.castro.jz@renesas.com> References: <20230927162508.328736-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 27 Sep 2023 09:25:27 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778209373909587188 X-GMAIL-MSGID: 1778209373909587188 The CSI IP found inside the Renesas RZ/V2M SoC can also work in SPI target mode. When working in target mode, the IP will make use of the SS (Slave Selection) pin, with "low" as default active level. The active level of SS can be changed to "high" upon setting property "spi-cs-high" to true. By default, the SS will be used in target mode, unless property "renesas,csi-no-ss" is set to true, in which case data will be shifted in and out purely based on clock activity, and the logic level of the SS pin will be completely ignored. Signed-off-by: Fabrizio Castro Reviewed-by: Rob Herring --- v1->v2: I have dropped properties renesas,csi-ss and renesas,csi-ss-high. I have added property renesas,csi-no-ss, and to configure SS as active high one now needs to use property spi-cs-high. I have also reworded the changelog to use a more modern terminology (host and target as opposed to master and slave). .../devicetree/bindings/spi/renesas,rzv2m-csi.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/renesas,rzv2m-csi.yaml b/Documentation/devicetree/bindings/spi/renesas,rzv2m-csi.yaml index e59183e53690..bed829837df1 100644 --- a/Documentation/devicetree/bindings/spi/renesas,rzv2m-csi.yaml +++ b/Documentation/devicetree/bindings/spi/renesas,rzv2m-csi.yaml @@ -39,6 +39,12 @@ properties: power-domains: maxItems: 1 + renesas,csi-no-ss: + type: boolean + description: + The CSI Slave Selection (SS) pin won't be used to enable transmission and + reception. Only available when in target mode. + required: - compatible - reg @@ -50,6 +56,9 @@ required: - '#address-cells' - '#size-cells' +dependencies: + renesas,csi-no-ss: [ spi-slave ] + unevaluatedProperties: false examples: From patchwork Wed Sep 27 16:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrizio Castro X-Patchwork-Id: 145459 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp2752502vqu; Wed, 27 Sep 2023 09:34:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGYsRLZw8wKMR4fiXIKfCdd7/AJ95ArltkPc/nykYYvaIjCqlrIMjxfvyQ1hf/B+ilC37ZQ X-Received: by 2002:a05:6808:610:b0:3ad:c5f3:36c6 with SMTP id y16-20020a056808061000b003adc5f336c6mr2994866oih.38.1695832479453; Wed, 27 Sep 2023 09:34:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695832479; cv=none; d=google.com; s=arc-20160816; b=CaU0tVOsqEzqJqMWIW8TZ1oDjYty2MsLPDEcVb/qKz0AL1ZHOt/uPlVW+JoLMfra8+ kxyk+EGYZMdw7loebVYUIuDvv0ylqcpNbF2HesVX4oiOYYRPIpXwmh34mEps66Qmqmz4 EmwtIDdkWCsybaamXoZPSvStXaWIUA0sHbpJ/pg6sDtUdEd3X1P7sHlE0WvIVlMsiz/P fVqBF3YScpYjO5WV3MPUUmaXpTLPzFV9qzgYKxUunrb6VVrcNw4H+lBoawX1nUBg3+RX oU80tMnjop60g3tY5I8/lLWWXDqFCfg4BM/9ZVcppoLCzor1rDpfCtrb60d3acQGdAWs Sv7g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=WdSTWRfvzx3W9Yd6ElSmt5P053GnoM8SE70LY6NhjhE=; fh=RCG5UTJZL4x7EFXQRWT8toPnZJDmRxABMjXK1Kmzugw=; b=c1gjeCRf9qZw+AB+2jnO5xA70XfR9D5YWhuxHX/UMwu0KSsSuNGHuw0Xuvvwe4Yzz+ 6/pVnC83TCQsEHTGMbwhL4gBOKkXGgP/6RInmJ97KKC8DUvWU6+kDBDO+q8+87rjwKll 0BHh23zII6x1DTsyMEEwHAK18L0x2GbPN6QHuLRlLqIeNYGrN+Z0ceiDsHXw4uigDXiP 9jbEi5PjOLWGT+dsj1Ik69cQEgEce8HoZy+UCuxgJT3xbE+CIVcG6VIpUfDLLPyJATpy fNDyaJKNHr7QAh1CPVSfFKMB1YOHlUEFeDITjeJFCAUMbZrxfpWJSiW/MkzXG76CroSz 651Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id v10-20020a63610a000000b00565e87d8707si16571762pgb.496.2023.09.27.09.34.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Sep 2023 09:34:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=renesas.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 2F81C807E915; Wed, 27 Sep 2023 09:25:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231702AbjI0QZb (ORCPT + 19 others); Wed, 27 Sep 2023 12:25:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbjI0QZ2 (ORCPT ); Wed, 27 Sep 2023 12:25:28 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 2AEE7EB; Wed, 27 Sep 2023 09:25:25 -0700 (PDT) X-IronPort-AV: E=Sophos;i="6.03,181,1694703600"; d="scan'208";a="177447629" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 28 Sep 2023 01:25:24 +0900 Received: from mulinux.home (unknown [10.226.92.108]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id ACBD9401F564; Thu, 28 Sep 2023 01:25:20 +0900 (JST) From: Fabrizio Castro To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven Cc: Fabrizio Castro , Magnus Damm , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Chris Paterson , Biju Das , Lad Prabhakar Subject: [PATCH v2 2/2] spi: rzv2m-csi: Add target mode support Date: Wed, 27 Sep 2023 17:25:08 +0100 Message-Id: <20230927162508.328736-3-fabrizio.castro.jz@renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230927162508.328736-1-fabrizio.castro.jz@renesas.com> References: <20230927162508.328736-1-fabrizio.castro.jz@renesas.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 27 Sep 2023 09:25:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778209237785645996 X-GMAIL-MSGID: 1778209237785645996 The CSI IP found inside the Renesas RZ/V2M SoC supports both SPI host and SPI target roles. When working in target mode, the CSI IP has the option of using its Slave Selection (SS) pin to enable TX and RX operations. Since the SPI target cannot control the clock, when working as target it's best not to stop operations during a transfer, as by doing so the IP will not send or receive data, regardless of clock and active level on pin SS. A side effect from not stopping operations is that the RX FIFO needs to be flushed, word by word, when RX data needs to be discarded. Finally, when in target mode timings are tighter, as missing a deadline translates to errors being thrown, resulting in aborting the transfer. In order to speed things up, we can avoid waiting for the TX FIFO to be empty, we can just wait for the RX FIFO to contain at least the number of words that we expect. Add target support to the currently existing CSI driver. Signed-off-by: Fabrizio Castro --- v1->v2: I have dropped properties renesas,csi-ss and renesas,csi-ss-high. The driver now uses property renesas,csi-no-ss to disable the SS pin. The driver now looks for SPI_CS_HIGH within the SPI mode field to configure the SS pin as active high. I have dropped "depends on SPI_SLAVE" from Kconfig. The current role doesn't get stored within the private data structure anymore, I am using spi_controller_is_target instead to check the role. I have also purged "master" and "slave" as naming schemes, I am now using "host" and "target" (in the code and also in the changelog) and related APIs instead. drivers/spi/Kconfig | 3 +- drivers/spi/spi-rzv2m-csi.c | 127 +++++++++++++++++++++++------------- 2 files changed, 85 insertions(+), 45 deletions(-) diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 2c21d5b96fdc..d4ac184bce95 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -862,7 +862,8 @@ config SPI_RZV2M_CSI tristate "Renesas RZ/V2M CSI controller" depends on ARCH_RENESAS || COMPILE_TEST help - SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI) + SPI driver for Renesas RZ/V2M Clocked Serial Interface (CSI). + CSI supports both SPI host and SPI target roles. config SPI_QCOM_QSPI tristate "QTI QSPI controller" diff --git a/drivers/spi/spi-rzv2m-csi.c b/drivers/spi/spi-rzv2m-csi.c index d0f51b17aa7c..741e0f44c49c 100644 --- a/drivers/spi/spi-rzv2m-csi.c +++ b/drivers/spi/spi-rzv2m-csi.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -38,6 +39,9 @@ #define CSI_MODE_SETUP 0x00000040 /* CSI_CLKSEL */ +#define CSI_CLKSEL_SS_ENA BIT(19) +#define CSI_CLKSEL_SS_POL BIT(18) +#define CSI_CLKSEL_SS (CSI_CLKSEL_SS_ENA | CSI_CLKSEL_SS_POL) #define CSI_CLKSEL_CKP BIT(17) #define CSI_CLKSEL_DAP BIT(16) #define CSI_CLKSEL_MODE (CSI_CLKSEL_CKP|CSI_CLKSEL_DAP) @@ -82,6 +86,10 @@ #define CSI_MAX_SPI_SCKO (8 * HZ_PER_MHZ) +#define CSI_CLKSEL_SS_DISABLED 0 +#define CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW BIT(1) +#define CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH GENMASK(1, 0) + struct rzv2m_csi_priv { void __iomem *base; struct clk *csiclk; @@ -99,6 +107,8 @@ struct rzv2m_csi_priv { wait_queue_head_t wait; u32 errors; u32 status; + bool target_aborted; + bool use_ss_pin; }; static void rzv2m_csi_reg_write_bit(const struct rzv2m_csi_priv *csi, @@ -193,6 +203,14 @@ static int rzv2m_csi_read_rxfifo(struct rzv2m_csi_priv *csi) return 0; } +static inline void rzv2m_csi_empty_rxfifo(struct rzv2m_csi_priv *csi) +{ + unsigned int i; + + for (i = 0; i < csi->words_to_transfer; i++) + readl(csi->base + CSI_IFIFO); +} + static inline void rzv2m_csi_calc_current_transfer(struct rzv2m_csi_priv *csi) { unsigned int bytes_transferred = max(csi->bytes_received, csi->bytes_sent); @@ -279,32 +297,23 @@ static int rzv2m_csi_wait_for_interrupt(struct rzv2m_csi_priv *csi, rzv2m_csi_enable_irqs(csi, enable_bits); - ret = wait_event_timeout(csi->wait, - ((csi->status & wait_mask) == wait_mask) || - csi->errors, HZ); + if (spi_controller_is_target(csi->controller)) { + ret = wait_event_interruptible(csi->wait, + ((csi->status & wait_mask) == wait_mask) || + csi->errors || csi->target_aborted); + if (ret || csi->target_aborted) + ret = -EINTR; + } else { + ret = wait_event_timeout(csi->wait, + ((csi->status & wait_mask) == wait_mask) || + csi->errors, HZ) == 0 ? -ETIMEDOUT : 0; + } rzv2m_csi_disable_irqs(csi, enable_bits); if (csi->errors) return -EIO; - if (!ret) - return -ETIMEDOUT; - - return 0; -} - -static int rzv2m_csi_wait_for_tx_empty(struct rzv2m_csi_priv *csi) -{ - int ret; - - if (readl(csi->base + CSI_OFIFOL) == 0) - return 0; - - ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_TREND, CSI_CNT_TREND_E); - if (ret == -ETIMEDOUT) - csi->errors |= TX_TIMEOUT_ERROR; - return ret; } @@ -312,7 +321,7 @@ static inline int rzv2m_csi_wait_for_rx_ready(struct rzv2m_csi_priv *csi) { int ret; - if (readl(csi->base + CSI_IFIFOL) == csi->bytes_to_transfer) + if (readl(csi->base + CSI_IFIFOL) >= csi->bytes_to_transfer) return 0; ret = rzv2m_csi_wait_for_interrupt(csi, CSI_INT_R_TRGR, @@ -388,6 +397,7 @@ static void rzv2m_csi_setup_operating_mode(struct rzv2m_csi_priv *csi, static int rzv2m_csi_setup(struct spi_device *spi) { struct rzv2m_csi_priv *csi = spi_controller_get_devdata(spi->controller); + u32 slave_selection = CSI_CLKSEL_SS_DISABLED; int ret; rzv2m_csi_sw_reset(csi, 0); @@ -402,8 +412,17 @@ static int rzv2m_csi_setup(struct spi_device *spi) rzv2m_csi_reg_write_bit(csi, CSI_MODE, CSI_MODE_DIR, !!(spi->mode & SPI_LSB_FIRST)); - /* Set the operation mode as master */ - rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, 0); + /* Set the role, 1 for target and 0 for host */ + rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SLAVE, + !!spi_controller_is_target(csi->controller)); + + if (csi->use_ss_pin) + slave_selection = spi->mode & SPI_CS_HIGH ? + CSI_CLKSEL_SS_ENABLED_ACTIVE_HIGH : + CSI_CLKSEL_SS_ENABLED_ACTIVE_LOW; + + /* Configure the slave selection (SS) pin */ + rzv2m_csi_reg_write_bit(csi, CSI_CLKSEL, CSI_CLKSEL_SS, slave_selection); /* Give the IP a SW reset */ ret = rzv2m_csi_sw_reset(csi, 1); @@ -431,9 +450,13 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi) /* Make sure the TX FIFO is empty */ writel(0, csi->base + CSI_OFIFOL); + /* Make sure the RX FIFO is empty */ + writel(0, csi->base + CSI_IFIFOL); + csi->bytes_sent = 0; csi->bytes_received = 0; csi->errors = 0; + csi->target_aborted = false; rzv2m_csi_disable_all_irqs(csi); rzv2m_csi_clear_all_irqs(csi); @@ -452,28 +475,21 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi) rzv2m_csi_enable_irqs(csi, CSI_INT_OVERF | CSI_INT_UNDER); - /* Make sure the RX FIFO is empty */ - writel(0, csi->base + CSI_IFIFOL); - writel(readl(csi->base + CSI_INT), csi->base + CSI_INT); csi->status = 0; - rzv2m_csi_start_stop_operation(csi, 1, false); - /* TX */ if (csi->txbuf) { ret = rzv2m_csi_fill_txfifo(csi); if (ret) break; - ret = rzv2m_csi_wait_for_tx_empty(csi); - if (ret) - break; - if (csi->bytes_sent == csi->buffer_len) tx_completed = true; } + rzv2m_csi_start_stop_operation(csi, 1, false); + /* * Make sure the RX FIFO contains the desired number of words. * We then either flush its content, or we copy it onto @@ -483,31 +499,28 @@ static int rzv2m_csi_pio_transfer(struct rzv2m_csi_priv *csi) if (ret) break; - /* RX */ - if (csi->rxbuf) { + if (!spi_controller_is_target(csi->controller)) rzv2m_csi_start_stop_operation(csi, 0, false); + /* RX */ + if (csi->rxbuf) { ret = rzv2m_csi_read_rxfifo(csi); if (ret) break; if (csi->bytes_received == csi->buffer_len) rx_completed = true; + } else { + rzv2m_csi_empty_rxfifo(csi); } - ret = rzv2m_csi_start_stop_operation(csi, 0, true); - if (ret) - goto pio_quit; - if (csi->errors) { ret = -EIO; - goto pio_quit; + break; } } rzv2m_csi_start_stop_operation(csi, 0, true); - -pio_quit: rzv2m_csi_disable_all_irqs(csi); rzv2m_csi_enable_rx_trigger(csi, false); rzv2m_csi_clear_all_irqs(csi); @@ -529,7 +542,8 @@ static int rzv2m_csi_transfer_one(struct spi_controller *controller, rzv2m_csi_setup_operating_mode(csi, transfer); - rzv2m_csi_setup_clock(csi, transfer->speed_hz); + if (!spi_controller_is_target(csi->controller)) + rzv2m_csi_setup_clock(csi, transfer->speed_hz); ret = rzv2m_csi_pio_transfer(csi); if (ret) { @@ -546,24 +560,48 @@ static int rzv2m_csi_transfer_one(struct spi_controller *controller, return ret; } +static int rzv2m_csi_target_abort(struct spi_controller *ctlr) +{ + struct rzv2m_csi_priv *csi = spi_controller_get_devdata(ctlr); + + csi->target_aborted = true; + wake_up(&csi->wait); + + return 0; +} + static int rzv2m_csi_probe(struct platform_device *pdev) { + struct device_node *np = pdev->dev.of_node; struct spi_controller *controller; struct device *dev = &pdev->dev; struct rzv2m_csi_priv *csi; struct reset_control *rstc; + bool target_mode; int irq; int ret; - controller = devm_spi_alloc_host(dev, sizeof(*csi)); + target_mode = of_property_read_bool(np, "spi-slave"); + + if (target_mode) + controller = devm_spi_alloc_target(dev, sizeof(*csi)); + else + controller = devm_spi_alloc_host(dev, sizeof(*csi)); + if (!controller) return -ENOMEM; csi = spi_controller_get_devdata(controller); platform_set_drvdata(pdev, csi); + csi->use_ss_pin = false; + if (spi_controller_is_target(controller) && + !of_property_read_bool(np, "renesas,csi-no-ss")) + csi->use_ss_pin = true; + csi->dev = dev; csi->controller = controller; + csi->target_aborted = false; csi->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(csi->base)) @@ -589,11 +627,12 @@ static int rzv2m_csi_probe(struct platform_device *pdev) init_waitqueue_head(&csi->wait); - controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; + controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_CS_HIGH; controller->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); controller->setup = rzv2m_csi_setup; controller->transfer_one = rzv2m_csi_transfer_one; controller->use_gpio_descriptors = true; + controller->target_abort = rzv2m_csi_target_abort; device_set_node(&controller->dev, dev_fwnode(dev));