From patchwork Tue Sep 26 15:26:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 144939 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:cae8:0:b0:403:3b70:6f57 with SMTP id r8csp2000156vqu; Tue, 26 Sep 2023 08:27:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxKMQ/+urR/juB25jwOkdMgoAHFthQuGTIPMpzx17QTxSYyn4ERYm4pnGRCkqF40iruQhM X-Received: by 2002:a05:6000:180e:b0:321:65f3:4100 with SMTP id m14-20020a056000180e00b0032165f34100mr8465727wrh.7.1695742051828; Tue, 26 Sep 2023 08:27:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695742051; cv=none; d=google.com; s=arc-20160816; b=ZdW4SxZ8qMAVCaZ3fg07bFuXt9rRS80+RGXz8Sug4ZrWDEryK8mJx5nj7WmoXGIQqg eNlvYShvepceylK3E5rQsFpF+nY6quzv6UrCvs3SchjFwxmht+FG466StqqP21aKZyQp N4O2RTRPweeRBBW72Eo6WoFlQop3oOqxIi2KE1mX5Fxc9nlgorEpRsGnFR/dSFlb56F0 d23t/XGZE90D2UlCRk0TQn/DPdoA6ua/Z89Qpq+5yNJOzizc2h5I8FO41622IjQLmwYz Jui4uiMIerZ2pXs6Ow6ycePkWCfCqY/uUiUqSFPYREzrVJuywRi3l+Hqw8oL1NnhYfUv lzCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dmarc-filter:delivered-to; bh=plpG3BkRpM0X7/IIZdT+gprMTVnCDqI6AU8Dq4M7vMw=; fh=12MRPJmZ1mgDpHqWoogMKqnaGRGM2b7lcuJroqfjJiw=; b=QOp2CSp32zvGoyWSf/LIWXgq4nWtYEiq3fmTu3WgjoBeXHQ30LxhCE8JXxKa0ngHU/ 2AaqITZLs6rTo/YPStFj9dlvwkPdqg5Np+49YaNxeP07mc8zYEBRC09m4YPUJ2OFM5Du 2BvvsVaYpX85CWzZW2wmkPB+gkkq+Jq7LyjH0J8NpFITri8Y5ZkeHMJlfxQE77fjxXhS ecxXJprf0ElcVgsEjB3QHyen1cn4afieudo6WYXn6k/H6UUovOXBf16shE6V7dIltsCv IU9WacUVrSqHdAiOINuxiJQyMsdA32bcg0I4wo7OHVzLPP6aiWBxwe+92B/lCu2aYyWN 0U8w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id ss2-20020a170907c00200b009ae68e40942si11928759ejc.477.2023.09.26.08.27.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 08:27:31 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 45DDF3861849 for ; Tue, 26 Sep 2023 15:27:19 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id C5CCA3858404 for ; Tue, 26 Sep 2023 15:26:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C5CCA3858404 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp67t1695742004tqcr8zlz Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 26 Sep 2023 23:26:43 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: QdNbrVbAPlvzmNXOxhG5JpWBrFPYI5Cz3Kcx/x9WoMOMGP4YqkQwg2RT+caw8 vINGT9qpuSuIY563yP3RLvd0lJ3JdPiIZI6yCFCKSa5WzWmPdoZKwoxvoVQ9UDSbJJf8gNm HIeiSJbur9+FuW3e5ls9gUilaK+IUOKepAv66V5ERbW2VL6X6lbmYEPNckL27s0l9sMQdbC g3Ly17pFXpuJ6Qn/9S3HboZzKAaEzDcS+rChJnt3SKUDItilScQ9S0Be+ufLiycmDDaX4+Q 9edAwWwfYtdK8rRcK1EHLlCF+UIf7lruEUyFgHkKQASjUgi19GoOy549maMS9oLFR2XqBQp Na+mNfVEAppMAAASG1KAlkDzxTMkOvlM7HQcX4iCx7BAUY39ODpRJ8xb5A6X+Vu5H6tMHHQ X-QQ-GoodBg: 2 X-BIZMAIL-ID: 4214204812936364400 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH V3] RISC-V: Remove mem-to-mem VLS move pattern[PR111566] Date: Tue, 26 Sep 2023 23:26:42 +0800 Message-Id: <20230926152642.3345241-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-10.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778114417436558880 X-GMAIL-MSGID: 1778114417436558880 PR target/111566 gcc/ChangeLog: * config/riscv/vector.md (*mov_mem_to_mem): Remove. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/mov-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/vls/mov-10.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-3.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-5.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-7.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-8.c: Ditto. * gcc.target/riscv/rvv/autovec/vls/mov-9.c: Ditto.1 * gcc.target/riscv/rvv/autovec/vls/mov-2.c: Removed. * gcc.target/riscv/rvv/autovec/vls/mov-4.c: Removed. * gcc.target/riscv/rvv/autovec/vls/mov-6.c: Removed. * gcc.target/riscv/rvv/fortran/pr111566.f90: New test. --- gcc/config/riscv/vector.md | 40 +--------------- .../gcc.target/riscv/rvv/autovec/vls/mov-1.c | 48 ------------------- .../gcc.target/riscv/rvv/autovec/vls/mov-10.c | 12 ----- .../gcc.target/riscv/rvv/autovec/vls/mov-2.c | 19 -------- .../gcc.target/riscv/rvv/autovec/vls/mov-3.c | 36 -------------- .../gcc.target/riscv/rvv/autovec/vls/mov-4.c | 19 -------- .../gcc.target/riscv/rvv/autovec/vls/mov-5.c | 24 ---------- .../gcc.target/riscv/rvv/autovec/vls/mov-6.c | 19 -------- .../gcc.target/riscv/rvv/autovec/vls/mov-7.c | 12 ----- .../gcc.target/riscv/rvv/autovec/vls/mov-8.c | 36 -------------- .../gcc.target/riscv/rvv/autovec/vls/mov-9.c | 24 ---------- .../gcc.target/riscv/rvv/fortran/pr111566.f90 | 31 ++++++++++++ 12 files changed, 33 insertions(+), 287 deletions(-) delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c delete mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index d5300a33946..57205025ff8 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -1222,48 +1222,12 @@ DONE; }) -(define_insn_and_split "*mov_mem_to_mem" - [(set (match_operand:VLS_AVL_IMM 0 "memory_operand") - (match_operand:VLS_AVL_IMM 1 "memory_operand"))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] - { - if (GET_MODE_BITSIZE (mode).to_constant () <= MAX_BITS_PER_WORD) - { - /* Opitmize the following case: - - typedef int8_t v2qi __attribute__ ((vector_size (2))); - v2qi v = *(v2qi*)in; - *(v2qi*)out = v; - - We prefer scalar load/store instead of vle.v/vse.v when - the VLS modes size is smaller scalar mode. */ - machine_mode mode; - unsigned size = GET_MODE_BITSIZE (mode).to_constant (); - if (FLOAT_MODE_P (mode)) - mode = mode_for_size (size, MODE_FLOAT, 0).require (); - else - mode = mode_for_size (size, MODE_INT, 0).require (); - emit_move_insn (gen_lowpart (mode, operands[0]), - gen_lowpart (mode, operands[1])); - } - else - { - operands[1] = force_reg (mode, operands[1]); - emit_move_insn (operands[0], operands[1]); - } - DONE; - } - [(set_attr "type" "vmov")] -) - (define_insn_and_split "*mov" [(set (match_operand:VLS_AVL_IMM 0 "reg_or_mem_operand" "=vr, m, vr") (match_operand:VLS_AVL_IMM 1 "reg_or_mem_operand" " m,vr, vr"))] "TARGET_VECTOR - && (register_operand (operands[0], mode) + && (can_create_pseudo_p () + || register_operand (operands[0], mode) || register_operand (operands[1], mode))" "@ # diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c index aedf98819bb..24bb7240db8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-1.c @@ -4,54 +4,6 @@ #include "def.h" -/* -** mov0: -** lbu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sb\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (int8_t *in, int8_t *out) -{ - v1qi v = *(v1qi*)in; - *(v1qi*)out = v; -} - -/* -** mov1: -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov1 (int8_t *in, int8_t *out) -{ - v2qi v = *(v2qi*)in; - *(v2qi*)out = v; -} - -/* -** mov2: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov2 (int8_t *in, int8_t *out) -{ - v4qi v = *(v4qi*)in; - *(v4qi*)out = v; -} - -/* -** mov3: -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov3 (int8_t *in, int8_t *out) -{ - v8qi v = *(v8qi*)in; - *(v8qi*)out = v; -} - /* ** mov4: ** vsetivli\s+zero,\s*16,\s*e8,\s*mf8,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c index 5e9615412b7..cae96b3be3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-10.c @@ -4,18 +4,6 @@ #include "def.h" -/* -** mov0: -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (double *in, double *out) -{ - v1df v = *(v1df*)in; - *(v1df*)out = v; -} - /* ** mov1: ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c deleted file mode 100644 index 10ae1972db7..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-2.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "def.h" - -/* -** mov: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** ret -*/ -void mov (int8_t *in, int8_t *out) -{ - v8qi v = *(v8qi*)in; - *(v8qi*)out = v; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c index f2880ae5e77..86ce22896c5 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-3.c @@ -4,42 +4,6 @@ #include "def.h" -/* -** mov0: -** lhu\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (int16_t *in, int16_t *out) -{ - v1hi v = *(v1hi*)in; - *(v1hi*)out = v; -} - -/* -** mov1: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov1 (int16_t *in, int16_t *out) -{ - v2hi v = *(v2hi*)in; - *(v2hi*)out = v; -} - -/* -** mov2: -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov2 (int16_t *in, int16_t *out) -{ - v4hi v = *(v4hi*)in; - *(v4hi*)out = v; -} - /* ** mov3: ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c deleted file mode 100644 index f81f1697d65..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-4.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "def.h" - -/* -** mov: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** ret -*/ -void mov (int16_t *in, int16_t *out) -{ - v4hi v = *(v4hi*)in; - *(v4hi*)out = v; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c index c30ed8f76f5..04475207966 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-5.c @@ -4,30 +4,6 @@ #include "def.h" -/* -** mov0: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (int32_t *in, int32_t *out) -{ - v1si v = *(v1si*)in; - *(v1si*)out = v; -} - -/* -** mov1: -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov1 (int32_t *in, int32_t *out) -{ - v2si v = *(v2si*)in; - *(v2si*)out = v; -} - /* ** mov2: ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c deleted file mode 100644 index d6dbff1caa9..00000000000 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-6.c +++ /dev/null @@ -1,19 +0,0 @@ -/* { dg-do compile } */ -/* { dg-options "-march=rv32gcv_zvfh_zvl4096b -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ -/* { dg-final { check-function-bodies "**" "" } } */ - -#include "def.h" - -/* -** mov: -** lw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** lw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sw\s+[a-x0-9]+,4\s*\([a-x0-9]+\) -** ret -*/ -void mov (int32_t *in, int32_t *out) -{ - v2si v = *(v2si*)in; - *(v2si*)out = v; -} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c index 46509e367c3..d0674a47a14 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-7.c @@ -4,18 +4,6 @@ #include "def.h" -/* -** mov0: -** ld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** sd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (int64_t *in, int64_t *out) -{ - v1di v = *(v1di*)in; - *(v1di*)out = v; -} - /* ** mov1: ** vsetivli\s+zero,\s*2,\s*e64,\s*m1,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c index 1cba7ddad94..b905c74d43b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-8.c @@ -4,42 +4,6 @@ #include "def.h" -/* -** mov0: -** flh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsh\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (_Float16 *in, _Float16 *out) -{ - v1hf v = *(v1hf*)in; - *(v1hf*)out = v; -} - -/* -** mov1: -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov1 (_Float16 *in, _Float16 *out) -{ - v2hf v = *(v2hf*)in; - *(v2hf*)out = v; -} - -/* -** mov2: -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov2 (_Float16 *in, _Float16 *out) -{ - v4hf v = *(v4hf*)in; - *(v4hf*)out = v; -} - /* ** mov3: ** vsetivli\s+zero,\s*8,\s*e16,\s*mf4,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c index 0773f6a70f3..5f9bc052e97 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/mov-9.c @@ -4,30 +4,6 @@ #include "def.h" -/* -** mov0: -** flw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsw\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov0 (float *in, float *out) -{ - v1sf v = *(v1sf*)in; - *(v1sf*)out = v; -} - -/* -** mov1: -** fld\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** fsd\s+[a-x0-9]+,0\s*\([a-x0-9]+\) -** ret -*/ -void mov1 (float *in, float *out) -{ - v2sf v = *(v2sf*)in; - *(v2sf*)out = v; -} - /* ** mov2: ** vsetivli\s+zero,\s*4,\s*e32,\s*mf2,\s*t[au],\s*m[au] diff --git a/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 new file mode 100644 index 00000000000..2e30dc9bfaa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/pr111566.f90 @@ -0,0 +1,31 @@ +! { dg-do compile } +! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -fallow-argument-mismatch -fmax-stack-var-size=65536 -S -std=legacy -w" } + +module a + integer,parameter :: SHR_KIND_R8 = selected_real_kind(12) +end module a +module b + use a, c => shr_kind_r8 +contains + subroutine d(cg , km, i1, i2) + real (c) ch(i2,km) + real (c) cg(4,i1:i2,km) + real dc(i2,km) + real(c) ci(i2,km) + real(c) cj(i2,km) + do k=2,ck + do i=i1,0 + cl = ci(i,k) *ci(i,1) / cj(i,k)+ch(i,1) + cm = cg(1,i,k) - min(e,cg(1,i,co)) + dc(i,k) = sign(cm, cl) + enddo + enddo + if ( cq == 0 ) then + do i=i1,i2 + if( cr <= cs ) then + cg= sign( min(ct, cg), cg) + endif + enddo + endif + end subroutine d +end module b