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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id kz4-20020a170902f9c400b001bda93595d9si4778707plb.604.2023.09.26.03.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 03:48:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=tecon.ru Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 6FE84802DD00; Tue, 26 Sep 2023 03:33:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234339AbjIZKd5 (ORCPT + 27 others); Tue, 26 Sep 2023 06:33:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229445AbjIZKdz (ORCPT ); Tue, 26 Sep 2023 06:33:55 -0400 X-Greylist: delayed 302 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Tue, 26 Sep 2023 03:33:46 PDT Received: from mail.tecon.ru (mail.tecon.ru [82.112.190.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3793E9 for ; Tue, 26 Sep 2023 03:33:46 -0700 (PDT) From: Dmitry Dunaev CC: , Dmitry Dunaev , Thomas Gleixner , Marc Zyngier , Paul Walmsley , Palmer Dabbelt , Albert Ou , , Subject: [PATCH] irqchip/riscv-intc: Mark INTC nodes for secondary CPUs as initialized. Date: Tue, 26 Sep 2023 13:28:01 +0300 Message-ID: <20230926102801.1591126-1-dunaev@tecon.ru> MIME-Version: 1.0 X-Spam-Status: No, score=0.1 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,TO_EQ_FM_DIRECT_MX autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 26 Sep 2023 03:33:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778096846425928413 X-GMAIL-MSGID: 1778096846425928413 The current Linux driver irq-riscv-intc initialize IRQ domain only once, when init function called on primary hart. In other cases no IRQ domain is created and no operation on interrupt-controller node is performed. This is cause of that no common Linux driver can use per-cpu interrupts mapped to several CPUs because fwnode of secondary cores INTC is not marked as initialized. This device is always will be marked as deferred. For example the system with devicetree cpu0: cpu@0 { cpu0_intc: interrupt-controller { interrupt-controller; compatible = riscv,cpu-intc; }; }; cpu1: cpu@1 { cpu1_intc: interrupt-controller { interrupt-controller; compatible = riscv,cpu-intc; }; }; buserr { compatible = riscv,buserr; interrupts-extended = <&cpu0_intc 16 &cpu1_intc 16>; }; will always report 'buserr' node as deferred without calling any bus probe function. This patch will mark all secondary nodes passed to irq-riscv-intc driver init function as initialized to be able to act as correct IRQ phandle node. Signed-off-by: Dmitry Dunaev --- drivers/irqchip/irq-riscv-intc.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 4adeee1bc391..c01a4e8d4983 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -155,8 +155,10 @@ static int __init riscv_intc_init(struct device_node *node, * for each INTC DT node. We only need to do INTC initialization * for the INTC DT node belonging to boot CPU (or boot HART). */ - if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) + if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) { + fwnode_dev_initialized(of_node_to_fwnode(node), true); return 0; + } return riscv_intc_init_common(of_node_to_fwnode(node)); } @@ -179,8 +181,10 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, * for each INTC. We only do INTC initialization * for the INTC belonging to the boot CPU (or boot HART). */ - if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) { + fwnode_dev_initialized(of_node_to_fwnode(node), true); return 0; + } fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); if (!fn) {