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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j21-20020a170906831500b0099bce8c04d8si10835464ejx.141.2023.09.26.00.26.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Sep 2023 00:26:14 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=je2QEhpo; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id D87FC385CCB5 for ; Tue, 26 Sep 2023 07:26:06 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (unknown [198.175.65.0]) by sourceware.org (Postfix) with ESMTPS id C5BF1385C6E8 for ; Tue, 26 Sep 2023 07:25:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C5BF1385C6E8 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695713102; x=1727249102; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=8a8z7HPYYoBobkkf8sygbMV+3MRDEXIfbLycq3nLlb4=; b=je2QEhpo8uHSImDttsC1YEVY4kOWA4tmXNhIT2+p6OsR6qsKavmM+u0O B7/zZShnLFI1CvjrtF6wuPjz0XQUtO7zQkdo4wD3ktqdzKKeTGGTychWA A60efxdAmMCEz3XoHe/xLB/RZFcedvK827A56rjC5Amwq1IVOiw5B1JyW mYesbgXoac/2r4UbqS/tVBoix0cEhlTTdtoex+TRkRrdOqinya1Ml6MoW dTRlAyxtvpgZTKfwdvTANGPrGggIqoHKuYt2n09fcm7Pkl1p3XMGNg5S8 AG+PlTgv5j2fWEbu1FWxGuB554dTr8H3sns9DIEcMXz32AZ5InEtkL289 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="151655" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="151655" Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Sep 2023 00:25:01 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="725348360" X-IronPort-AV: E=Sophos;i="6.03,177,1694761200"; d="scan'208";a="725348360" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga006.jf.intel.com with ESMTP; 26 Sep 2023 00:24:56 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 926D11005662; Tue, 26 Sep 2023 15:24:55 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Support FP rint auto-vectorization Date: Tue, 26 Sep 2023 15:24:52 +0800 Message-Id: <20230926072452.3580823-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778084137922612324 X-GMAIL-MSGID: 1778084137922612324 From: Pan Li This patch would like to support auto-vectorization for the rint API in math.h. It depends on the -ffast-math option. When we would like to call rint/rintf like v2 = rint (v1), we will convert it into below insns (reference the implementation of llvm). * vfcvt.x.f v3, v1 * vfcvt.f.x v2, v3 However, the floating point value may not need the cvt as above if its mantissa is zero. Take single precision floating point as example: Assume we have RTZ rounding mode +------------+---------------+-----------------+ | raw float | binary layout | after int | +------------+---------------+-----------------+ | -8388607.5 | 0xcaffffff | -8388607.0 | | 8388607.5 | 0x4affffff | 8388607.0 | | 8388608.0 | 0x4b000000 | 8388608.0 | | 8388609.0 | 0x4b000001 | 8388609.0 | +------------+---------------+-----------------+ All single floating point >= 8388608.0 will have all zero mantisaa. We leverage vmflt and mask to filter them out in vector and only do the cvt on mask. Befor this patch: math-rint-1.c:21:1: missed: couldn't vectorize loop ... .L3: flw fa0,0(s0) addi s0,s0,4 addi s1,s1,4 call rint fsw fa0,-4(s1) bne s0,s2,.L3 After this patch: vfabs.v v2,v1 vmflt.vf v0,v2,fa5 vfcvt.x.f.v v4,v1,v0.t vfcvt.f.x.v v2,v4,v0.t vfsgnj.vv v2,v2,v1 Please note VLS mode is also involved in this patch and covered by the test cases. gcc/ChangeLog: * config/riscv/autovec.md (rint2): New pattern. * config/riscv/riscv-protos.h (expand_vec_rint): New function decl. * config/riscv/riscv-v.cc (expand_vec_rint): New function impl. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/unop/math-rint-0.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-rint-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-rint-2.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-rint-3.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c: New test. * gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c: New test. * gcc.target/riscv/rvv/autovec/vls/math-rint-1.c: New test. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/autovec.md | 10 ++++ gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 22 +++++++ .../riscv/rvv/autovec/unop/math-rint-0.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-rint-1.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-rint-2.c | 18 ++++++ .../riscv/rvv/autovec/unop/math-rint-3.c | 20 +++++++ .../riscv/rvv/autovec/unop/math-rint-run-1.c | 48 +++++++++++++++ .../riscv/rvv/autovec/unop/math-rint-run-2.c | 48 +++++++++++++++ .../riscv/rvv/autovec/vls/math-rint-1.c | 58 +++++++++++++++++++ 10 files changed, 261 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index b47f086f5e6..1d2fca60e98 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -2241,3 +2241,13 @@ (define_expand "nearbyint2" DONE; } ) + +(define_expand "rint2" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand:V_VLSF 1 "register_operand")] + "TARGET_VECTOR && !flag_trapping_math && !flag_rounding_math" + { + riscv_vector::expand_vec_rint (operands[0], operands[1], mode, mode); + DONE; + } +) diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index f87bdef0f71..629adeea94c 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -462,6 +462,7 @@ void expand_reduction (unsigned, unsigned, rtx *, rtx); void expand_vec_ceil (rtx, rtx, machine_mode, machine_mode); void expand_vec_floor (rtx, rtx, machine_mode, machine_mode); void expand_vec_nearbyint (rtx, rtx, machine_mode, machine_mode); +void expand_vec_rint (rtx, rtx, machine_mode, machine_mode); #endif bool sew64_scalar_helper (rtx *, rtx *, rtx, machine_mode, bool, void (*)(rtx *, rtx)); diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 5d3d458fa6c..445ed000f88 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3698,4 +3698,26 @@ expand_vec_nearbyint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); } +void +expand_vec_rint (rtx op_0, rtx op_1, machine_mode vec_fp_mode, + machine_mode vec_int_mode) +{ + /* Step-1: Get the abs float value for mask generation. */ + emit_vec_abs (op_0, op_1, vec_fp_mode); + + /* Step-2: Generate the mask on const fp. */ + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); + rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); + + /* Step-3: Convert to integer on mask, with dyn rounding (aka rint). */ + rtx tmp = gen_reg_rtx (vec_int_mode); + emit_vec_cvt_x_f (tmp, op_1, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-4: Convert to floating-point on mask for the rint result. */ + emit_vec_cvt_f_x (op_0, tmp, mask, UNARY_OP_TAMU_FRM_DYN, vec_fp_mode); + + /* Step-5: Retrieve the sign bit for -0.0. */ + emit_vec_copysign (op_0, op_0, op_1, vec_fp_mode); +} + } // namespace riscv_vector diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c new file mode 100644 index 00000000000..0d44b9844dd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-0.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test__Float16___builtin_rintf16: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e16,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (_Float16, __builtin_rintf16) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c new file mode 100644 index 00000000000..2ce122af677 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-1.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_rintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (float, __builtin_rintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c new file mode 100644 index 00000000000..e3b911b45c4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-2.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_double___builtin_rint: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e64,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +*/ +TEST_UNARY_CALL (double, __builtin_rint) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c new file mode 100644 index 00000000000..541c42c2ec7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-3.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math -fno-schedule-insns -fno-schedule-insns2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ + +#include "test-math.h" + +/* +** test_float___builtin_rintf: +** ... +** vsetvli\s+[atx][0-9]+,\s*zero,\s*e32,\s*m1,\s*ta,\s*mu +** vfabs\.v\s+v[0-9]+,\s*v[0-9]+ +** vmflt\.vf\s+v0,\s*v[0-9]+,\s*[fa]+[0-9]+ +** vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t +** vfsgnj\.vv\s+v[0-9]+,v[0-9]+,v[0-9]+ +** ... +** vmerge\.vvm\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0 +** ... +*/ +TEST_COND_UNARY_CALL (float, __builtin_rintf) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c new file mode 100644 index 00000000000..e96dae4b435 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-1.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +float in[ARRAY_SIZE]; +float out[ARRAY_SIZE]; +float ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (float, __builtin_rintf) +TEST_ASSERT (float) + +TEST_INIT (float, 1.2, 1.0, 1) +TEST_INIT (float, -1.2, -1.0, 2) +TEST_INIT (float, 3.0, 3.0, 3) +TEST_INIT (float, 8388607.5, 8388607.0, 4) +TEST_INIT (float, 8388609.0, 8388609.0, 5) +TEST_INIT (float, 0.0, 0.0, 6) +TEST_INIT (float, -0.0, -0.0, 7) +TEST_INIT (float, -8388607.5, -8388607.0, 8) +TEST_INIT (float, -8388608.0, -8388608.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RTZ); + + RUN_TEST (float, 1, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 2, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 3, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 4, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 5, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 6, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 7, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 8, __builtin_rintf, in, out, ref, ARRAY_SIZE); + RUN_TEST (float, 9, __builtin_rintf, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before == fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c new file mode 100644 index 00000000000..f0007d3f6d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-rint-run-2.c @@ -0,0 +1,48 @@ +/* { dg-do run { target { riscv_vector } } } */ +/* { dg-additional-options "-std=c99 -O3 -ftree-vectorize -fno-vect-cost-model -ffast-math" } */ + +#include "test-math.h" + +#define ARRAY_SIZE 128 + +double in[ARRAY_SIZE]; +double out[ARRAY_SIZE]; +double ref[ARRAY_SIZE]; + +TEST_UNARY_CALL (double, __builtin_rint) +TEST_ASSERT (double) + +TEST_INIT (double, 1.2, 1.0, 1) +TEST_INIT (double, -1.8, -2.0, 2) +TEST_INIT (double, 3.0, 3.0, 3) +TEST_INIT (double, 4503599627370495.5, 4503599627370496.0, 4) +TEST_INIT (double, 4503599627370497.0, 4503599627370497.0, 5) +TEST_INIT (double, 0.0, 0.0, 6) +TEST_INIT (double, -0.0, -0.0, 7) +TEST_INIT (double, -4503599627370495.5, -4503599627370496.0, 8) +TEST_INIT (double, -4503599627370496.0, -4503599627370496.0, 9) + +int +main () +{ + unsigned fflags_before = get_fflags (); + + set_rm (FRM_RNE); + + RUN_TEST (double, 1, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 2, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 3, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 4, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 5, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 6, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 7, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 8, __builtin_rint, in, out, ref, ARRAY_SIZE); + RUN_TEST (double, 9, __builtin_rint, in, out, ref, ARRAY_SIZE); + + unsigned fflags_after = get_fflags (); + + if (fflags_before == fflags_after) + __builtin_abort (); + + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c new file mode 100644 index 00000000000..cf10d61541a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/math-rint-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 --param=riscv-autovec-lmul=m8 -ffast-math -fdump-tree-optimized" } */ + +#include "def.h" + +DEF_OP_V (rintf16, 1, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 2, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 4, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 8, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 16, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 32, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 64, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 128, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 256, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 512, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 1024, _Float16, __builtin_rintf16) +DEF_OP_V (rintf16, 2048, _Float16, __builtin_rintf16) + +DEF_OP_V (rintf, 1, float, __builtin_rintf) +DEF_OP_V (rintf, 2, float, __builtin_rintf) +DEF_OP_V (rintf, 4, float, __builtin_rintf) +DEF_OP_V (rintf, 8, float, __builtin_rintf) +DEF_OP_V (rintf, 16, float, __builtin_rintf) +DEF_OP_V (rintf, 32, float, __builtin_rintf) +DEF_OP_V (rintf, 64, float, __builtin_rintf) +DEF_OP_V (rintf, 128, float, __builtin_rintf) +DEF_OP_V (rintf, 256, float, __builtin_rintf) +DEF_OP_V (rintf, 512, float, __builtin_rintf) +DEF_OP_V (rintf, 1024, float, __builtin_rintf) + +DEF_OP_V (rint, 1, double, __builtin_rint) +DEF_OP_V (rint, 2, double, __builtin_rint) +DEF_OP_V (rint, 4, double, __builtin_rint) +DEF_OP_V (rint, 8, double, __builtin_rint) +DEF_OP_V (rint, 16, double, __builtin_rint) +DEF_OP_V (rint, 32, double, __builtin_rint) +DEF_OP_V (rint, 64, double, __builtin_rint) +DEF_OP_V (rint, 128, double, __builtin_rint) +DEF_OP_V (rint, 256, double, __builtin_rint) +DEF_OP_V (rint, 512, double, __builtin_rint) + +/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-tree-dump-not "1,1" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2,2" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4,4" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "16,16" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "32,32" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "64,64" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "128,128" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "256,256" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "512,512" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "1024,1024" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "2048,2048" "optimized" } } */ +/* { dg-final { scan-tree-dump-not "4096,4096" "optimized" } } */ +/* { dg-final { scan-assembler-not {frflags\s+[atx][0-9]+} } } */ +/* { dg-final { scan-assembler-not {fsflags\s+[atx][0-9]+} } } */ +/* { dg-final { scan-assembler-times {vfcvt\.x\.f\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */ +/* { dg-final { scan-assembler-times {vfcvt\.f\.x\.v\s+v[0-9]+,\s*v[0-9]+,\s*v0\.t} 30 } } */