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[8.43.85.97]) by mx.google.com with ESMTPS id a6-20020a1709064a4600b009a0f9f9d779si10420957ejv.436.2023.09.25.20.13.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Sep 2023 20:13:30 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=L9X3sqFL; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2B2C1385C41F for ; Tue, 26 Sep 2023 03:13:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id C16973858D35 for ; Tue, 26 Sep 2023 03:13:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C16973858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695697981; x=1727233981; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=nteEWYz3GO9sBaG/KDDsL9UIboK271tDv9yapkmXE1I=; b=L9X3sqFLOminDlRrrdOI17JQAqDXxYa278FJjEO3vZIhjPnIZQELRCe/ MKb3Cc9Gana3jHqQgSS5FkrevRCRWeCDBuiRG2vIm+B5Qn5qbdxLC/U6X QuGrBAEAbvMBYunK7bktkaac9n4yPqFgs7vypXBpDO+deNOJJS8xbcLkT 2ZpN+D7Dn5ZNb522blUTwPyojMsTpSOO3yEWmueMfJy3UqgfR69IcmMWl R+vHy5JJFUeoGZp6673pNXFC9hBUwDJymAI1gOU7nKmgzQy6uKW8VlTgV QHE/vREaC1EUtSqFOsNMjNY+iIAqO+O5kp/gct84wN6K4hjXJ+po1aYKk w==; X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="445600960" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="445600960" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 25 Sep 2023 20:13:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10843"; a="777959245" X-IronPort-AV: E=Sophos;i="6.03,176,1694761200"; d="scan'208";a="777959245" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga008.jf.intel.com with ESMTP; 25 Sep 2023 20:12:58 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 98EA1100568E; Tue, 26 Sep 2023 11:12:57 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com Subject: [PATCH v1] RISC-V: Rename rounding const fp function for refactor Date: Tue, 26 Sep 2023 11:12:56 +0800 Message-Id: <20230926031256.2692187-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1778068236125561159 X-GMAIL-MSGID: 1778068236125561159 From: Pan Li The rounding related API shared one const, rename it to avoid unnecessary redundant code. gcc/ChangeLog: * config/riscv/riscv-v.cc (gen_ceil_const_fp): Remove. (get_fp_rounding_coefficient): Rename. (gen_floor_const_fp): Remove. (expand_vec_ceil): Take renamed func. (expand_vec_floor): Ditto. Signed-off-by: Pan Li Signed-off-by: Pan Li --- gcc/config/riscv/riscv-v.cc | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index a1ffefb23f3..9a1df950d58 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -3548,7 +3548,7 @@ cmp_lmul_gt_one (machine_mode mode) greater than and equal to 4503599627370496. */ static rtx -gen_ceil_const_fp (machine_mode inner_mode) +get_fp_rounding_coefficient (machine_mode inner_mode) { REAL_VALUE_TYPE real; @@ -3564,13 +3564,6 @@ gen_ceil_const_fp (machine_mode inner_mode) return const_double_from_real_value (real, inner_mode); } -static rtx -gen_floor_const_fp (machine_mode inner_mode) -{ - /* The floor needs the same floating point const as ceil. */ - return gen_ceil_const_fp (inner_mode); -} - static rtx emit_vec_float_cmp_mask (rtx fp_vector, rtx_code code, rtx fp_scalar, machine_mode vec_fp_mode) @@ -3637,7 +3630,7 @@ expand_vec_ceil (rtx op_0, rtx op_1, machine_mode vec_fp_mode, emit_vec_abs (op_0, op_1, vec_fp_mode); /* Step-2: Generate the mask on const fp. */ - rtx const_fp = gen_ceil_const_fp (GET_MODE_INNER (vec_fp_mode)); + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); /* Step-3: Convert to integer on mask, with rounding up (aka ceil). */ @@ -3662,7 +3655,7 @@ expand_vec_floor (rtx op_0, rtx op_1, machine_mode vec_fp_mode, emit_vec_abs (op_0, op_1, vec_fp_mode); /* Step-2: Generate the mask on const fp. */ - rtx const_fp = gen_floor_const_fp (GET_MODE_INNER (vec_fp_mode)); + rtx const_fp = get_fp_rounding_coefficient (GET_MODE_INNER (vec_fp_mode)); rtx mask = emit_vec_float_cmp_mask (op_0, LT, const_fp, vec_fp_mode); /* Step-3: Convert to integer on mask, with rounding down (aka floor). */