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[8.43.85.97]) by mx.google.com with ESMTPS id co6-20020a0564020c0600b00533a57ecba8si2729029edb.514.2023.09.23.22.50.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 23 Sep 2023 22:50:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=hLbGJSGQ; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 4C8063857B9B for ; Sun, 24 Sep 2023 05:50:51 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.43]) by sourceware.org (Postfix) with ESMTPS id 8F79C3858CDB for ; Sun, 24 Sep 2023 05:50:23 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 8F79C3858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1695534623; x=1727070623; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P1Q6xhK5A8RnlBA0orVXv6rezo1VAOZu/LltSRcan+4=; b=hLbGJSGQvdaYuntqdrjP0spD9h/kKFY6JKeZBuNE4+ald4ENb8Kib7cE IZo6rTSbq7+1h2ExBHjV8RYMUsr4acOAOtjGZ7mYKFX/MBmU+U5LUJEHO wAiugMfbok9c+JqKR8YRybeCpjMG2tdNHuP8uUWBrP18AB5Mycsd+2iIv e/Lf02yAxI+Gog/jyFsidgu+TIdbQ7Li02OW3D81vG60pVENM338nQ7hb gHI0DkvbzINDappYSW52SjNEOzrrYACZiuYoxJ0zGXTEXEUPjDrK+jjJZ 1i8TODchsjjV/U9Tt9+WF8DrT6ouUNdnB2FOh0icMw4kP6osKIyMgLSmX w==; X-IronPort-AV: E=McAfee;i="6600,9927,10842"; a="467361694" X-IronPort-AV: E=Sophos;i="6.03,171,1694761200"; d="scan'208";a="467361694" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2023 22:50:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10842"; a="741554953" X-IronPort-AV: E=Sophos;i="6.03,171,1694761200"; d="scan'208";a="741554953" Received: from shvmail02.sh.intel.com ([10.239.244.9]) by orsmga007.jf.intel.com with ESMTP; 23 Sep 2023 22:50:19 -0700 Received: from pli-ubuntu.sh.intel.com (pli-ubuntu.sh.intel.com [10.239.159.47]) by shvmail02.sh.intel.com (Postfix) with ESMTP id 3DE1010056EE; Sun, 24 Sep 2023 13:50:19 +0800 (CST) From: pan2.li@intel.com To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, pan2.li@intel.com, yanzhang.wang@intel.com, kito.cheng@gmail.com, patrick@rivosinc.com Subject: [PATCH v2] RISC-V: Fix fortran ICE/PR111546 when RV32 vec_init Date: Sun, 24 Sep 2023 13:50:17 +0800 Message-Id: <20230924055017.2386471-1-pan2.li@intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230924034528.1827780-1-pan2.li@intel.com> References: <20230924034528.1827780-1-pan2.li@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777889092436375511 X-GMAIL-MSGID: 1777896948876429068 From: Pan Li When broadcast the reperated element, we take the mask_int_mode by mistake. This patch would like to fix it by leveraging the machine mode of the element. The below test case in RV32 will be fixed. * gcc/testsuite/gfortran.dg/overload_5.f90 PR target/111546 gcc/ChangeLog: * config/riscv/riscv-v.cc (expand_vector_init_merge_repeating_sequence): Bugfix Signed-off-by: Pan Li Signed-off-by: Pan Li Signed-off-by: Pan Li > --- gcc/config/riscv/riscv-v.cc | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index c2466b1354f..a1ffefb23f3 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -2054,12 +2054,17 @@ static void expand_vector_init_merge_repeating_sequence (rtx target, const rvv_builder &builder) { - machine_mode dup_mode = get_repeating_sequence_dup_machine_mode (builder); - machine_mode mask_mode = get_mask_mode (builder.mode ()); + /* We can't use BIT mode (BI) directly to generate mask = 0b01010... + since we don't have such instruction in RVV. + Instead, we should use INT mode (QI/HI/SI/DI) with integer move + instruction to generate the mask data we want. */ + machine_mode mask_int_mode + = get_repeating_sequence_dup_machine_mode (builder); + machine_mode mask_bit_mode = get_mask_mode (builder.mode ()); uint64_t full_nelts = builder.full_nelts ().to_constant (); /* Step 1: Broadcast the first pattern. */ - rtx ops[] = {target, force_reg (GET_MODE_INNER (dup_mode), builder.elt (0))}; + rtx ops[] = {target, force_reg (builder.inner_mode (), builder.elt (0))}; emit_vlmax_insn (code_for_pred_broadcast (builder.mode ()), UNARY_OP, ops); /* Step 2: Merge the rest iteration of pattern. */ @@ -2067,8 +2072,8 @@ expand_vector_init_merge_repeating_sequence (rtx target, { /* Step 2-1: Generate mask register v0 for each merge. */ rtx merge_mask = builder.get_merge_scalar_mask (i); - rtx mask = gen_reg_rtx (mask_mode); - rtx dup = gen_reg_rtx (dup_mode); + rtx mask = gen_reg_rtx (mask_bit_mode); + rtx dup = gen_reg_rtx (mask_int_mode); if (full_nelts <= builder.inner_bits_size ()) /* vmv.s.x. */ { @@ -2078,14 +2083,15 @@ expand_vector_init_merge_repeating_sequence (rtx target, } else /* vmv.v.x. */ { - rtx ops[] = {dup, force_reg (GET_MODE_INNER (dup_mode), merge_mask)}; + rtx ops[] = {dup, + force_reg (GET_MODE_INNER (mask_int_mode), merge_mask)}; rtx vl = gen_int_mode (CEIL (full_nelts, builder.inner_bits_size ()), Pmode); - emit_nonvlmax_insn (code_for_pred_broadcast (dup_mode), UNARY_OP, + emit_nonvlmax_insn (code_for_pred_broadcast (mask_int_mode), UNARY_OP, ops, vl); } - emit_move_insn (mask, gen_lowpart (mask_mode, dup)); + emit_move_insn (mask, gen_lowpart (mask_bit_mode, dup)); /* Step 2-2: Merge pattern according to the mask. */ rtx ops[] = {target, target, builder.elt (i), mask};