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Fri, 4 Nov 2022 11:58:38 +0000 (GMT) From: Sriranjani P To: peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sriranjani P , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Pankaj Dubey , Jayati Sahu Subject: [PATCH 1/4] dt-bindings: net: Add EQoS compatible for FSD SoC Date: Fri, 4 Nov 2022 17:35:14 +0530 Message-Id: <20221104120517.77980-2-sriranjani.p@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTa1AbVRTHvdlkd8EJroDtJUCLy4gFBkg0hI3ycvpwfXRkqB8c7QCZsBOY JJtMNqmFaS1QgRLta6wtYuStNhFohYAIpSJQBArYao2ofVBCxqalD0kpVEsrIaDffufcc/7/ OefeiyOBvagIz2eNjIFVaEjUn9/RH/1sXNtjjFJcNx9M3XcfBZTlx/f5VM3AuIByDU5h1MBI I4+6XH9LQB24dhWhznUcEFCtToeA+rnLglJmx7SAql5sFlCDtWuoe2dnAFXffhejHt1oB9TA 6DWEKu0ZwKg/ZloE6UG03fobj3YdbMfob6suYXRtq4lutVWg9EXHKZRua9xD3z79C0ofsNsA /f1pCe1a6EFo+3ceQHta12UI31Yn5zGKXMYQwbBKXW4+q0ohX9uWvTE7USaWxEnkVBIZwSq0 TAq56fWMuC35mqUxyYgdCo1pKZWh4DgyITXZoDMZmYg8HWdMIRl9rkYv1cdzCi1nYlXxLGN8 QSIWP5e4VJijzhs9XyrQ/+63s9piA0WgETcDHIeEFM65Y8zAHw8kugEcvH4b8wWzAH7hcQNf cA/AQ71j2GrH300hvnwPgLX7exBfUMqDJc5y1Az8cJSIg6UOD897EEz8CuDVjyaWdRGiBIFn Pz++XBVEbIGjDgfPy3ziGVheP4l5WUikwC/HrAIvQ2I9/OpkL+K19iNSofV4qFcHEhM4/OYT N89Xswku2p18HwfB6z/YMR+LoPtg2QqrYNtA24qmBu4r2Yv4OA32XrDwvfoIEQ1PdCX40uHw 45GWZXmECID7/5lesRLCzupVjoINUxUrHAabp2ZX5Gl4q+0h6tvKYQDnzN3oIbCu6n+LWgBs IITRc1oVwyXqJSzz7n+3ptRpW8HyU455pRNcmrwT3wd4OOgDEEfIYOFsh1IZKMxVFBQyBl22 waRhuD6QuLS/w4joKaVu6S+wxmyJVC6WymQyqfx5mYRcK2yojFEGEiqFkVEzjJ4xrPbxcD9R ES+sLINuUv8ZXvdwYuSdraOdT3vSnvAPaID9WR8cGXeXvfWednvAhiaT0xoh6DoWNj/ELw6Z LNzlUEUG1FSORRsWRNasqigsvN4sz3gz9eXx+WBbTnpZVXFkV+fNMy8Zx8svYmm2oa8lat7a yDvu7U5ZaOax6a0vLhSqKtSPoipfdVrYIv+5AtK6O/3EyX0bMkXNGpffqSuxnL5bemX95qGG uoTJNcmDw83hNeVdtpGftjGoSfbG4mfy/uG9d+eP7k7MepDZEutRJ2XePH8kffPjFi5vWM3E aGZqL7v02r/uV13YGfqp3HXuQ/GunrBY+wPjmRs7iskn9WxSTkF7qqtyD8nn8hSSGMTAKf4F vHysC1MEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWy7bCSvG7hv5Rkg87HyhY/X05jtJhzvoXF Yv6Rc6wWT489Yrc4cmoJk8W9Re9YLfpePGS2uLCtj9Vi0+NrrBaXd81hs+i69oTVYt7ftawW xxaIWXw7/YbRYtHWL+wW/19vZbQ4cuYFs0Xr3iPsFrffrGN1EPbYsvImk8fT/q3sHjtn3WX3 WLCp1GPTqk42jzvX9rB5bF5S7/F+31U2j74tqxg9Du4z9Hj6Yy+zx5b9nxk9Pm+SC+CN4rJJ Sc3JLEst0rdL4Mo4c7GVteAWZ8W8OasYGxiXcHQxcnBICJhI/Foj2cXIxSEksJtRYveHv0xd jJxAcRmJkw+WMEPYwhIr/z1nhyhqZpJ4//gvO0iCTUBXovXaZyaQhIjAQ0aJ8587WUEcZoEu ZolXXTvA2oUF3CTOXLsGNpZFQFWifdEDsG5eAVuJ5WdXskKskJdYveEAM8hJnAJ2EitXSIOY QkAlc+drTGDkW8DIsIpRMrWgODc9t9iwwDAvtVyvODG3uDQvXS85P3cTIzhqtDR3MG5f9UHv ECMTB+MhRgkOZiUR3k/bkpOFeFMSK6tSi/Lji0pzUosPMUpzsCiJ817oOhkvJJCeWJKanZpa kFoEk2Xi4JRqYDpx2WSbk8rEt7nHmls8FSqmbGuOOhChuHj3lbWWVexxFhF1Esuub+z7vnv7 dY8Gi2/f1QrnJL4w/DV/3bmUBcr1Mx6+C2KLLVgziUVjmuCU3CW7NZe/ee5hdck0LXfflUIV +QAls+LlHqWczgsLKrY5KpmIaaW/0PH5dvhjnUHAmyP8LLF19y3+9vK6zZf45HbEP+Be9LKn 7zkk/qus+/hOge/wu/VnH+s2ncllFcpmmxXhf/Sm0LyUiH1yftpJRoasi/s3TD/rdjw+ejsD 9ynJ3UmhmnbZO/QZHjAEZnCL6hj+3WirEK+tlx1esET44wu5BZ1yxQFL8267t7zTSZN8eDVM 6OIhtaqjxw8dUWIpzkg01GIuKk4EAHqrtnoJAwAA X-CMS-MailID: 20221104115841epcas5p490b99811e257b8f3f965748df0a57be5 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221104115841epcas5p490b99811e257b8f3f965748df0a57be5 References: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748567947115813969?= X-GMAIL-MSGID: =?utf-8?q?1748567947115813969?= Add FSD Ethernet compatible in dt-bindings document Cc: "David S. Miller" Cc: Eric Dumazet Cc: Jakub Kicinski Cc: Paolo Abeni Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Alexandre Torgue Cc: Giuseppe Cavallaro Cc: Jose Abreu Cc: devicetree@vger.kernel.org Signed-off-by: Pankaj Dubey Signed-off-by: Jayati Sahu Signed-off-by: Sriranjani P --- Documentation/devicetree/bindings/net/snps,dwmac.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index e88a86623fce..2b0b9e5f3fa1 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -89,6 +89,7 @@ properties: - snps,dwmac-5.10a - snps,dwxgmac - snps,dwxgmac-2.10 + - tesla,dwc-qos-ethernet-4.21 reg: minItems: 1 From patchwork Fri Nov 4 12:05:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriranjani P X-Patchwork-Id: 15492 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp363264wru; Fri, 4 Nov 2022 05:19:02 -0700 (PDT) X-Google-Smtp-Source: AMsMyM7EiHxQ37/Q4eK2YhdqBTWwwf5znXdCjwAPyCcb6gfPboV4Ff7vXee3gxJOCxhnrprPpHho X-Received: by 2002:a17:907:7b8b:b0:7ad:e144:19e1 with SMTP id ne11-20020a1709077b8b00b007ade14419e1mr23214100ejc.154.1667564341807; Fri, 04 Nov 2022 05:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1667564341; cv=none; d=google.com; s=arc-20160816; b=H8QaXuh0bmCCKrGBWkL0P8XWf9vIfKyAKeCPA5DyRSIht0DueYZKmU54wDaMCSH0YB LXsicZPFuYx/AdCm4cmKn9qDmD6GwlPQQegcg4U/n8toaVupfQkTHJjm7E1OWD+uWlgk RC9pVrac4RdGxgfNZ0ERx9RTtJRhJrd1btN2Au8TUkiBaYqrctcAmZhL+dyWGx1ho9v/ cmXRcsffK7TTmdiaJ3JzmACOuaJiTilbeivECewJQCualOC+Fc/SowRGuhxhvMDbICLM NEhNEqgMUsnP6C4vGCzZBOl9ceR3s1tKWFGxrOChemoImizHmpj9yomhvPJHG/wB+DWE oVig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:dlp-filter:cms-type:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature:dkim-filter; bh=gWvumClwLh3eNt5+I81qtQmvmemuNRTWHvi94SK/Qr8=; b=qm4mO5f9yrlvWBDMd4A5g27U1bPmkP7sztdHa0u6yRml4vA6RRWwiBPdW0wFKgWHV9 bosiyby5NIRrUc/8BlCN8J5ZHuDxoC3wYUmK4gdXJmrXuTX8xxN6mwKrDAGs/QZWE21g yAUTS7myf27dbmU+VlLkv279iF13Oftj587tPTON9DFXqoFhRWSTvg9UFPzCBc0lUo8b T+o77FjRbUwHfr6JkURV1GBTY8atkH/JzwFaA2ECq8/nRBG2YjY1kc7wW1PUzRVdHJSK N5hcNl0utQreZSahONylEw+GcLOEbyhh+3Ac018UpYZRH+qxGdkXyS74wRLjhsb001iS h3ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@samsung.com header.s=mail20170921 header.b=NPr9jBkE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=samsung.com Received: from out1.vger.email (out1.vger.email. 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Fri, 4 Nov 2022 11:58:52 +0000 (GMT) From: Sriranjani P To: peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sriranjani P , Chandrasekar R , Suresh Siddha Subject: [PATCH 2/4] net: stmmac: dwc-qos: Add FSD EQoS support Date: Fri, 4 Nov 2022 17:35:15 +0530 Message-Id: <20221104120517.77980-3-sriranjani.p@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrIJsWRmVeSWpSXmKPExsWy7bCmhu4+htRkg9MbZSx+vpzGaDHnfAuL xdNjj9gt7i16x2pxYVsfq8Wmx9dYLS7vmsNm0XXtCavFvL9rWS2OLRCz+Hb6DaPF/9dbGS1m XdjBanHkzAtmi9tv1rFaLHqwgNVBwGPLyptMHk/7t7J77Jx1l91jwaZSj02rOtk8Ni+p93i/ 7yqbR9+WVYweB/cZejz9sZfZY8v+z4we/5rmsnt83iQXwBuVbZORmpiSWqSQmpecn5KZl26r 5B0c7xxvamZgqGtoaWGupJCXmJtqq+TiE6DrlpkD9JeSQlliTilQKCCxuFhJ386mKL+0JFUh I7+4xFYptSAlp8CkQK84Mbe4NC9dLy+1xMrQwMDIFKgwITtj1rNmloL24IqWP2uZGhh/uXQx cnJICJhIfPnxgK2LkYtDSGA3o8TZc4/ZIZxPjBKbLuxmBqkSEvjMKHHpAxdcx4J5zBBFuxgl 7v+ZC9XRyiSxcNYBNpAqNgFdidZrn5lAEiIC1xklHk6+AVbFLNDAJPH+zkR2kCphAXuJW8uW g3WwCKhKHH96C2wfr4CtxP+trawQ++QlVm84ABTn4OAUsJNYuUIaZI6EwBEOibvPNrBD1LhI fJu+nhnCFpZ4dXwLVFxK4vO7vWwQdrrE5iOboWbmSHQ0NUPV20scuDKHBWQ+s4CmxPpd+hBh WYmpp9YxgdjMAnwSvb+fMEHEeSV2zIOx1SQWP+qEsmUk1j76BDXeQ+L50q2skKCbyCixaAvf BEa5WQgbFjAyrmKUTC0ozk1PLTYtMMpLLYfHWnJ+7iZGcNrV8trB+PDBB71DjEwcjIcYJTiY lUR4P21LThbiTUmsrEotyo8vKs1JLT7EaAoMvonMUqLJ+cDEn1cSb2hiaWBiZmZmYmlsZqgk zrt4hlaykEB6YklqdmpqQWoRTB8TB6dUA1Pdei7htbsinj9edE1dMEDcMeTu4w6mNbXFPbqG UpdPHX3HNFspdOe8J/oPGLpdT2ZEqu8rN1teFsZfPHnRVos9S9h3bz7tEXf5c/3duKTVrdre /w5obd+15Mw6htNRM1j9f/xuWdo0U9ysOuYGj8QC2bfWOVIhcfMWrn3E+eqRXvvkLJXLGj/O STgGaQe/Vqhc0LDhVvie2zcFloQ+5Ji06uI0/qQUhe2Jvz1/hE1QqJ96adNF4R36pUsXTDpy 4ue1CbFiOcseyfinfNBbYzwrilFY4VbXZNYtKzdtqk4Jt33Km1dqzyOY82uy/k/3fctS6lvc hGZ8F1lbtmeW8+u3HHqZhmsvLL6XaMm0pfqSEktxRqKhFnNRcSIADltmWUQEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrBLMWRmVeSWpSXmKPExsWy7bCSvG7dv5Rkg57ZChY/X05jtJhzvoXF 4umxR+wW9xa9Y7W4sK2P1WLT42usFpd3zWGz6Lr2hNVi3t+1rBbHFohZfDv9htHi/+utjBaz LuxgtThy5gWzxe0361gtFj1YwOog4LFl5U0mj6f9W9k9ds66y+6xYFOpx6ZVnWwem5fUe7zf d5XNo2/LKkaPg/sMPZ7+2MvssWX/Z0aPf01z2T0+b5IL4I3isklJzcksSy3St0vgypj1rJml oD24ouXPWqYGxl8uXYycHBICJhJfFsxj7mLk4hAS2MEo0T9pPwtEQkbi5IMlzBC2sMTKf8/Z IYqamSQuX5wLlmAT0JVovfaZCSQhIvCQUeL8505WEIdZoI1JYtGVe+wgVcIC9hK3li1nA7FZ BFQljj+9BdbNK2Ar8X9rKyvECnmJ1RsOAMU5ODgF7CRWrpAGMYWASubO15jAyLeAkWEVo2Rq QXFuem6xYYFRXmq5XnFibnFpXrpecn7uJkZwZGhp7WDcs+qD3iFGJg7GQ4wSHMxKIryftiUn C/GmJFZWpRblxxeV5qQWH2KU5mBREue90HUyXkggPbEkNTs1tSC1CCbLxMEp1cBkoia4MMhL 0WThi7iZzE0JPrut2N6E/WZ6oy7gs+mhcBLnuuo43ux0xw9sAcf7hLYVPrn/4qXXov8cfp25 Ah+T5bZkO8VzbS2Vrpo0+ZjSCZsw8V0eB8oDtzfvyFNOm1/9Wqs5lfsD5zZlw8b4H8ad77VP KMVMNp7Z981h4pVbDbvepD1ae//6jvtMJo9qXm9/7Hno8xZDI/6FAv0hJo715x7GXhCvmmhm Fte9z8mNRyqT47laxcFyqXUrOva+O6i9sfXulQUOXsxPjhfXZH77frIv4t/c97ZyPKv3sTBo d73XtXV5zzr9vVaNfmTxUd1vby962Ae23fzf67Jz36+0RdEdj3rMYi7t+x8UdEGJpTgj0VCL uag4EQCD4ubq+wIAAA== X-CMS-MailID: 20221104115854epcas5p4ca280f9c4cc4d1fa564d80016e9f0061 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221104115854epcas5p4ca280f9c4cc4d1fa564d80016e9f0061 References: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748567932361995476?= X-GMAIL-MSGID: =?utf-8?q?1748567947367342846?= The FSD SoC contains two instance of the Synopsys DWC ethernet QOS IP core. The binding that it uses is slightly different from existing ones because of the integration (clocks, resets). For FSD SoC, a mux switch is needed between internal and external clocks. By default after reset internal clock is used but for receiving packets properly, external clock is needed. Mux switch to external clock happens only when the external clock is present. Signed-off-by: Chandrasekar R Signed-off-by: Suresh Siddha Signed-off-by: Sriranjani P --- .../stmicro/stmmac/dwmac-dwc-qos-eth.c | 229 ++++++++++++++++++ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 12 + include/linux/stmmac.h | 1 + 3 files changed, 242 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c index 80efdeeb0b59..0a60fe3e1909 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-dwc-qos-eth.c @@ -20,6 +20,7 @@ #include #include #include +#include #include "stmmac_platform.h" #include "dwmac4.h" @@ -37,6 +38,44 @@ struct tegra_eqos { struct gpio_desc *reset; }; +enum fsd_rxmux_clk { + FSD_RXCLK_MUX = 7, + FSD_RXCLK_EXTERNAL, + FSD_RXCLK_INTERNAL +}; + +struct fsd_eqos_plat_data { + const struct fsd_eqos_variant *fsd_eqos_instance_variant; + struct clk_bulk_data *clks; + struct device *dev; + int instance_num; +}; + +struct fsd_eqos_variant { + const char * const *clk_list; + int num_clks; +}; + +static const char * const fsd_eqos_instance_0_clk[] = { + "ptp_ref", "master_bus", "slave_bus", "tx", "rx" +}; + +static const char * const fsd_eqos_instance_1_clk[] = { + "ptp_ref", "master_bus", "slave_bus", "tx", "rx", "master2_bus", + "slave2_bus", "eqos_rxclk_mux", "eqos_phyrxclk", "dout_peric_rgmii_clk" +}; + +static const struct fsd_eqos_variant fsd_eqos_clk_info[] = { + { + .clk_list = fsd_eqos_instance_0_clk, + .num_clks = ARRAY_SIZE(fsd_eqos_instance_0_clk) + }, + { + .clk_list = fsd_eqos_instance_1_clk, + .num_clks = ARRAY_SIZE(fsd_eqos_instance_1_clk) + }, +}; + static int dwc_eth_dwmac_config_dt(struct platform_device *pdev, struct plat_stmmacenet_data *plat_dat) { @@ -267,6 +306,190 @@ static int tegra_eqos_init(struct platform_device *pdev, void *priv) return 0; } +static int dwc_eqos_rxmux_setup(void *priv, bool external) +{ + struct fsd_eqos_plat_data *plat = priv; + + /* doesn't support RX clock mux */ + if (!plat->clks[FSD_RXCLK_MUX].clk) + return 0; + + if (external) + return clk_set_parent(plat->clks[FSD_RXCLK_MUX].clk, + plat->clks[FSD_RXCLK_EXTERNAL].clk); + else + return clk_set_parent(plat->clks[FSD_RXCLK_MUX].clk, + plat->clks[FSD_RXCLK_INTERNAL].clk); +} + +static int dwc_eqos_setup_rxclock(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + if (np && of_property_read_bool(np, "rx-clock-mux")) { + unsigned int reg, val; + struct regmap *syscon = syscon_regmap_lookup_by_phandle(np, + "rx-clock-mux"); + + if (IS_ERR(syscon)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-mux syscon!\n"); + return PTR_ERR(syscon); + } + + if (of_property_read_u32_index(np, "rx-clock-mux", 1, ®)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-mux reg. offset!\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "rx-clock-mux", 2, &val)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-mux reg. val!\n"); + return -EINVAL; + } + + regmap_write(syscon, reg, val); + } + + if (np && of_property_read_bool(np, "rx-clock-skew")) { + unsigned int reg, val; + struct regmap *syscon = syscon_regmap_lookup_by_phandle(np, + "rx-clock-skew"); + + if (IS_ERR(syscon)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-skew syscon!\n"); + return PTR_ERR(syscon); + } + + if (of_property_read_u32_index(np, "rx-clock-skew", 1, ®)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-skew reg. offset!\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "rx-clock-skew", 2, &val)) { + dev_err(&pdev->dev, "couldn't get the rx-clock-skew reg. val!\n"); + return -EINVAL; + } + + regmap_write(syscon, reg, val); + } + + if (np && of_property_read_bool(np, "tx-clock-mux")) { + unsigned int reg, val; + struct regmap *syscon = syscon_regmap_lookup_by_phandle(np, + "tx-clock-mux"); + + if (IS_ERR(syscon)) { + dev_err(&pdev->dev, "couldn't get the tx-clock-mux syscon!\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "tx-clock-mux", 1, ®)) { + dev_err(&pdev->dev, "couldn't get the tx-clock-mux reg. offset!\n"); + return -EINVAL; + } + + if (of_property_read_u32_index(np, "tx-clock-mux", 2, &val)) { + dev_err(&pdev->dev, "couldn't get the tx-clock-mux reg. val!\n"); + return -EINVAL; + } + + regmap_write(syscon, reg, val); + } + + return 0; +} + +static int fsd_eqos_clk_init(struct fsd_eqos_plat_data *plat, + struct plat_stmmacenet_data *data) +{ + int ret, i; + + const struct fsd_eqos_variant *fsd_eqos_variant_data = plat->fsd_eqos_instance_variant; + + plat->clks = devm_kcalloc(plat->dev, fsd_eqos_variant_data->num_clks, + sizeof(*plat->clks), GFP_KERNEL); + if (!plat->clks) + return -ENOMEM; + + for (i = 0; i < fsd_eqos_variant_data->num_clks; i++) + plat->clks[i].id = fsd_eqos_variant_data->clk_list[i]; + + ret = devm_clk_bulk_get(plat->dev, fsd_eqos_variant_data->num_clks, plat->clks); + if (ret) + return ret; + + return 0; +} + +static int fsd_clks_endisable(void *priv, bool enabled) +{ + struct fsd_eqos_plat_data *plat = priv; + int ret; + + const struct fsd_eqos_variant *fsd_eqos_variant_data = plat->fsd_eqos_instance_variant; + + if (enabled) { + ret = clk_bulk_prepare_enable(fsd_eqos_variant_data->num_clks, plat->clks); + if (ret) { + dev_err(plat->dev, "failed to enable clks, err = %d\n", ret); + return ret; + } + } else { + clk_bulk_disable_unprepare(fsd_eqos_variant_data->num_clks, plat->clks); + } + + return 0; +} + +static int fsd_eqos_probe(struct platform_device *pdev, + struct plat_stmmacenet_data *data, + struct stmmac_resources *res) +{ + struct fsd_eqos_plat_data *priv_plat; + struct device_node *np = pdev->dev.of_node; + int ret; + + priv_plat = devm_kzalloc(&pdev->dev, sizeof(*priv_plat), GFP_KERNEL); + if (!priv_plat) { + ret = -ENOMEM; + goto error; + } + + priv_plat->dev = &pdev->dev; + data->bus_id = of_alias_get_id(np, "eth"); + priv_plat->instance_num = data->bus_id; + + priv_plat->fsd_eqos_instance_variant = &fsd_eqos_clk_info[data->bus_id]; + + ret = fsd_eqos_clk_init(priv_plat, data); + + data->bsp_priv = priv_plat; + data->clks_config = fsd_clks_endisable; + data->rxmux_setup = dwc_eqos_rxmux_setup; + + ret = fsd_clks_endisable(priv_plat, true); + if (ret) + goto error; + + ret = dwc_eqos_setup_rxclock(pdev); + if (ret) + dev_err_probe(&pdev->dev, ret, "ERROR:Unable to setup rxclock\n"); +out: + return 0; + +error: + priv_plat = ERR_PTR(ret); + goto out; +} + +static int fsd_eqos_remove(struct platform_device *pdev) +{ + struct fsd_eqos_plat_data *priv_plat = get_stmmac_bsp_priv(&pdev->dev); + + fsd_clks_endisable(priv_plat, false); + + return 0; +} + static int tegra_eqos_probe(struct platform_device *pdev, struct plat_stmmacenet_data *data, struct stmmac_resources *res) @@ -415,6 +638,11 @@ static const struct dwc_eth_dwmac_data tegra_eqos_data = { .remove = tegra_eqos_remove, }; +static const struct dwc_eth_dwmac_data fsd_eqos_data = { + .probe = fsd_eqos_probe, + .remove = fsd_eqos_remove, +}; + static int dwc_eth_dwmac_probe(struct platform_device *pdev) { const struct dwc_eth_dwmac_data *data; @@ -493,6 +721,7 @@ static int dwc_eth_dwmac_remove(struct platform_device *pdev) static const struct of_device_id dwc_eth_dwmac_match[] = { { .compatible = "snps,dwc-qos-ethernet-4.10", .data = &dwc_qos_data }, { .compatible = "nvidia,tegra186-eqos", .data = &tegra_eqos_data }, + { .compatible = "tesla,dwc-qos-ethernet-4.21", .data = &fsd_eqos_data }, { } }; MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match); diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 8273e6a175c8..7be95a876c32 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -3831,6 +3831,9 @@ static int __stmmac_open(struct net_device *dev, netif_tx_start_all_queues(priv->dev); stmmac_enable_all_dma_irq(priv); + if (priv->plat->rxmux_setup) + priv->plat->rxmux_setup(priv->plat->bsp_priv, true); + return 0; irq_error: @@ -3884,6 +3887,9 @@ static int stmmac_release(struct net_device *dev) struct stmmac_priv *priv = netdev_priv(dev); u32 chan; + if (priv->plat->rxmux_setup) + priv->plat->rxmux_setup(priv->plat->bsp_priv, false); + if (device_may_wakeup(priv->device)) phylink_speed_down(priv->phylink, false); /* Stop and disconnect the PHY */ @@ -7383,6 +7389,9 @@ int stmmac_suspend(struct device *dev) if (!ndev || !netif_running(ndev)) return 0; + if (priv->plat->rxmux_setup) + priv->plat->rxmux_setup(priv->plat->bsp_priv, false); + mutex_lock(&priv->lock); netif_device_detach(ndev); @@ -7546,6 +7555,9 @@ int stmmac_resume(struct device *dev) mutex_unlock(&priv->lock); rtnl_unlock(); + if (priv->plat->rxmux_setup) + priv->plat->rxmux_setup(priv->plat->bsp_priv, true); + netif_device_attach(ndev); return 0; diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h index fb2e88614f5d..8867646917e0 100644 --- a/include/linux/stmmac.h +++ b/include/linux/stmmac.h @@ -229,6 +229,7 @@ struct plat_stmmacenet_data { void (*ptp_clk_freq_config)(void *priv); int (*init)(struct platform_device *pdev, void *priv); void (*exit)(struct platform_device *pdev, void *priv); + int (*rxmux_setup)(void *priv, bool external); struct mac_device_info *(*setup)(void *priv); int (*clks_config)(void *priv, bool enabled); int (*crosststamp)(ktime_t *device, struct system_counterval_t *system, From patchwork Fri Nov 4 12:05:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriranjani P X-Patchwork-Id: 15490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp363234wru; 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Fri, 4 Nov 2022 11:58:59 +0000 (GMT) From: Sriranjani P To: peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sriranjani P , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Pankaj Dubey , Jayati Sahu Subject: [PATCH 3/4] arm64: dts: fsd: Add Ethernet support for FSYS0 Block of FSD SoC Date: Fri, 4 Nov 2022 17:35:16 +0530 Message-Id: <20221104120517.77980-4-sriranjani.p@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VTe0xTVxze6e1tL5iauyLuwJiwO2STBWwHlAOCI86Yiy4ZzmwuJEvXtXeF tLRNH9vckmnkJVVh6OaMI6yrHaMYHistE2cFKdNI1UnE4gvWVhgIDLBMMjMIo1zc/vu+7/f9 zu9xziEwYRcvlijWGBm9RqameJHcDs+mV1IuP8PIRYcGMtGThycAqvutjIu+672Oo9FLQT7q 7bNx0LB1GkfV4wEM3eioxpHjgQ9HN8/V8ZDZN4Kj+sVmHF2yrEfz3imArK6/+Ghp0gVQ79Vx DJW7e/no3lQLnhdFO+13OPRojYtPd54a4tMWh4l2NFXx6Pu+8zy63bafnrlwi0dXO5sAffGC mB79243Rzq45QM85NhQIClU5RYxMwegTGI1cqyjWKHOpXXukb0gzJCJxijgLZVIJGlkJk0tt f7MgZUexenlMKuFjmdq0LBXIDAZq89YcvdZkZBKKtAZjLsXoFGpdui7VICsxmDTKVA1jzBaL RK9lLBs/UBVVfGvl6gaSPr0yWY0dAN54MyAISKbD8zOxZhBJCMlfAOwr+xNnSQjAh1NeLkvm Aby5WIeZQcRKxsSD0tWAG8DuYzbAknIONNvH8bCLR6bAct8cJxxYRw4CGDh+mx8mGHkQg94f GnlhVxS5FzYcCRchCC65Edbejw/LAjIX9t8a4rLl4uGZtm4sbIkgt0J74/PhYyB5m4CzE7ZV z3a4uGTHWRwFJy47+SyOhXPTbh6LlbC9t33Vo4aHDpaujvM67B6oW2kBIzfB1nObWfkF+HVf CyeMMXItPPrPCIfVBfBs/VOcBE8Hq1ZxHGwOhnB2pzT0D6exO6kFsK6+FfsSbDj1fwULAE0g htEZSpSMIUMn1jCf/Hdpcm2JA6y85OT8s2DIP5vaAzgE6AGQwKh1glCHXC4UKGT7PmP0Wqne pGYMPSBjeXu1WGy0XLv8FTRGqTg9S5QukUjSs9IkYuo5wemTyXIhqZQZGRXD6Bj90zwOERF7 gNPSkv+sSv0N5Wr7w1RpiahaEObMj3i4V+qPe0JTc7usLzt/jldH9/lj7DZiTZfP/O7k6KOd 0oW+1jVHMHVSIDE4uBRQyhP9ghP2awNpjd+3q2Z/rUGOsruWfljj+eJkw5DFr/68IyRVcts6 sxscuoqm6Rh+8PravHs7aeHo4Y9mCnf74kQ/ZTV5pyoiegbdPwoqQ7a0LZ7ETGlQOSYZ8/Cz 6ILO9x/R6+VF/e858756aziRQ2x57K3q6Wwe046NIK52PqBTWPcfzt6xe5vC/WRb2TsXrx1d 2BtZWbZnccGV+rb4asnju4V35kvzWxnXh9HYq2demvk97sbwix0b91FcQ5FMnIzpDbJ/ATdI sZ9SBAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWy7bCSvG7bv5Rkg78bZS1+vpzGaDHnfAuL xfwj51gtnh57xG5x5NQSJot7i96xWvS9eMhscWFbH6vFpsfXWC0u75rDZtF17Qmrxby/a1kt ji0Qs/h2+g2jxaKtX9gt/r/eymhx5MwLZovWvUfYLW6/WcfqIOyxZeVNJo+n/VvZPXbOusvu sWBTqcemVZ1sHneu7WHz2Lyk3uP9vqtsHn1bVjF6HNxn6PH0x15mjy37PzN6fN4kF8AbxWWT kpqTWZZapG+XwJXRNnsRS8EVtYqTr/uYGxhPy3cxcnJICJhIvHrczNLFyMUhJLCbUeL2jH5W iISMxMkHS5ghbGGJlf+es0MUNTNJ9E0+yQiSYBPQlWi99pkJJCEi8JBR4vznTlYQh1mgi1ni VdcOsHZhgVCJnq+/2boYOThYBFQlJt4BW80rYCtx8epdFogN8hKrNxxgBinhFLCTWLlCGsQU AiqZO19jAiPfAkaGVYySqQXFuem5xYYFhnmp5XrFibnFpXnpesn5uZsYwVGjpbmDcfuqD3qH GJk4GA8xSnAwK4nwftqWnCzEm5JYWZValB9fVJqTWnyIUZqDRUmc90LXyXghgfTEktTs1NSC 1CKYLBMHp1QDk+Xqy0dFljwNkTRUkNNJrgy6bd170MMqYPnX326xm4yc+Iuf7O/Z+sHs6bOn SVuP3j6VsPldkHzZ0o/B87J+TpE8c11r2XdfKdeO5xdqtB7tPSb98rLh45MWnheqVXhK9pRn Mq/c9WWtwLIYzw83M4xi5sRdDN/myJ1n98aI4fnsNeE/TiXzTBbYuKqUZ0UUn654wa5PJzNt cme96NztqPTsf5b1jdBim5t5dzqkJ21U3VJ7oe0U30dHhneG6dNv6tSlKTIyW4QkOKfuk/z/ wnad+Y+S1Vcaj2cE/phzQNCqbnPWxZbSM+zbE2LZ3impq9seyCzZ0mOkKvD2ShCb3w/JNYdY VX3XssfIqd/PVmIpzkg01GIuKk4EAO9c1vQJAwAA X-CMS-MailID: 20221104115902epcas5p209442971ba9f4cb001a933bda3c50b25 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221104115902epcas5p209442971ba9f4cb001a933bda3c50b25 References: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748567943288691467?= X-GMAIL-MSGID: =?utf-8?q?1748567943288691467?= The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in FSYS0 block and other in PERIC block. Adds device tree node for Ethernet in FSYS0 Block and enables the same for FSD platform. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Richard Cochran Cc: devicetree@vger.kernel.org Signed-off-by: Pankaj Dubey Signed-off-by: Jayati Sahu Signed-off-by: Sriranjani P --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 ++++++++++++++++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 38 +++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 1db6ddf03f01..42bf25c680e2 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -30,6 +30,15 @@ }; }; +ðernet_0 { + status = "okay"; + + fixed-link { + speed=<1000>; + full-duplex; + }; +}; + &fin_pll { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index d0abb9aa0e9e..8c7e43085a2b 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -64,6 +64,62 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + eth0_tx_clk: eth0-tx-clk-pins { + samsung,pins = "gpf0-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_tx_data: eth0-tx-data-pins { + samsung,pins = "gpf0-1", "gpf0-2", "gpf0-3", "gpf0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_tx_ctrl: eth0-tx-ctrl-pins { + samsung,pins = "gpf0-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_phy_intr: eth0-phy-intr-pins { + samsung,pins = "gpf0-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_rx_clk: eth0-rx-clk-pins { + samsung,pins = "gpf1-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_rx_data: eth0-rx-data-pins { + samsung,pins = "gpf1-1", "gpf1-2", "gpf1-3", "gpf1-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_rx_ctrl: eth0-rx-ctrl-pins { + samsung,pins = "gpf1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth0_mdio: eth0-mdio-pins { + samsung,pins = "gpf1-6", "gpf1-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_peric { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..2495928b71dc 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -32,6 +32,7 @@ spi0 = &spi_0; spi1 = &spi_1; spi2 = &spi_2; + eth0 = ðernet_0; }; cpus { @@ -860,6 +861,43 @@ clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>; clock-names = "ref_clk"; }; + + ethernet_0: ethernet@15300000 { + compatible = "tesla,dwc-qos-ethernet-4.21"; + reg = <0x0 0x15300000 0x0 0x10000>; + interrupts = ; + clocks = + /* ptp ref clock */ + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_PTP_REF_I>, + /* aclk clocks */ + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_ACLK_I>, + /* hclk clocks */ + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_HCLK_I>, + /* rgmii clocks */ + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_RGMII_CLK_I>, + /* rxi clocks */ + <&clock_fsys0 FSYS0_EQOS_TOP0_IPCLKPORT_CLK_RX_I>; + clock-names = + /* ptp ref clocks */ + "ptp_ref", + /* aclk clocks */ + "master_bus", + /* hclk clocks */ + "slave_bus", + /* rgmii clk */ + "tx", + /* rxi clocks */ + "rx"; + pinctrl-names = "default"; + pinctrl-0 = <ð0_tx_clk>, <ð0_tx_data>, <ð0_tx_ctrl>, + <ð0_phy_intr>, <ð0_rx_clk>, <ð0_rx_data>, + <ð0_rx_ctrl>, <ð0_mdio>; + local-mac-address = [45 54 48 30 4d 43]; + rx-clock-skew = <&sysreg_fsys0 0x0 0x2>; + iommus = <&smmu_fsys0 0x0 0x1>; + status = "disabled"; + phy-mode = "rgmii"; + }; }; }; From patchwork Fri Nov 4 12:05:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sriranjani P X-Patchwork-Id: 15493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp363915wru; Fri, 4 Nov 2022 05:20:20 -0700 (PDT) X-Google-Smtp-Source: AMsMyM5sb956nsBmSAwRhvQvWqfNLJWlraaZxsAfI9mYn94rVQoPGd7JrqiIQP3o1eAEkJ2tK/ui X-Received: by 2002:a17:902:ef85:b0:187:85d:bd2e with SMTP id iz5-20020a170902ef8500b00187085dbd2emr32812822plb.31.1667564420134; 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Fri, 4 Nov 2022 11:59:06 +0000 (GMT) From: Sriranjani P To: peppe.cavallaro@st.com, alexandre.torgue@foss.st.com, joabreu@synopsys.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, mcoquelin.stm32@gmail.com, richardcochran@gmail.com Cc: netdev@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Sriranjani P , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, Pankaj Dubey , Jayati Sahu Subject: [PATCH 4/4] arm64: dts: fsd: Add Ethernet support for PERIC Block of FSD SoC Date: Fri, 4 Nov 2022 17:35:17 +0530 Message-Id: <20221104120517.77980-5-sriranjani.p@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrEJsWRmVeSWpSXmKPExsWy7bCmpu5DhtRkg6eLZCx+vpzGaDHnfAuL xfwj51gtnh57xG5x5NQSJot7i96xWvS9eMhscWFbH6vFpsfXWC0u75rDZtF17Qmrxby/a1kt ji0Qs/h2+g2jxaKtX9gt/r/eymhx5MwLZovWvUfYLW6/WcfqIOyxZeVNJo+n/VvZPXbOusvu sWBTqcemVZ1sHneu7WHz2Lyk3uP9vqtsHn1bVjF6HNxn6PH0x15mjy37PzN6fN4kF8AblW2T kZqYklqkkJqXnJ+SmZduq+QdHO8cb2pmYKhraGlhrqSQl5ibaqvk4hOg65aZA/SmkkJZYk4p UCggsbhYSd/Opii/tCRVISO/uMRWKbUgJafApECvODG3uDQvXS8vtcTK0MDAyBSoMCE74+Wv fawF97UrZl2ZzNzAuFa5i5GTQ0LARGLpm2NMXYxcHEICuxkl2u9MZ4dwPjFKPOw7xgzhfGaU WHLmCgtMy6QPPVCJXYwSl9q7WCCcViaJ/RNWglWxCehKtF77DDZYROA60KzJN8AGMws0MUuc XrqCDaRKWCBc4vXX+UwgNouAqsT29X/ZQWxeAVuJBz/fskPsk5dYveEA0D4ODk4BO4mVK6RB 5kgIXOGQuNjbxgxR4yJx8Xk/lC0s8er4FqheKYnP7/ayQdjpEpuPbGaFsHMkOpqaoertJQ5c mcMCMp9ZQFNi/S59iLCsxNRT68BOYxbgk+j9/YQJIs4rsWMejK0msfhRJ5QtI7H20Seo8R4S LZPuskFCZSKjxJaVB5gnMMrNQlixgJFxFaNkakFxbnpqsWmBcV5qOTzekvNzNzGCE7OW9w7G Rw8+6B1iZOJgPMQowcGsJML7aVtyshBvSmJlVWpRfnxRaU5q8SFGU2D4TWSWEk3OB+aGvJJ4 QxNLAxMzMzMTS2MzQyVx3sUztJKFBNITS1KzU1MLUotg+pg4OKUamBLkZulNDnzOzvFxrf1K hWnrs+P/K/yZ+qVFwOTMaU1efb2SaE3O1R3LMlgcVhaceCB8I3iC0VSlrqvBWqEKkvqyn2WV I0701R2STDJw9/bRvJPJzaxi0rRPmuuF4xP+P+na/rtu8WxblLJiy7de2Zcr+PsOF1lNF/ui 1avSyq5d62df5vA6jPVwce0z0f70kPzvDFNvx/PmhXZNY6++u6lWYa+YwPQr89rmbw6w3fos dO/HUq3mCMVLHavn5khbTf5yQMHT9xs/+3WxWUby0f8KJrYst0t///+3uLSMrrBV1bZPusf3 n3BgX2umvmWdzOu5bLEfb5eenKnK69fLKtd2oG6PPGfE65TeunolluKMREMt5qLiRAAZdT5P VQQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrGLMWRmVeSWpSXmKPExsWy7bCSvG7vv5RkgzdrNC1+vpzGaDHnfAuL xfwj51gtnh57xG5x5NQSJot7i96xWvS9eMhscWFbH6vFpsfXWC0u75rDZtF17Qmrxby/a1kt ji0Qs/h2+g2jxaKtX9gt/r/eymhx5MwLZovWvUfYLW6/WcfqIOyxZeVNJo+n/VvZPXbOusvu sWBTqcemVZ1sHneu7WHz2Lyk3uP9vqtsHn1bVjF6HNxn6PH0x15mjy37PzN6fN4kF8AbxWWT kpqTWZZapG+XwJXx8tc+1oL72hWzrkxmbmBcq9zFyMkhIWAiMelDD3MXIxeHkMAORomGK03s EAkZiZMPljBD2MISK/89B4sLCTQzSXxdJg1iswnoSrRe+8wE0iwi8JBR4vznTlYQh1mgi1ni VdcOsG5hgVCJnk2XwWwWAVWJ7ev/gk3iFbCVePDzLdQ2eYnVGw4A1XBwcArYSaxcIQ1iCgGV zJ2vMYGRbwEjwypGydSC4tz03GLDAqO81HK94sTc4tK8dL3k/NxNjOCo0dLawbhn1Qe9Q4xM HIyHGCU4mJVEeD9tS04W4k1JrKxKLcqPLyrNSS0+xCjNwaIkznuh62S8kEB6YklqdmpqQWoR TJaJg1OqgWndgv3lPzQLhGeEWM94LjdB/Qv77Mhdiz4/Pabauq3y5wOFtXt1VZ+qfd9454wE 2+G/8SHRHx+JRh4yT+juiQ5w1G9/oLanqrbp4+HfwXI/loXrWVorNP0qqZbfKx0W5FArNv21 YLnY6tchrRl8eZcNo9wcjBP8hLMc4p9eD/rns1vUoOC44BoV8cvN5gEcvSXv/kbNe9atwnf2 scE3h9WMyqdnyqlrxDOcZd/Na+hao2mnrJVTvjEx7MvJ+U7XZ9vPkHIS/yN2pmJlmELpucWP 6/4vYtoQk+p20u/P5oNH3usWWu140CHhL1a/lkX34+aFu3s2HC1245nKeHeqht//PRYmkUuz Z/pmOPXLK7EUZyQaajEXFScCAEYGT3MJAwAA X-CMS-MailID: 20221104115909epcas5p25a8a564cd18910ec2368341855c1a6a2 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20221104115909epcas5p25a8a564cd18910ec2368341855c1a6a2 References: <20221104120517.77980-1-sriranjani.p@samsung.com> X-Spam-Status: No, score=-5.4 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_MED, RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748568029798440716?= X-GMAIL-MSGID: =?utf-8?q?1748568029798440716?= The FSD SoC contains two instances of Synopsys DWC QoS Ethernet IP, one in FSYS0 block and other in PERIC block. Adds device tree node for Ethernet in PERIC Block and enables the same for FSD platform. Cc: Rob Herring Cc: Krzysztof Kozlowski Cc: Richard Cochran Cc: devicetree@vger.kernel.org Signed-off-by: Pankaj Dubey Signed-off-by: Jayati Sahu Signed-off-by: Sriranjani P --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 9 ++++ arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi | 56 +++++++++++++++++++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 58 ++++++++++++++++++++++ 3 files changed, 123 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 42bf25c680e2..328db875667a 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -39,6 +39,15 @@ }; }; +ðernet_1 { + status = "okay"; + + fixed-link { + speed=<1000>; + full-duplex; + }; +}; + &fin_pll { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi index 8c7e43085a2b..94ef5392ad9c 100644 --- a/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd-pinctrl.dtsi @@ -395,6 +395,62 @@ samsung,pin-pud = ; samsung,pin-drv = ; }; + + eth1_tx_clk: eth1-tx-clk-pins { + samsung,pins = "gpf2-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_tx_data: eth1-tx-data-pins { + samsung,pins = "gpf2-1", "gpf2-2", "gpf2-3", "gpf2-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_tx_ctrl: eth1-tx-ctrl-pins { + samsung,pins = "gpf2-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_phy_intr: eth1-phy-intr-pins { + samsung,pins = "gpf2-6"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_rx_clk: eth1-rx-clk-pins { + samsung,pins = "gpf3-0"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_rx_data: eth1-rx-data-pins { + samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3", "gpf3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_rx_ctrl: eth1-rx-ctrl-pins { + samsung,pins = "gpf3-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + eth1_mdio: eth1-mdio-pins { + samsung,pins = "gpf3-6", "gpf3-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; }; &pinctrl_pmu { diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index 2495928b71dc..e63c1f8fa6ca 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -33,6 +33,7 @@ spi1 = &spi_1; spi2 = &spi_2; eth0 = ðernet_0; + eth1 = ðernet_1; }; cpus { @@ -898,6 +899,63 @@ status = "disabled"; phy-mode = "rgmii"; }; + + ethernet_1: ethernet@14300000 { + compatible = "tesla,dwc-qos-ethernet-4.21"; + reg = <0x0 0x14300000 0x0 0x10000>; + interrupts = ; + clocks = + /* ptp ref clock */ + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_PTP_REF_I>, + /* aclk clocks */ + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_ACLK_I>, + /* hclk clocks */ + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_HCLK_I>, + /* rgmii clocks */ + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_RGMII_CLK_I>, + /* rxi clocks */ + <&clock_peric PERIC_EQOS_TOP_IPCLKPORT_CLK_RX_I>, + /* eqos d-bus clocks */ + <&clock_peric PERIC_BUS_D_PERIC_IPCLKPORT_EQOSCLK>, + /* eqos p-bus clocks */ + <&clock_peric PERIC_BUS_P_PERIC_IPCLKPORT_EQOSCLK>, + /* eqos peric clock mux */ + <&clock_peric PERIC_EQOS_PHYRXCLK_MUX>, + /* eqos peric phy rxclock */ + <&clock_peric PERIC_EQOS_PHYRXCLK>, + /* internal peric rgmii clk */ + <&clock_peric PERIC_DOUT_RGMII_CLK>; + clock-names = + /* ptp ref clocks */ + "ptp_ref", + /* aclk clocks */ + "master_bus", + /* hclk clocks */ + "slave_bus", + /* rgmii clk */ + "tx", + /* rxi clocks */ + "rx", + /* eqos dbus clocks */ + "master2_bus", + /* eqos pbus clocks */ + "slave2_bus", + /* rgmii clock mux */ + "eqos_rxclk_mux", + /* rgmii phy rx clock */ + "eqos_phyrxclk", + /* internal peric rgmii clk */ + "dout_peric_rgmii_clk"; + pinctrl-names = "default"; + pinctrl-0 = <ð1_tx_clk>, <ð1_tx_data>, <ð1_tx_ctrl>, + <ð1_phy_intr>, <ð1_rx_clk>, <ð1_rx_data>, + <ð1_rx_ctrl>, <ð1_mdio>; + local-mac-address = [45 54 48 31 4d 43]; + rx-clock-skew = <&sysreg_peric 0x10 0x0>; + iommus = <&smmu_peric 0x0 0x1>; + status = "disabled"; + phy-mode = "rgmii"; + }; }; };