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Peter Anvin" Cc: linux-kernel@vger.kernel.org Subject: [PATCH v2 1/4] x86/resctrl: Enable non-contiguous bits in Intel CAT Date: Fri, 22 Sep 2023 10:48:23 +0200 Message-ID: <918e147601697b1d4b8f8589f5751e05d6ceccdf.1695371055.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 22 Sep 2023 01:49:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777751387450408610 X-GMAIL-MSGID: 1777761004715848284 The setting for non-contiguous 1s support in Intel CAT is hardcoded to false. On these systems, writing non-contiguous 1s into the schemata file will fail before resctrl passes the value to the hardware. In Intel CAT CPUID.0x10.1:ECX[3] and CPUID.0x10.2:ECX[3] stopped being reserved and now carry information about non-contiguous 1s value support for L3 and L2 cache respectively. The CAT capacity bitmask (CBM) supports a non-contiguous 1s value if the bit is set. Replace the hardcoded non-contiguous support value with the support learned from the hardware. Add hardcoded non-contiguous support value to Haswell probe since it can't make use of CPUID for Cache allocation. Originally-by: Fenghua Yu Signed-off-by: Maciej Wieczor-Retman Reviewed-by: Peter Newman Tested-by: Peter Newman --- Changelog v2: - Rewrite part of a comment concerning Haswell. (Reinette) arch/x86/kernel/cpu/resctrl/core.c | 9 ++++++--- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 10 ++++++---- arch/x86/kernel/cpu/resctrl/internal.h | 9 +++++++++ 3 files changed, 21 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 030d3b409768..c783a873147c 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -152,6 +152,7 @@ static inline void cache_alloc_hsw_probe(void) r->cache.cbm_len = 20; r->cache.shareable_bits = 0xc0000; r->cache.min_cbm_bits = 2; + r->cache.arch_has_sparse_bitmaps = false; r->alloc_capable = true; rdt_alloc_capable = true; @@ -267,15 +268,18 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) { struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); union cpuid_0x10_1_eax eax; + union cpuid_0x10_x_ecx ecx; union cpuid_0x10_x_edx edx; - u32 ebx, ecx; + u32 ebx; - cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx, &edx.full); + cpuid_count(0x00000010, idx, &eax.full, &ebx, &ecx.full, &edx.full); hw_res->num_closid = edx.split.cos_max + 1; r->cache.cbm_len = eax.split.cbm_len + 1; r->default_ctrl = BIT_MASK(eax.split.cbm_len + 1) - 1; r->cache.shareable_bits = ebx & r->default_ctrl; r->data_width = (r->cache.cbm_len + 3) / 4; + if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) + r->cache.arch_has_sparse_bitmaps = ecx.split.noncont; r->alloc_capable = true; } @@ -872,7 +876,6 @@ static __init void rdt_init_res_defs_intel(void) if (r->rid == RDT_RESOURCE_L3 || r->rid == RDT_RESOURCE_L2) { - r->cache.arch_has_sparse_bitmaps = false; r->cache.arch_has_per_cpu_cfg = false; r->cache.min_cbm_bits = 1; } else if (r->rid == RDT_RESOURCE_MBA) { diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index b44c487727d4..f076f12cf8e8 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -87,10 +87,12 @@ int parse_bw(struct rdt_parse_data *data, struct resctrl_schema *s, /* * Check whether a cache bit mask is valid. - * For Intel the SDM says: - * Please note that all (and only) contiguous '1' combinations - * are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.). - * Additionally Haswell requires at least two bits set. + * On Intel CPUs, non-contiguous 1s value support is indicated by CPUID: + * - CPUID.0x10.1:ECX[3]: L3 non-contiguous 1s value supported if 1 + * - CPUID.0x10.2:ECX[3]: L2 non-contiguous 1s value supported if 1 + * + * Haswell does not support a non-contiguous 1s value and additionally + * requires at least two bits set. * AMD allows non-contiguous bitmasks. */ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 85ceaf9a31ac..c47ef2f13e8e 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -492,6 +492,15 @@ union cpuid_0x10_3_eax { unsigned int full; }; +/* CPUID.(EAX=10H, ECX=ResID).ECX */ +union cpuid_0x10_x_ecx { + struct { + unsigned int reserved:3; + unsigned int noncont:1; + } split; + unsigned int full; +}; + /* CPUID.(EAX=10H, ECX=ResID).EDX */ union cpuid_0x10_x_edx { struct { From patchwork Fri Sep 22 08:48:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maciej Wieczor-Retman X-Patchwork-Id: 143462 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5611817vqi; Fri, 22 Sep 2023 07:17:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFVyOaJY0riZgjr0w2tG83Hf2lmKp5VEYY3wOgozZivf5tie/GsHjGtam7tazww3alpV/fi X-Received: by 2002:a17:902:f548:b0:1c5:d354:93b6 with SMTP id h8-20020a170902f54800b001c5d35493b6mr5073997plf.67.1695392248313; Fri, 22 Sep 2023 07:17:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695392248; cv=none; d=google.com; s=arc-20160816; b=w72viTTFUPadspMqZLz4G9pzN4NBwL9eIdgHpGraIfX794vNWLLKjqESqRCC/gFHYS H3Xw4CRJS8/0w/OSHxzjGc1ogiNFqUPj3ngnbOQp/dxSjaLWYdF8rjtAbcEJpQ17jv0F /yasHZRiL7bYLVUpMLKMP2UY4CJXmxI3Rlz2TL1xxg3NvLq7RJV0YycTsKqfUGK/Dla+ qyzclBiJ0WI0K1yASPQ/DJnuECPl1PbaGw507qnN2r9R90l23flE1ZqAMj5Mh9U92IlE wkKS19N/KwaCCdUUcu5mSpy2aR4EYfofoVKat4msLHGortwlOTcRP2T4rzxvWQVxiyLU nouA== ARC-Message-Signature: i=1; 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Peter Anvin" Cc: linux-kernel@vger.kernel.org Subject: [PATCH v2 2/4] x86/resctrl: Add sparse_masks file in info Date: Fri, 22 Sep 2023 10:48:24 +0200 Message-ID: <3b7f8c61f0f443e303bc9c5075566b89ffdebe7f.1695371055.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H3,RCVD_IN_MSPIKE_WL, SPF_HELO_NONE,SPF_NONE,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 22 Sep 2023 01:49:20 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777747621810257269 X-GMAIL-MSGID: 1777747621810257269 From: Fenghua Yu Add the interface in resctrl FS to show if sparse cache allocations bit masks are supported on the platform. Reading the file returns either a "1" if non-contiguous 1s are supported and "0" otherwise. The file path is /sys/fs/resctrl/info/{resource}/sparse_masks, where {resource} can be either "L2" or "L3". Signed-off-by: Fenghua Yu Signed-off-by: Maciej Wieczor-Retman --- Changelog v2: - Change bitmap naming convention to bit mask. (Reinette) - Change file name to "sparse_masks". (Reinette) arch/x86/kernel/cpu/resctrl/rdtgroup.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 725344048f85..5383169ff982 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -895,6 +895,17 @@ static int rdt_shareable_bits_show(struct kernfs_open_file *of, return 0; } +static int rdt_has_sparse_bitmaps_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) +{ + struct resctrl_schema *s = of->kn->parent->priv; + struct rdt_resource *r = s->res; + + seq_printf(seq, "%u\n", r->cache.arch_has_sparse_bitmaps); + + return 0; +} + /** * rdt_bit_usage_show - Display current usage of resources * @@ -1839,6 +1850,13 @@ static struct rftype res_common_files[] = { .seq_show = rdtgroup_size_show, .fflags = RF_CTRL_BASE, }, + { + .name = "sparse_masks", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdt_has_sparse_bitmaps_show, + .fflags = RF_CTRL_INFO | RFTYPE_RES_CACHE, + }, }; From patchwork Fri Sep 22 08:48:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maciej Wieczor-Retman X-Patchwork-Id: 143415 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5548344vqi; Fri, 22 Sep 2023 05:56:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEP8NEtmogzUKVAg4HZSptpGsmXQIpBghoarrP7BFALX1MWLtiWEZqebHsT3pquPOmx0lbh X-Received: by 2002:a05:6a21:7982:b0:15e:a8:6bb4 with SMTP id bh2-20020a056a21798200b0015e00a86bb4mr275252pzc.8.1695387402916; Fri, 22 Sep 2023 05:56:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695387402; cv=none; d=google.com; s=arc-20160816; b=hmQEUaTEAv1FJvWmFYMlVo/U9DwkhjLsq3lfKgnkdQTIx4HPhI2FWWA9XuQI4CK0vt wfdQEqW2HkYAOfFgWcqSLawH1+DYeDsPwMzeadBras2siYOBh+8VtpCDLumOJy4sY0SJ H/AEuFpKG5G7zECbR0e+b7Zh+xTu+Fgwy1CqiBnPnlc9JV6BG1Eu5tUDWJeP+d199cV5 mvwxl1ifuCWRQNYVg5vGVKattT6R9khQ/lH/q4/Oljvw++VVn7k0q1+EsPSIPuENPmkH 6VWijskJbh1f/mf64/RJrwd3a0enz7gTP00SvH0CBCCQWeOqd1ZXft6Egk47b48t3Jp8 0rxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ex5jlUrXJC279gM4NXcAPdZYA8oQs9PsGGp+TAzN//Y=; fh=qtEk00d2+4XMfn63r4rr3njQyy4aQXo4MEaOJVONGlQ=; b=FZbCKtsFEHUCIMz+6/P4lTQ9/tuVERE0NxW4wZtGjCilXGaNUa+90/plC3tH16zKAR A0Uf3GXMoTU7zjyq4THQJTDEUTqS5xQoZov8TfL32/cFGBqUB525IUyv6UsAs+b7PRAP cS+8EZIOj5CO9JvOq10dxsHr0izgwQXbxx0yYuEX/mXA8k9tOBFTy+1d/aUSuqK/kQ4g aNCBSdby4SZj1jJ2DIv+Fq6UIGJEm75eB3NDtbHbPdNOTmffAHvuH/KclTAPk80q90AH 6rSLQfnBE1Dli5Y77JmCGBt7zqnmsd2oupCxO3ZcoDjHPDJbLfpVf3ggX2h8YJwweZ9g UIvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=LH2gtsc6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from agentk.vger.email (agentk.vger.email. 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Peter Anvin" , Jonathan Corbet Cc: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org Subject: [PATCH v2 3/4] Documentation/x86: Document resctrl's new sparse_masks Date: Fri, 22 Sep 2023 10:48:25 +0200 Message-ID: <308c92438288a45a12330af83aa0088a31f60343.1695371055.git.maciej.wieczor-retman@intel.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 22 Sep 2023 01:49:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777742541252876315 X-GMAIL-MSGID: 1777742541252876315 From: Fenghua Yu The documentation mentions that non-contiguous bit masks are not supported in Intel Cache Allocation Technology (CAT). Update the documentation on how to determine if sparse bit masks are allowed in L2 and L3 CAT. Mention the file with feature support information is located in the /sys/fs/resctrl/info/{resource}/ directories and enumerate what are the possible outputs on file read operation. Signed-off-by: Fenghua Yu Signed-off-by: Maciej Wieczor-Retman --- Changelog v2: - Change bitmap naming convention to bit mask. (Reinette) Documentation/arch/x86/resctrl.rst | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index cb05d90111b4..4c6421e2aa31 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -124,6 +124,13 @@ related to allocation: "P": Corresponding region is pseudo-locked. No sharing allowed. +"sparse_masks": + Indicates if non-contiguous 1s value in CBM is supported. + + "0": + Only contiguous 1s value in CBM is supported. + "1": + Non-contiguous 1s value in CBM is supported. Memory bandwidth(MB) subdirectory contains the following files with respect to allocation: @@ -445,12 +452,13 @@ For cache resources we describe the portion of the cache that is available for allocation using a bitmask. The maximum value of the mask is defined by each cpu model (and may be different for different cache levels). It is found using CPUID, but is also provided in the "info" directory of -the resctrl file system in "info/{resource}/cbm_mask". Intel hardware +the resctrl file system in "info/{resource}/cbm_mask". Some Intel hardware requires that these masks have all the '1' bits in a contiguous block. So 0x3, 0x6 and 0xC are legal 4-bit masks with two bits set, but 0x5, 0x9 -and 0xA are not. On a system with a 20-bit mask each bit represents 5% -of the capacity of the cache. You could partition the cache into four -equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. +and 0xA are not. Check /sys/fs/resctrl/info/{resource}/sparse_masks +if non-contiguous 1s value is supported. On a system with a 20-bit mask +each bit represents 5% of the capacity of the cache. You could partition +the cache into four equal parts with masks: 0x1f, 0x3e0, 0x7c00, 0xf8000. Memory bandwidth Allocation and monitoring ========================================== From patchwork Fri Sep 22 08:48:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maciej Wieczor-Retman X-Patchwork-Id: 143543 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5737478vqi; Fri, 22 Sep 2023 10:05:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFops3jznaWV4i3QkvcrgTfUhAy2J2kwwneWhDTJaw2HOKjfNyUno3/A5vJpXYCZoQ6JyyT X-Received: by 2002:a17:903:41cc:b0:1c1:d4f4:cd3c with SMTP id u12-20020a17090341cc00b001c1d4f4cd3cmr111088ple.31.1695402332524; Fri, 22 Sep 2023 10:05:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695402332; cv=none; d=google.com; s=arc-20160816; b=AkFgKaXEjRa7ptkPInA6E+RWDlU/Su7siVdZRb//h3wxaYulo+dcc2gFoEnXCk89nV MXmXifXsj+6zsP0fEQombKL250Fa4DfzaUCwfJ4kTjKsO1h1s0UVWZ0njHs6TERIjemu FVIdqzBv/jaNE5AE1pF1yVmg4bz5YC+JQRqhcW5wr2q6j5yH+Vw0G1Jp3I5yOkZUxrB4 XMRNXnByZ1zW7sCieskpC4eVcqx/d9rTersh+cIGYvBhPiInWBu1mSTM7hfLYCE27Iiq pwffuKG0WaUJYLP+GvRp0kDr52BvLdXj+X8y6HB+UYA2Ci/6QwvvOGIQ3k8pKXGi61Eu 2B8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8UCI+Jv7gb4GAszIM+qknuDgrSet9WXQnVDef+xmMaI=; fh=JoGJTBLBX0mCLsj1pwi/CRHCOqwSpQQHNFK25Wueyf0=; b=Xq3uVw19EmcB3JBapIy7Ggia1FuE1kvQOkjnvKTpyqoFRXa0uCTmzvIRVybLROaTrv ++OijF0Q+gGQ1LwXAcTO4712gGvygY4563Ihj5H9m+KwU2JeWioMwIe3vC4m9ARYA8Q1 2PwOmi1+2wNatYJwKQ9LnYWEOFZ7fgOw86nw/OtHbED0OtXV3JaH3Z9LWmAewywmV9V3 LsMti5WE2S/sckZ5AAFXCPPFcSAtmOccLUh4x6kmoB0/0CyP3KJdUsUhIrqmwV2E9eKs 0J2LDaBnR8sJ9640Qger4RmOg1b9kdOgJsIxIS2APEkybMhsjt8pPLq2C9izBgaYHWaA a0nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Z2SF1XeA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from agentk.vger.email (agentk.vger.email. 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Peter Anvin" Cc: linux-kernel@vger.kernel.org Subject: [PATCH v2 4/4] x86/resctrl: Rename arch_has_sparse_bitmaps Date: Fri, 22 Sep 2023 10:48:26 +0200 Message-ID: X-Mailer: git-send-email 2.42.0 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 22 Sep 2023 01:50:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777758196374714159 X-GMAIL-MSGID: 1777758196374714159 Both AMD and Intel documentations use capacity bitmasks terminology rather than capacity bitmaps. Also bitmask term is much more widely used inside x86 resctrl code. Unify the naming convention by renaming arch_has_sparse_bitmaps struct member to arch_has_sparse_bitmasks. Suggested-by: Reinette Chatre Signed-off-by: Maciej Wieczor-Retman --- Changelog v2: - Created this patch. arch/x86/kernel/cpu/resctrl/core.c | 6 +++--- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 4 ++-- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 8 ++++---- include/linux/resctrl.h | 6 +++--- 4 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index c783a873147c..19e0681f0435 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -152,7 +152,7 @@ static inline void cache_alloc_hsw_probe(void) r->cache.cbm_len = 20; r->cache.shareable_bits = 0xc0000; r->cache.min_cbm_bits = 2; - r->cache.arch_has_sparse_bitmaps = false; + r->cache.arch_has_sparse_bitmasks = false; r->alloc_capable = true; rdt_alloc_capable = true; @@ -279,7 +279,7 @@ static void rdt_get_cache_alloc_cfg(int idx, struct rdt_resource *r) r->cache.shareable_bits = ebx & r->default_ctrl; r->data_width = (r->cache.cbm_len + 3) / 4; if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) - r->cache.arch_has_sparse_bitmaps = ecx.split.noncont; + r->cache.arch_has_sparse_bitmasks = ecx.split.noncont; r->alloc_capable = true; } @@ -895,7 +895,7 @@ static __init void rdt_init_res_defs_amd(void) if (r->rid == RDT_RESOURCE_L3 || r->rid == RDT_RESOURCE_L2) { - r->cache.arch_has_sparse_bitmaps = true; + r->cache.arch_has_sparse_bitmasks = true; r->cache.arch_has_per_cpu_cfg = true; r->cache.min_cbm_bits = 0; } else if (r->rid == RDT_RESOURCE_MBA) { diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index f076f12cf8e8..beccb0e87ba7 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -115,8 +115,8 @@ static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r) first_bit = find_first_bit(&val, cbm_len); zero_bit = find_next_zero_bit(&val, cbm_len, first_bit); - /* Are non-contiguous bitmaps allowed? */ - if (!r->cache.arch_has_sparse_bitmaps && + /* Are non-contiguous bitmasks allowed? */ + if (!r->cache.arch_has_sparse_bitmasks && (find_next_bit(&val, cbm_len, zero_bit) < cbm_len)) { rdt_last_cmd_printf("The mask %lx has non-consecutive 1-bits\n", val); return false; diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 5383169ff982..945801898a4d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -895,13 +895,13 @@ static int rdt_shareable_bits_show(struct kernfs_open_file *of, return 0; } -static int rdt_has_sparse_bitmaps_show(struct kernfs_open_file *of, - struct seq_file *seq, void *v) +static int rdt_has_sparse_bitmasks_show(struct kernfs_open_file *of, + struct seq_file *seq, void *v) { struct resctrl_schema *s = of->kn->parent->priv; struct rdt_resource *r = s->res; - seq_printf(seq, "%u\n", r->cache.arch_has_sparse_bitmaps); + seq_printf(seq, "%u\n", r->cache.arch_has_sparse_bitmasks); return 0; } @@ -1854,7 +1854,7 @@ static struct rftype res_common_files[] = { .name = "sparse_masks", .mode = 0444, .kf_ops = &rdtgroup_kf_single_ops, - .seq_show = rdt_has_sparse_bitmaps_show, + .seq_show = rdt_has_sparse_bitmasks_show, .fflags = RF_CTRL_INFO | RFTYPE_RES_CACHE, }, diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 8334eeacfec5..83c2cbf7136d 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -57,7 +57,7 @@ struct resctrl_staged_config { * @list: all instances of this resource * @id: unique id for this instance * @cpu_mask: which CPUs share this resource - * @rmid_busy_llc: bitmap of which limbo RMIDs are above threshold + * @rmid_busy_llc: bitmask of which limbo RMIDs are above threshold * @mbm_total: saved state for MBM total bandwidth * @mbm_local: saved state for MBM local bandwidth * @mbm_over: worker to periodically read MBM h/w counters @@ -94,7 +94,7 @@ struct rdt_domain { * zero CBM. * @shareable_bits: Bitmask of shareable resource with other * executing entities - * @arch_has_sparse_bitmaps: True if a bitmap like f00f is valid. + * @arch_has_sparse_bitmasks: True if a bitmask like f00f is valid. * @arch_has_per_cpu_cfg: True if QOS_CFG register for this cache * level has CPU scope. */ @@ -102,7 +102,7 @@ struct resctrl_cache { unsigned int cbm_len; unsigned int min_cbm_bits; unsigned int shareable_bits; - bool arch_has_sparse_bitmaps; + bool arch_has_sparse_bitmasks; bool arch_has_per_cpu_cfg; };