From patchwork Fri Sep 22 09:28:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 143293 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5435913vqi; Fri, 22 Sep 2023 02:38:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFsI3IsfvuUkbFIxSuTKTYnUX60M4Qrj/jA5yVvUV1jEhJhd5Hz/e+qOKjC2VoS9oSVLpRc X-Received: by 2002:a17:903:22cc:b0:1c5:b4a1:ff6 with SMTP id y12-20020a17090322cc00b001c5b4a10ff6mr9129716plg.45.1695375489167; Fri, 22 Sep 2023 02:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695375489; cv=none; d=google.com; s=arc-20160816; b=Q9/qX0hSEKRyDOXRuStIYHk72zMd865aKV56kmDKe99KK4sFFuhbeNsaL0Z2bXjowN bzeK0KB3sBwdYDpe0A2KcsyzEFwa4DDz7cJ6RzcgrqaZ1AIXqPN82N9x9VDoOvDMiF78 EuUXGettVG/5v4N7t6qA4iWARl6//SwJMD+YEwMLl55ll2Ueyr6XW5DYviXLyKbfckqJ U7xHlx5+UxEh1Fpwdj6gXeY+EYtQVQl5geU8dUbzgfMsRT3Y1FjO7sYTTuCBWVG6yhkb r7tYfam6UEKkuVuvGNBP2JuvsRymq2XglGm3JWiGVY0eX2GEFlq19hBeStwp4gNdVCkY PD9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=tZB1Gpl6nVRZRmMpfmbs0mFiZCBVmuVfTXoMiXC2tgw=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=yJ5yb4RUEoeWM6PnYtDpeD09TlPJiH9Td/nnUnpWV++9PYm/wjTC6cxmXM+r+CXCZM EgO2ZhIsdzLlO5YwdA8Cbta/OyV+cs+f46IVdjcB6fZspcCG+selAv7VJjuQNFj/ujYc akAoq/+RhbcW2DHBLSIggFYTXC6YMbtTtPGMhMaF5aqYUFXCGF783qhzFFMmwFSqgCwo U79yLN1+n/d0F9UpbxFpwqkkKry3FkvOQ2Zl5TrxlSPjejs30GxIiVjyQlyQ3BqwQEZ7 QdAGmWyXxhlsfq3YwrGuWeoX/J6HshRa4GezVo34RNhpi84YJNHUejVQXPqoyiOsQwI+ /l7g== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id x12-20020a1709028ecc00b001b87bd2f7b0si3178089plo.402.2023.09.22.02.38.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 02:38:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D8DD0831554E; Fri, 22 Sep 2023 02:29:05 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232950AbjIVJ3H convert rfc822-to-8bit (ORCPT + 30 others); Fri, 22 Sep 2023 05:29:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56214 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232939AbjIVJ3C (ORCPT ); Fri, 22 Sep 2023 05:29:02 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 58C3419E; Fri, 22 Sep 2023 02:28:53 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 12E2A17EDF; Fri, 22 Sep 2023 17:28:51 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:51 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:49 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 1/4] dt-bindings: pwm: Add StarFive PWM module Date: Fri, 22 Sep 2023 17:28:45 +0800 Message-ID: <20230922092848.72664-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 22 Sep 2023 02:29:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777730049170967576 X-GMAIL-MSGID: 1777730049170967576 Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/starfive,jh7100-pwm.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml new file mode 100644 index 000000000000..6f1937beb962 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/starfive,jh7100-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7100 and JH7110 PWM controller + +maintainers: + - William Qiu + +description: + StarFive SoCs contain PWM and when operating in PWM mode, the PTC core generates + binary signal with user-programmable low and high periods. Clock source for the + PWM can be either system clock or external clock. Each PWM timer block provides 8 + PWM channels. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - starfive,jh7100-pwm + - starfive,jh7110-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - resets + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; From patchwork Fri Sep 22 09:28:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 143290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5433678vqi; Fri, 22 Sep 2023 02:32:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFZQdiFGNfxPlbsXkeX3WQf4Kjh4qjeTocwGcRV6GI/KYSFXMC0gAa7VwBFKakPzckhwWww X-Received: by 2002:a05:6a00:3a1e:b0:68a:3ba3:e249 with SMTP id fj30-20020a056a003a1e00b0068a3ba3e249mr8855619pfb.16.1695375163574; Fri, 22 Sep 2023 02:32:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695375163; cv=none; d=google.com; s=arc-20160816; b=J1X1uEf3Iqk9Xrob4hz93lbOY5xwSVAm7K3BzmAupQB+kffvv59jaRoPYRUudDDE0C 2BEpk4imtQq3/XjX+mSVGc5+tCSZXvwPTaJnf3/tnOUTFlVDZHQ/W8599G2kqZ2SX0NP lxoPRwdM/XQoraAlh89xmW+cibcMC6ki03TJh8zwUpsZ4JW+3kxKPvuxgpNw+McCV+Jd WS5M6TZnmxcX2IKAHJNxiVF5dvyMrTphnHlkX7s4oVommAwMMg8TqHh9PU4bO1bYzpwj fHizvi9fHwRuhJmVV9/xBRt6YbhsHJqtpymNNAz5PDBPV0LFY5jGNur/iJj6r2IjVIwx UXSg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=7lyD79G2iftiGZOxiPqraxaGqTVQ44pvHl60+AxjeHk=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=iCrSRluWfnMKjKqqq69cBB7O5NOJJRKi9uXEpUeR0gaE8zkAC5H7lXMZYGqP7Gk644 AzwOqWmQBgXMJRevmPR+5873g2TI04zg+WHlPCn6RaUHghRVkjOI7laDUVgeQ/1r/vDP PH+tsnp5MCFD/hoIB0Uk/NW6elt+izg7Lw4tmUW2vZgQRY39nGVhVup8MUNfF+R/w4rw Ul2QNAiI4G6EkFayzV1FPWgzVbBDP4TXTQN7T8MbecVg1d0j+WUl6P0AwP2WgT5WjYuT DDjxXHNSumunkNPqGT+sJhwJRGIRA/Ko4ggqrW+5aDHyqmrvPo+Velkhx/01hpBZjj8J n9sw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id v15-20020a65460f000000b005704979833csi3227247pgq.855.2023.09.22.02.32.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 02:32:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id E033C83FC3BE; Fri, 22 Sep 2023 02:29:26 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232977AbjIVJ3M convert rfc822-to-8bit (ORCPT + 30 others); Fri, 22 Sep 2023 05:29:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233001AbjIVJ3H (ORCPT ); Fri, 22 Sep 2023 05:29:07 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9BF31BC; Fri, 22 Sep 2023 02:28:59 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id E518624E2A1; Fri, 22 Sep 2023 17:28:51 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:52 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:50 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 2/4] pwm: starfive: Add PWM driver support Date: Fri, 22 Sep 2023 17:28:46 +0800 Message-ID: <20230922092848.72664-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 22 Sep 2023 02:29:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777729707368272793 X-GMAIL-MSGID: 1777729707368272793 Add Pulse Width Modulation driver support for StarFive JH7100 and JH7110 SoC. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 9 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-starfive.c | 190 +++++++++++++++++++++++++++++++++++++ 4 files changed, 207 insertions(+) create mode 100644 drivers/pwm/pwm-starfive.c diff --git a/MAINTAINERS b/MAINTAINERS index bf0f54c24f81..bc2155bd2712 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20495,6 +20495,13 @@ F: drivers/pinctrl/starfive/pinctrl-starfive-jh71* F: include/dt-bindings/pinctrl/pinctrl-starfive-jh7100.h F: include/dt-bindings/pinctrl/starfive,jh7110-pinctrl.h +STARFIVE JH71X0 PWM DRIVERS +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/starfive,jh7100-pwm.yaml +F: drivers/pwm/pwm-starfive-ptc.c + STARFIVE JH71X0 RESET CONTROLLER DRIVERS M: Emil Renner Berthing M: Hal Feng diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..e2ee0169f6e4 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -569,6 +569,15 @@ config PWM_SPRD To compile this driver as a module, choose M here: the module will be called pwm-sprd. +config PWM_STARFIVE + tristate "StarFive PWM support" + depends on ARCH_STARFIVE || COMPILE_TEST + help + Generic PWM framework driver for StarFive SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-starfive. + config PWM_STI tristate "STiH4xx PWM support" depends on ARCH_STI || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..93b954376873 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_PWM_SIFIVE) += pwm-sifive.o obj-$(CONFIG_PWM_SL28CPLD) += pwm-sl28cpld.o obj-$(CONFIG_PWM_SPEAR) += pwm-spear.o obj-$(CONFIG_PWM_SPRD) += pwm-sprd.o +obj-$(CONFIG_PWM_STARFIVE) += pwm-starfive.o obj-$(CONFIG_PWM_STI) += pwm-sti.o obj-$(CONFIG_PWM_STM32) += pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) += pwm-stm32-lp.o diff --git a/drivers/pwm/pwm-starfive.c b/drivers/pwm/pwm-starfive.c new file mode 100644 index 000000000000..d390349fc95d --- /dev/null +++ b/drivers/pwm/pwm-starfive.c @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM driver for the StarFive JH71x0 SoC + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/* Access PTC register (CNTR, HRC, LRC and CTRL) */ +#define REG_PTC_BASE_ADDR_SUB(base, N) ((base) + (((N) > 3) ? \ + (((N) % 4) * 0x10 + (1 << 15)) : ((N) * 0x10))) +#define REG_PTC_RPTC_CNTR(base, N) (REG_PTC_BASE_ADDR_SUB(base, N)) +#define REG_PTC_RPTC_HRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x4) +#define REG_PTC_RPTC_LRC(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0x8) +#define REG_PTC_RPTC_CTRL(base, N) (REG_PTC_BASE_ADDR_SUB(base, N) + 0xC) + +/* PTC_RPTC_CTRL register bits*/ +#define PTC_EN BIT(0) +#define PTC_ECLK BIT(1) +#define PTC_NEC BIT(2) +#define PTC_OE BIT(3) +#define PTC_SIGNLE BIT(4) +#define PTC_INTE BIT(5) +#define PTC_INT BIT(6) +#define PTC_CNTRRST BIT(7) +#define PTC_CAPTE BIT(8) + +struct starfive_pwm_ptc_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +static inline struct starfive_pwm_ptc_device * +chip_to_starfive_ptc(struct pwm_chip *chip) + +{ + return container_of(chip, struct starfive_pwm_ptc_device, chip); +} + +static int starfive_pwm_ptc_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data; + + period_data = readl(REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + duty_data = readl(REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate); + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = (ctrl_data & PTC_EN) ? true : false; + + return 0; +} + +static int starfive_pwm_ptc_apply(struct pwm_chip *chip, + struct pwm_device *dev, + const struct pwm_state *state) +{ + struct starfive_pwm_ptc_device *pwm = chip_to_starfive_ptc(chip); + u32 period_data, duty_data, ctrl_data = 0; + + if (state->polarity != PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, + NSEC_PER_SEC); + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, + NSEC_PER_SEC); + + writel(period_data, REG_PTC_RPTC_LRC(pwm->regs, dev->hwpwm)); + writel(duty_data, REG_PTC_RPTC_HRC(pwm->regs, dev->hwpwm)); + writel(0, REG_PTC_RPTC_CNTR(pwm->regs, dev->hwpwm)); + + ctrl_data = readl(REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + if (state->enabled) + writel(ctrl_data | PTC_EN | PTC_OE, REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + else + writel(ctrl_data & ~(PTC_EN | PTC_OE), REG_PTC_RPTC_CTRL(pwm->regs, dev->hwpwm)); + + return 0; +} + +static const struct pwm_ops starfive_pwm_ptc_ops = { + .get_state = starfive_pwm_ptc_get_state, + .apply = starfive_pwm_ptc_apply, + .owner = THIS_MODULE, +}; + +static int starfive_pwm_ptc_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct starfive_pwm_ptc_device *pwm; + struct pwm_chip *chip; + int ret; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + chip = &pwm->chip; + chip->dev = dev; + chip->ops = &starfive_pwm_ptc_ops; + chip->npwm = 8; + chip->of_pwm_n_cells = 3; + + pwm->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->regs)) + return dev_err_probe(dev, PTR_ERR(pwm->regs), + "Unable to map IO resources\n"); + + pwm->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Unable to get pwm's clock\n"); + + pwm->rst = devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(pwm->rst)) + return dev_err_probe(dev, PTR_ERR(pwm->rst), + "Unable to get pwm's reset\n"); + + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(dev, "Failed to enable clock for pwm: %d\n", ret); + return ret; + } + + pwm->clk_rate = clk_get_rate(pwm->clk); + if (pwm->clk_rate <= 0) { + dev_warn(dev, "Failed to get APB clock rate\n"); + return -EINVAL; + } + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) { + dev_err(dev, "Cannot register PTC: %d\n", ret); + clk_disable_unprepare(pwm->clk); + reset_control_assert(pwm->rst); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int starfive_pwm_ptc_remove(struct platform_device *dev) +{ + struct starfive_pwm_ptc_device *pwm = platform_get_drvdata(dev); + + reset_control_assert(pwm->rst); + clk_disable_unprepare(pwm->clk); + + return 0; +} + +static const struct of_device_id starfive_pwm_ptc_of_match[] = { + { .compatible = "starfive,jh7100-pwm" }, + { .compatible = "starfive,jh7110-pwm" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, starfive_pwm_ptc_of_match); + +static struct platform_driver starfive_pwm_ptc_driver = { + .probe = starfive_pwm_ptc_probe, + .remove = starfive_pwm_ptc_remove, + .driver = { + .name = "pwm-starfive-ptc", + .of_match_table = starfive_pwm_ptc_of_match, + }, +}; +module_platform_driver(starfive_pwm_ptc_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("StarFive PWM PTC driver"); +MODULE_LICENSE("GPL"); From patchwork Fri Sep 22 09:28:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 143291 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5433696vqi; Fri, 22 Sep 2023 02:32:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IExZFDqR5gK5yEa+oKVqrtvSjBPldtkMjOf+tSi5ajjq2366k47dzEaSw4JUihYpbba6pt8 X-Received: by 2002:a81:5309:0:b0:59a:f6ee:3766 with SMTP id h9-20020a815309000000b0059af6ee3766mr7147398ywb.37.1695375165481; Fri, 22 Sep 2023 02:32:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695375165; cv=none; d=google.com; s=arc-20160816; b=Cnc56OLYWADnHDL7D7VDCCdy9uecqP2i6O8BnZ6NgljIrvedzjbdgnnwJlMow0AB5n 3NpXy8HZNPvNf7ptU3cbN0HZa37dm74/R6St6sLxUK3xPFTNA2H52Wl3D182iH+78ocl uZNlBQtZ//0evL5FLfhBRr80BrQcCQ3d2fXLvgqf8ujvAW5FC2vQ7Auh82CW/ctxpGSY JZN0dG9EN+dcSn+43JRsOkglWw+utwRxyGpcEQvaxtp5467pwkUlesnWlTWqo9MEO6nn MvM5XnGyPEXhqpvOnopqCXeR6ru+p9fSaC8+rUYdhHqcyGBNExoLfJnOuEVaz4CywkSO DlCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=FTp1Rg6aBXP4PndpiU8Koj61erzDnd5oSDNjCnzqqUI=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=VdrxH6iWEqR6dwYKGViGz4hivfqzxGjxQsBwhjxnb+68n7G7ul6nb2s259vF111pn6 xvKn7ZrBM/szq70H0Oe4JgzqLCUfT7yW9a+v5HHXvlBL0UAxlzIUmliq7jY2veREq0ov 7oynFb49DwQdCxsnRImuIMZCgajCEg4WHldT9ZaXy+sK6PVnqJvWZ9SPR5bTJyZbddo0 ycfMZmDGeuYOROZKIsrGb6TNu3+0KbEbAE+kiS1lnoKlwYPMOK/fpPT0FjG1SZUmFNDr i/UnJglinBEcOClUHiTVmEIsVTaUDJJjxnfP30oCCr9hr4itzJft/IT8H8i+ywQXAYRN caHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id s200-20020a632cd1000000b0056fad9586d2si3250434pgs.429.2023.09.22.02.32.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 02:32:45 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 28B66846830A; Fri, 22 Sep 2023 02:29:36 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233003AbjIVJ3O convert rfc822-to-8bit (ORCPT + 30 others); Fri, 22 Sep 2023 05:29:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232989AbjIVJ3G (ORCPT ); Fri, 22 Sep 2023 05:29:06 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A9C661BD; Fri, 22 Sep 2023 02:28:59 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id C617924E2A5; Fri, 22 Sep 2023 17:28:52 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:53 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:51 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Fri, 22 Sep 2023 17:28:47 +0800 Message-ID: <20230922092848.72664-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 22 Sep 2023 02:29:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777729709053380830 X-GMAIL-MSGID: 1777729709053380830 Add StarFive JH7110 PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index d79f94432b27..4bfb8f0f810f 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -268,6 +268,12 @@ reserved-data@600000 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; @@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>; From patchwork Fri Sep 22 09:28:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 143292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5434414vqi; Fri, 22 Sep 2023 02:34:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEwYmOAZtSoq6ohTA2p/Rj9qEXetHpOyH3nF/n/y6y3qVoZ/ZY7PWa+1vWVFC46Eqxqcdm2 X-Received: by 2002:a17:90a:f690:b0:26d:1a49:d1e9 with SMTP id cl16-20020a17090af69000b0026d1a49d1e9mr7766291pjb.17.1695375267932; Fri, 22 Sep 2023 02:34:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695375267; cv=none; d=google.com; s=arc-20160816; b=EcCAP8xWC0eJ3UzckrCfN4DSVKkwCneSioexMgwsJIe6GHO0PZbGtGPQqTo0NjZTX9 /uKhBywrlewfTgZ184D8v4uzrEZwyFiA9a7X1yuFWU6iQyEyhtcf/LmQ/fkQPnJfRaCN gQAYRLhKniacZ6z1RhjFD+eE8t7kMhW8NVonj5Gulwc3A9MiH+obblyRJkCmSqbf6013 7ilf/YqYiuF33HK0Enwq33BLHI7DFx/y9YS3ZmSc6Wa4Gs3Ap06m4czQnhnotXdSmL4J rtYof0443S+fEhYa0KU+nQGjiqtUKAPhVYNJ8f9fFTAoNgzTr5ZZGmra93dxW8TyxzBL SKxA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=U0Lp2dJCjs+zS5BcyeG/fPS6iH5USxXlyJnt+f/up+I=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=xAbQWL2PeXVof7G11CzI9uIpwTczemhUmFkUYJ/DPkqajs1M1uibPPXkVumUg/pm6D 0Ew+n3BC2m1RDIiGWPrdigG7z/DJu8eowLE9xV7sROP+kgayfKc/3LAvnrXF8B6Ubh58 4F5Wnza4RHSdX0v3iwBAKfPH57eZRj2/QsB3F00OlxyM2p+sooJksA7sopztIFiKvjbP JemxvdD8R0DmhPywVQx2NGC/hiITvxa3kh2wgUSaQdmoXskVVtoeWen2mgSivEcJMXQI 8lBJi6UKLyfs9r1vCqw5FIQRLQGtYt6wkbO5y2/NzMKbs9QGI2tB5oaBsyyZOZznwoDP DtvA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id nk6-20020a17090b194600b0025979e8c246si3552116pjb.70.2023.09.22.02.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Sep 2023 02:34:27 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id DA8E483FC3B8; Fri, 22 Sep 2023 02:29:12 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229559AbjIVJ3F convert rfc822-to-8bit (ORCPT + 30 others); Fri, 22 Sep 2023 05:29:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232941AbjIVJ3C (ORCPT ); Fri, 22 Sep 2023 05:29:02 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 105831B0; Fri, 22 Sep 2023 02:28:55 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 94D8017ED4; Fri, 22 Sep 2023 17:28:53 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:53 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 22 Sep 2023 17:28:52 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v5 4/4] riscv: dts: starfive: jh7100: Add PWM node and pins configuration Date: Fri, 22 Sep 2023 17:28:48 +0800 Message-ID: <20230922092848.72664-5-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230922092848.72664-1-william.qiu@starfivetech.com> References: <20230922092848.72664-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS061.cuchost.com (172.16.6.21) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 22 Sep 2023 02:29:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777729817195555199 X-GMAIL-MSGID: 1777729817195555199 Add StarFive JH7100 PWM controller node and add PWM pins configuration on VisionFive 1 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..11876906cc05 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..9c8c557031e6 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -274,6 +274,15 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh7100-pwm"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>;