From patchwork Thu Sep 21 03:36:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5078496vqi; Thu, 21 Sep 2023 12:13:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENX+eSIjjMTEI3TU57OuoV0bkT7eLf36lX9oRE3KdThoTC/TW64W0DbyR7w87epIdzxMrp X-Received: by 2002:a17:902:e851:b0:1b8:76ce:9d91 with SMTP id t17-20020a170902e85100b001b876ce9d91mr6346131plg.1.1695323581623; Thu, 21 Sep 2023 12:13:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695323581; cv=none; d=google.com; s=arc-20160816; b=kgCNk/mKaQZTyYlttpb+A3Sc272woFhqO6lzwWiRzIN5a6D9IhRZaWkqXVj+kEpZwN O7UQN6Ipq8YGmlwNarBq2rtKw4T6z/ww0IC/C5gzhU4doVM7udpW7wVDmksZQBt2z8+S Nvlnb8wQJsKNmOhZvnZWdZYSzOnoCZSKUxtv8gb8cM6H1PQYvXrgRWYzZMNkmTgQUShA zWY/hZFK/MHEQPdf05EvK+08v2qaj6XXZMP7xfuOcqU1brd63YpN+rrO/p5wWJ4Ze8Rk ITbYA0HHzInTZsdD/fgB+Tx9VL3RWLW7vDmK9XQDEL49Wa+7h127mJc0SgFkmzpd1YEu LjTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=lIKSc1L8JNYSxtTlGTrxKJ5F2yZL3v9XfGB/qKz4mmM=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=nOYM+IKEGWe+bDb2LAo7cy9vos89YqWV+cfRHWCh43OwC1n+Nq0MTKRmOSwXv0xmuP WtFg2bUFxk7wfbuYkkDgwUFLs/ocwuLHrRC0VbpjQp+x3l9X0dZOFWJr2bAnD1f33nST xh4+EYQzfE3BSqON+3zDAk6Hj9m1dETBgV7s5mFG+/Dr/V3loMLxrLSQI2MKGjIH1+UI HC3Zu+9cd8d1xn+aArrV0IOB65gYi8+Sa0OsVar/WWDbTdIlWpYV8SvzsGb62dQcfYcC KH1CcgMVqnStiuUltt7Dy9tMv6dcuwGYo3tB6wMC6FEnmNtsPKpkIZKC1z82d98xkxvk E+cQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id o1-20020a17090323c100b001b8c4168e20si1959235plh.58.2023.09.21.12.13.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 12:13:01 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 20F4781F4732; Thu, 21 Sep 2023 12:03:08 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229804AbjIUTCd (ORCPT + 28 others); Thu, 21 Sep 2023 15:02:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230024AbjIUTCI (ORCPT ); Thu, 21 Sep 2023 15:02:08 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 398848C63D; Thu, 21 Sep 2023 10:42:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E0CE1C15; Wed, 20 Sep 2023 20:37:21 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.32.120]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id DBFA83F59C; Wed, 20 Sep 2023 20:36:40 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V7 1/3] coresight: etm: Override TRCIDR3.CCITMIN on errata affected cpus Date: Thu, 21 Sep 2023 09:06:29 +0530 Message-Id: <20230921033631.1298723-2-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921033631.1298723-1-anshuman.khandual@arm.com> References: <20230921033631.1298723-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 21 Sep 2023 12:03:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777675620029210660 X-GMAIL-MSGID: 1777675620029210660 This work arounds errata 1490853 on Cortex-A76, and Neoverse-N1, errata 1491015 on Cortex-A77, errata 1502854 on Cortex-X1, and errata 1619801 on Neoverse-V1, based affected cpus, where software read for TRCIDR3.CCITMIN field in ETM gets an wrong value. If software uses the value returned by the TRCIDR3.CCITMIN register field, then it will limit the range which could be used for programming the ETM. In reality, the ETM could be programmed with a much smaller value than what is indicated by the TRCIDR3.CCITMIN field and still function correctly. If software reads the TRCIDR3.CCITMIN register field, corresponding to the instruction trace counting minimum threshold, observe the value 0x100 or a minimum cycle count threshold of 256. The correct value should be 0x4 or a minimum cycle count threshold of 4. This work arounds the problem via storing 4 in drvdata->ccitmin on affected systems where the TRCIDR3.CCITMIN has been 256, thus preserving cycle count threshold granularity. These errata information has been updated in arch/arm64/silicon-errata.rst, but without their corresponding configs because these have been implemented directly in the driver. Cc: Catalin Marinas Cc: Will Deacon Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: linux-doc@vger.kernel.org Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- Documentation/arch/arm64/silicon-errata.rst | 10 +++++ .../coresight/coresight-etm4x-core.c | 37 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index e96f057ea2a0..8f1be5da68b7 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -115,6 +115,10 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A76 | #1463225 | ARM64_ERRATUM_1463225 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A76 | #1490853 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A77 | #1491015 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | @@ -125,6 +129,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1 | #1502854 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | @@ -133,6 +139,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1349291 | N/A | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N1 | #1490853 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | @@ -141,6 +149,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2253138 | ARM64_ERRATUM_2253138 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V1 | #1619801 | N/A | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-600 | #1076982,1209401| N/A | diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 77b0271ce6eb..9619d9d0bbb1 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1150,6 +1150,41 @@ static void cpu_detect_trace_filtering(struct etmv4_drvdata *drvdata) drvdata->trfcr = trfcr; } +/* + * The following errata on applicable cpu ranges, affect the CCITMIN filed + * in TCRIDR3 register. Software read for the field returns 0x100 limiting + * the cycle threshold granularity, whereas the right value should have + * been 0x4, which is well supported in the hardware. + */ +static struct midr_range etm_wrong_ccitmin_cpus[] = { + /* Erratum #1490853 - Cortex-A76 */ + MIDR_RANGE(MIDR_CORTEX_A76, 0, 0, 4, 0), + /* Erratum #1490853 - Neoverse-N1 */ + MIDR_RANGE(MIDR_NEOVERSE_N1, 0, 0, 4, 0), + /* Erratum #1491015 - Cortex-A77 */ + MIDR_RANGE(MIDR_CORTEX_A77, 0, 0, 1, 0), + /* Erratum #1502854 - Cortex-X1 */ + MIDR_REV(MIDR_CORTEX_X1, 0, 0), + /* Erratum #1619801 - Neoverse-V1 */ + MIDR_REV(MIDR_NEOVERSE_V1, 0, 0), + {}, +}; + +static void etm4_fixup_wrong_ccitmin(struct etmv4_drvdata *drvdata) +{ + /* + * Erratum affected cpus will read 256 as the minimum + * instruction trace cycle counting threshold whereas + * the correct value should be 4 instead. Override the + * recorded value for 'drvdata->ccitmin' to workaround + * this problem. + */ + if (is_midr_in_range_list(read_cpuid_id(), etm_wrong_ccitmin_cpus)) { + if (drvdata->ccitmin == 256) + drvdata->ccitmin = 4; + } +} + static void etm4_init_arch_data(void *info) { u32 etmidr0; @@ -1214,6 +1249,8 @@ static void etm4_init_arch_data(void *info) etmidr3 = etm4x_relaxed_read32(csa, TRCIDR3); /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */ drvdata->ccitmin = FIELD_GET(TRCIDR3_CCITMIN_MASK, etmidr3); + etm4_fixup_wrong_ccitmin(drvdata); + /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */ drvdata->s_ex_level = FIELD_GET(TRCIDR3_EXLEVEL_S_MASK, etmidr3); drvdata->config.s_ex_level = drvdata->s_ex_level; From patchwork Thu Sep 21 03:36:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142999 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5205453vqi; Thu, 21 Sep 2023 16:27:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQ8+T11iB4KAiIpL2X1S/CJFn+0StbZBat+KNF7zUN9+jGEgvQGcSwGqsF1ajHY9QF/ca5 X-Received: by 2002:a17:903:120b:b0:1c3:1167:26e4 with SMTP id l11-20020a170903120b00b001c3116726e4mr7421420plh.60.1695338844018; Thu, 21 Sep 2023 16:27:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695338844; cv=none; d=google.com; s=arc-20160816; b=pioquunA/22E8kNWXq3ek9682l1rVwbJJH9/XLkak79Z9E0wFZ8Q056k1MpGl8CqyA ApQT2zsv/aq+n+EJ/Y+cqbRo1PNMFRVna6OinT2NeMVjX5U5X14cVz5E/5j5vB0Js7WY XcpWXDZKTDgCJgQFW0pvxfxgUIgI4NJdmiQiZvDgE0WOqoBApVqLqGBxirjLI2iAKmHB 53NsuTGTyOz2TbIHjns9psoUDllyZyj/aYO8wOEcLE+xb3RaCOA0k9Eufu5BRghTwWWH vn1skPZtnErcQYC+1qFSP5RE14bHcVWdvNPQJe92dT87XCyXsHhuPBx/7Z3IEN99Rj66 uezw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=REsqtnTUokhX1sLKj5chmGLWlYQw2oIn92SC+cp/CqY=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=vc7UgYumSE9pmCffzGJOmqfC/QFRlCfnFrui4rcyFAebO9VW9l5F81FNWbMmK1gCkN UYS4hQlM/18P52wFWiwDJ2OBPSDQkXXoNa/2Zn2m7NkBRXiCAl10c9ZWOM8syRTgSeDJ Bnr7IxF/glWQJzeByixzbn7SKQHOBIo0F+MsCc2byiItTBEugNnzTHINY5qyWmQK0txy ay6Tp70V1wrcrMkObmih5aBwWBIxH7T6VK0QujZmfhCZ6oMOJ1Kibc6tgnVyPHR7gThR ri5k+czk08zOfQk1WYkoeCMbsIttg9xLyYbW1n4JUkLnm9tgAJhFRaaiGzIxP9zHJEHv AdNA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id c7-20020a170903234700b001a6bb7b7a44si2608923plh.307.2023.09.21.16.27.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 16:27:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 54A9D8286E80; Thu, 21 Sep 2023 13:36:48 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232193AbjIUUgW (ORCPT + 29 others); Thu, 21 Sep 2023 16:36:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53982 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232425AbjIUUfG (ORCPT ); Thu, 21 Sep 2023 16:35:06 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3B0608C63E; Thu, 21 Sep 2023 10:42:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 765C5DA7; Wed, 20 Sep 2023 20:37:26 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.32.120]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 5C6CA3F59C; Wed, 20 Sep 2023 20:36:45 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V7 2/3] coresight: etm: Make cycle count threshold user configurable Date: Thu, 21 Sep 2023 09:06:30 +0530 Message-Id: <20230921033631.1298723-3-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921033631.1298723-1-anshuman.khandual@arm.com> References: <20230921033631.1298723-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Thu, 21 Sep 2023 13:36:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777691623578357041 X-GMAIL-MSGID: 1777691623578357041 When cycle counting is enabled, we use a default threshold value i.e 0x100 for the instruction trace cycle counting. This patch makes the cycle threshold user configurable via perf event attributes( 'cc_threshold' => event->attr.config3[11:0] ), falling back to the current default if unspecified. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Leo Yan Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Mike Leach Signed-off-by: Anshuman Khandual --- drivers/hwtracing/coresight/coresight-etm-perf.c | 2 ++ drivers/hwtracing/coresight/coresight-etm4x-core.c | 9 +++++++-- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c index 5ca6278baff4..09f75dffae60 100644 --- a/drivers/hwtracing/coresight/coresight-etm-perf.c +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c @@ -68,6 +68,7 @@ PMU_FORMAT_ATTR(preset, "config:0-3"); PMU_FORMAT_ATTR(sinkid, "config2:0-31"); /* config ID - set if a system configuration is selected */ PMU_FORMAT_ATTR(configid, "config2:32-63"); +PMU_FORMAT_ATTR(cc_threshold, "config3:0-11"); /* @@ -101,6 +102,7 @@ static struct attribute *etm_config_formats_attr[] = { &format_attr_preset.attr, &format_attr_configid.attr, &format_attr_branch_broadcast.attr, + &format_attr_cc_threshold.attr, NULL, }; diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 9619d9d0bbb1..5b6a878a2ac5 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -644,7 +644,7 @@ static int etm4_parse_event_config(struct coresight_device *csdev, struct etmv4_config *config = &drvdata->config; struct perf_event_attr *attr = &event->attr; unsigned long cfg_hash; - int preset; + int preset, cc_threshold; /* Clear configuration from previous run */ memset(config, 0, sizeof(struct etmv4_config)); @@ -667,7 +667,12 @@ static int etm4_parse_event_config(struct coresight_device *csdev, if (attr->config & BIT(ETM_OPT_CYCACC)) { config->cfg |= TRCCONFIGR_CCI; /* TRM: Must program this for cycacc to work */ - config->ccctlr = ETM_CYC_THRESHOLD_DEFAULT; + cc_threshold = attr->config3 & ETM_CYC_THRESHOLD_MASK; + if (!cc_threshold) + cc_threshold = ETM_CYC_THRESHOLD_DEFAULT; + if (cc_threshold < drvdata->ccitmin) + cc_threshold = drvdata->ccitmin; + config->ccctlr = cc_threshold; } if (attr->config & BIT(ETM_OPT_TS)) { /* From patchwork Thu Sep 21 03:36:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anshuman Khandual X-Patchwork-Id: 142855 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp5084988vqi; Thu, 21 Sep 2023 12:25:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVFUL21aCTWoN89IScozvHF1F5P6HNBvom8hXj+BUhGx3cfNR9iQ2W/Elh0TD1rjQzg5pk X-Received: by 2002:a05:6300:8083:b0:15c:b7ba:ebda with SMTP id ap3-20020a056300808300b0015cb7baebdamr6104509pzc.55.1695324307524; Thu, 21 Sep 2023 12:25:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695324307; cv=none; d=google.com; s=arc-20160816; b=FygrOO3Y9faBp9oJzDc6gPZbH5JM5AnSBpLqfwQXWXQoyKZ4eRsBtft4moZ+Y76Qh6 /0OWTjzmsniQGYhIXl8i2ESfhYN+0zHrBy00u7Gd2GrcrDMNeIgiN655sMzIwX704iXx As59aYxCIaY+AdHMZg4y/2pXpNRj1Lz15wEbYj3Vkm/5nDkwJH8bmRmw+SDtM1C4/brY C8wBBz6D8ysVx9lANMZc2mCo36f+VSNzhbRUNbpxHPQQ+cxmFuj/FnfeV2qNUz9w0sB3 RTh1d0nwdkdFf+lTZPE676gFeZcVoNVkBB0cUA4y4uQb8iv7NazJMh8OfH13P8kGoxOI EWWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=/ABFvXitoUhGgvKWgVLSjE34Xutdrpxjmzw+8l/wgFw=; fh=1B1+mkCYVeZZz1DAsIIoOA2jU5pSNu/8Q01YDfzUzC8=; b=Yq4X7SNSiW1W3G0HQTgyYZHs+aa4T3Z/0wZVaVV8vErK5qd2vx69x8b7VtYEhEtbog Vu3uRH8F/BUoYb2xPLYHBBprNywQZ1+6MSknebaj5Jv8jbk5gKzk8mGWMq59I+WctTBa 8uQTQmkCqIbeVPGus4Zvgt1rwGsM+8u+z8nF4z+62d1Zr1XbpDEQgQ3N6KpE2xIRsDoH x6omOpsH7Mlsj8O3lww5CuWf+rcFvZZVECVKU2+zqpoNmIE0MlRv/p0wljh5+m+O6jLn yCXGzLFjnyL9//T9Obq0LrUabU6tp4GXKmgqcnT4iUj8IzrtxVkbcZzb/CypF393dQ23 ee7A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id x10-20020a170902a38a00b001c5db1e47c3si1333112pla.553.2023.09.21.12.25.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 12:25:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 5C78281B94EB; Thu, 21 Sep 2023 12:02:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229867AbjIUTCo (ORCPT + 28 others); Thu, 21 Sep 2023 15:02:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjIUTCJ (ORCPT ); Thu, 21 Sep 2023 15:02:09 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 33B448C63C; Thu, 21 Sep 2023 10:42:37 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2327C1007; Wed, 20 Sep 2023 20:37:31 -0700 (PDT) Received: from a077893.arm.com (unknown [10.163.32.120]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id E63313F59C; Wed, 20 Sep 2023 20:36:49 -0700 (PDT) From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org, suzuki.poulose@arm.com Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Mike Leach , James Clark , Leo Yan , Jonathan Corbet , linux-doc@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org Subject: [PATCH V7 3/3] Documentation: coresight: Add cc_threshold tunable Date: Thu, 21 Sep 2023 09:06:31 +0530 Message-Id: <20230921033631.1298723-4-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230921033631.1298723-1-anshuman.khandual@arm.com> References: <20230921033631.1298723-1-anshuman.khandual@arm.com> MIME-Version: 1.0 X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00,RCVD_IN_DNSWL_MED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Thu, 21 Sep 2023 12:02:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777676381089492704 X-GMAIL-MSGID: 1777676381089492704 This updates config option to include 'cc_threshold' tunable value. Cc: Suzuki K Poulose Cc: Mike Leach Cc: James Clark Cc: Jonathan Corbet Cc: coresight@lists.linaro.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed by: Mike Leach Signed-off-by: Anshuman Khandual --- Documentation/trace/coresight/coresight.rst | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/trace/coresight/coresight.rst b/Documentation/trace/coresight/coresight.rst index 4a71ea6cb390..ce55adb80b82 100644 --- a/Documentation/trace/coresight/coresight.rst +++ b/Documentation/trace/coresight/coresight.rst @@ -624,6 +624,10 @@ They are also listed in the folder /sys/bus/event_source/devices/cs_etm/format/ * - timestamp - Session local version of the system wide setting: :ref:`ETMv4_MODE_TIMESTAMP ` + * - cc_threshold + - Cycle count threshold value. If nothing is provided here or the provided value is 0, then the + default value i.e 0x100 will be used. If provided value is less than minimum cycles threshold + value, as indicated via TRCIDR3.CCITMIN, then the minimum value will be used instead. How to use the STM module -------------------------