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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j13-20020aa7ca4d000000b00532e95992a5si879571edt.555.2023.09.21.02.51.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Sep 2023 02:51:10 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id B63F73857009 for ; Thu, 21 Sep 2023 09:51:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id 121A73858D39 for ; Thu, 21 Sep 2023 09:50:34 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 121A73858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp91t1695289829ti65ydab Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 21 Sep 2023 17:50:28 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: W+onFc5Tw4MEfliNbA0SWUEZsY1mZkAxnad5reLsIg/L7CBis8paf9JtmrP0k XO/2XUPABXVmG4kNT0ofBKgdsjtm/347CJsG5/stsXEn3KXSDXyewV2DN7eUe7mcu+5Emc2 y/131vWZVCyURYVCWDC1xOYM3fSPTog0La0P6e5qmvhAVXYo748Kh0xKqu1DMaLqzi2h/c6 dXWy2hNt7WLAcU8wPfL3TDvPY3llx8lBl6+Q9HX+XnFMxGcjEMIV8nsocHgBxE1kgQdBx7Q +/+xr7X26Zf8ULrT8Ew6Hl4UfXMPtnfYpN+OW4tMuSHyHcfR3hldsvePn2MUyp8U3zMFdpf fkOXm1hCh78LzFK6T6ClzDJZRuiiz7WcOXI16XhQlcSEjB+19PBjXQBTa8XmRKc8PErRMiw Jwe0aoF7DpY= X-QQ-GoodBg: 2 X-BIZMAIL-ID: 5025867613353580315 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH V2] RISC-V: Adjusting the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions Date: Thu, 21 Sep 2023 17:50:27 +0800 Message-Id: <20230921095027.143005-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777640271139923104 X-GMAIL-MSGID: 1777640271139923104 V2 Change: Use Robin's comments. This patch adjusts the comments of the emit_vlmax_insn/emit_vlmax_insn_lra/emit_nonvlmax_insn functions. The purpose of the adjustment is to make it clear that vlmax here is not VLMAX as defined inside the RVV ISA. This is because this function is used by RVV mode (e.g. RVVM1SImode) in addition to VLS mode (V16QI). For RVV mode, it means the same thing, for VLS mode, it indicates setting the vl to the number of units of the mode. Changed the comment because I didn't think of a better name. If there is a suitable name, feel free to discuss it. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_vlmax_insn): Adjust comments. (emit_nonvlmax_insn): Adjust comments. (emit_vlmax_insn_lra): Adjust comments. Co-Authored-By: Robin Dapp --- gcc/config/riscv/riscv-v.cc | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) -- 2.36.3 diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 64a71a128d4..bb08289d39a 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -347,33 +347,42 @@ private: expand_operand m_ops[MAX_OPERANDS]; }; -/* Emit RVV insn which vl is VLMAX. - This function can only be used before LRA pass or - for VLS_AVL_IMM modes. */ +/* Emit an RVV insn with a vector length that equals the number of units of the + vector mode. For VLA modes this corresponds to VLMAX. + + Unless the vector length can be encoded in the vsetivl[i] instruction this + function must only be used as long as we can create pseudo registers. This is + because it will set a pseudo register to VLMAX using vsetvl and use this as + definition for the vector length. */ void emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops) { insn_expander e (insn_flags, true); + gcc_assert (can_create_pseudo_p () || const_vlmax_p (e.get_vtype_mode (ops))); + e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL. */ +/* Like emit_vlmax_insn but must only be used when we cannot create pseudo + registers anymore. This function, however, takes a predefined vector length + from the value in VL. */ void -emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - insn_expander e (insn_flags, false); + gcc_assert (!can_create_pseudo_p ()); + + insn_expander e (insn_flags, true); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); } -/* Emit RVV insn which vl is VL but the AVL_TYPE insn attr is VLMAX. - This function used after LRA pass that cann't create pseudo register. */ +/* Emit an RVV insn with a predefined vector length. Contrary to + emit_vlmax_insn the instruction's vector length is not deduced from its mode + but taken from the value in VL. */ void -emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) +emit_nonvlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl) { - gcc_assert (!can_create_pseudo_p ()); - - insn_expander e (insn_flags, true); + insn_expander e (insn_flags, false); e.set_vl (vl); e.emit_insn ((enum insn_code) icode, ops); }