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Wed, 20 Sep 2023 12:11:18 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Dinh Nguyen Cc: Serge Semin , Punnaiah Choudary Kalluri , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Sherry Sun , Borislav Petkov Subject: [PATCH v4 01/20] EDAC/synopsys: Fix ECC status data and IRQ disable race condition Date: Wed, 20 Sep 2023 22:10:25 +0300 Message-ID: <20230920191059.28395-2-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:11:43 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777613647702969221 X-GMAIL-MSGID: 1777613647702969221 The race condition around the ECCCLR register access happens in the IRQ disable method called in the device remove() procedure and in the ECC IRQ handler: 1. Enable IRQ: a. ECCCLR = EN_CE | EN_UE 2. Disable IRQ: a. ECCCLR = 0 3. IRQ handler: a. ECCCLR = CLR_CE | CLR_CE_CNT | CLR_CE | CLR_CE_CNT b. ECCCLR = 0 c. ECCCLR = EN_CE | EN_UE So if the IRQ disabling procedure is called concurrently with the IRQ handler method the IRQ might be actually left enabled due to the statement 3c. The root cause of the problem is that ECCCLR register (which since v3.10a has been called as ECCCTL) has intermixed ECC status data clear flags and the IRQ enable/disable flags. Thus the IRQ disabling (clear EN flags) and handling (write 1 to clear ECC status data) procedures must be serialised around the ECCCTL register modification to prevent the race. So fix the problem described above by adding the spin-lock around the ECCCLR modifications and preventing the IRQ-handler from modifying the IRQs enable flags (there is no point in disabling the IRQ and then re-enabling it again within a single IRQ handler call, see the statements 3a/3b and 3c above). Fixes: f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR") Signed-off-by: Serge Semin --- Cc: Sherry Sun Changelog v4: - This is a new patch detached from [PATCH v3 01/17] EDAC/synopsys: Fix native uMCTL2 IRQs handling procedure - Rename lock to reglock (Borislav) --- drivers/edac/synopsys_edac.c | 50 ++++++++++++++++++++++++++---------- 1 file changed, 37 insertions(+), 13 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index f7d37c282819..014a2176c2c1 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -300,6 +301,7 @@ struct synps_ecc_status { /** * struct synps_edac_priv - DDR memory controller private instance data. * @baseaddr: Base address of the DDR controller. + * @reglock: Concurrent CSRs access lock. * @message: Buffer for framing the event specific info. * @stat: ECC status information. * @p_data: Platform data. @@ -314,6 +316,7 @@ struct synps_ecc_status { */ struct synps_edac_priv { void __iomem *baseaddr; + spinlock_t reglock; char message[SYNPS_EDAC_MSG_SIZE]; struct synps_ecc_status stat; const struct synps_platform_data *p_data; @@ -409,7 +412,8 @@ static int zynq_get_error_info(struct synps_edac_priv *priv) static int zynqmp_get_error_info(struct synps_edac_priv *priv) { struct synps_ecc_status *p; - u32 regval, clearval = 0; + u32 regval, clearval; + unsigned long flags; void __iomem *base; base = priv->baseaddr; @@ -453,10 +457,14 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); p->ueinfo.data = readl(base + ECC_UESYND0_OFST); out: - clearval = ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT; - clearval |= ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; + spin_lock_irqsave(&priv->reglock, flags); + + clearval = readl(base + ECC_CLR_OFST) | + ECC_CTRL_CLR_CE_ERR | ECC_CTRL_CLR_CE_ERRCNT | + ECC_CTRL_CLR_UE_ERR | ECC_CTRL_CLR_UE_ERRCNT; writel(clearval, base + ECC_CLR_OFST); - writel(0x0, base + ECC_CLR_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); return 0; } @@ -516,24 +524,41 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) static void enable_intr(struct synps_edac_priv *priv) { + unsigned long flags; + /* Enable UE/CE Interrupts */ - if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) - writel(DDR_UE_MASK | DDR_CE_MASK, - priv->baseaddr + ECC_CLR_OFST); - else + if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_EN_OFST); + return; + } + + spin_lock_irqsave(&priv->reglock, flags); + + writel(DDR_UE_MASK | DDR_CE_MASK, + priv->baseaddr + ECC_CLR_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); } static void disable_intr(struct synps_edac_priv *priv) { + unsigned long flags; + /* Disable UE/CE Interrupts */ - if (priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR) - writel(0x0, priv->baseaddr + ECC_CLR_OFST); - else + if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_DB_OFST); + + return; + } + + spin_lock_irqsave(&priv->reglock, flags); + + writel(0, priv->baseaddr + ECC_CLR_OFST); + + spin_unlock_irqrestore(&priv->reglock, flags); } /** @@ -577,8 +602,6 @@ static irqreturn_t intr_handler(int irq, void *dev_id) /* v3.0 of the controller does not have this register */ if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); - else - enable_intr(priv); return IRQ_HANDLED; } @@ -1360,6 +1383,7 @@ static int mc_probe(struct platform_device *pdev) priv = mci->pvt_info; priv->baseaddr = baseaddr; priv->p_data = p_data; + spin_lock_init(&priv->reglock); mc_init(mci, pdev); From patchwork Wed Sep 20 19:10:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142595 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4416945vqi; Wed, 20 Sep 2023 13:50:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEFGK3mKLhJU80gOw3kYfsI+6kVM7wN7clGxtDaJKu5MtmqORxHLgk/eGQ2RUkPr3ugdDo5 X-Received: by 2002:a05:6358:430c:b0:139:5a46:ea7e with SMTP id r12-20020a056358430c00b001395a46ea7emr4120809rwc.28.1695243017432; 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Wed, 20 Sep 2023 12:11:21 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Manish Narani Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov Subject: [PATCH v4 02/20] EDAC/synopsys: Fix generic device type detection procedure Date: Wed, 20 Sep 2023 22:10:26 +0300 Message-ID: <20230920191059.28395-3-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777591142294107167 X-GMAIL-MSGID: 1777591142294107167 First of all the enum dev_type constants describe the memory DRAM chips used at the stick, not the entire DQ-bus width (see the enumeration kdoc for details). So what is returned from the zynqmp_get_dtype() function and then specified to the dimm_info->dtype field is definitely incorrect. Secondly the DRAM chips type has nothing to do with the data bus width specified in the MSTR.data_bus_width CSR field. That CSR field just determines the part of the whole DQ-bus currently used to access the data from the all DRAM memory chips. So it doesn't indicate the individual chips type. Thirdly the DRAM chips type can be determined only in case of the DDR4 protocol by means of the MSTR.device_config field state (it is supposed to be set by the system firmware). Finally the DW uMCTL2 DDRC ECC capability doesn't depend on the memory chips type. Moreover it doesn't depend on the utilized data bus width in runtime either. The IP-core reference manual says in [1,2] that the ECC support can't be enabled during the IP-core synthesizes for the DRAM data bus widths other than 16, 32 or 64. At the same time the bus width mode (MSTR.data_bus_width) doesn't change the ECC feature availability. Thus it was wrong to determine the ECC state with respect to the DQ-bus width mode. Fix all of the mistakes described above in the zynqmp_get_dtype() and zynqmp_get_ecc_state() methods: specify actual DRAM chips data width only for the DDR4 protocol and return that it's UNKNOWN in the rest of the cases; determine ECC availability by the ECCCFG0.ecc_mode field state only (that field can't be modified anyway if the IP-core was synthesized with no ECC support). [1] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p. 421. [2] DesignWare® Cores Enhanced Universal DDR Memory Controller (uMCTL2) Databook, Version 3.91a, October 2020, p. 633. Fixes: b500b4a029d5 ("EDAC, synopsys: Add ECC support for ZynqMP DDR controller") Signed-off-by: Serge Semin --- Changelog v2: - Include "linux/bitfield.h" header file to get the FIELD_GET macro definition. (@tbot) --- drivers/edac/synopsys_edac.c | 49 +++++++++++++++--------------------- 1 file changed, 20 insertions(+), 29 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 014a2176c2c1..b463bd802961 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -675,26 +675,25 @@ static enum dev_type zynq_get_dtype(const void __iomem *base) */ static enum dev_type zynqmp_get_dtype(const void __iomem *base) { - enum dev_type dt; - u32 width; - - width = readl(base + CTRL_OFST); - width = (width & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; - switch (width) { - case DDRCTL_EWDTH_16: - dt = DEV_X2; - break; - case DDRCTL_EWDTH_32: - dt = DEV_X4; - break; - case DDRCTL_EWDTH_64: - dt = DEV_X8; - break; - default: - dt = DEV_UNKNOWN; + u32 regval; + + regval = readl(base + CTRL_OFST); + if (!(regval & MEM_TYPE_DDR4)) + return DEV_UNKNOWN; + + regval = (regval & DDRC_MSTR_CFG_MASK) >> DDRC_MSTR_CFG_SHIFT; + switch (regval) { + case DDRC_MSTR_CFG_X4_MASK: + return DEV_X4; + case DDRC_MSTR_CFG_X8_MASK: + return DEV_X8; + case DDRC_MSTR_CFG_X16_MASK: + return DEV_X16; + case DDRC_MSTR_CFG_X32_MASK: + return DEV_X32; } - return dt; + return DEV_UNKNOWN; } /** @@ -731,19 +730,11 @@ static bool zynq_get_ecc_state(void __iomem *base) */ static bool zynqmp_get_ecc_state(void __iomem *base) { - enum dev_type dt; - u32 ecctype; + u32 regval; - dt = zynqmp_get_dtype(base); - if (dt == DEV_UNKNOWN) - return false; + regval = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; - ecctype = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; - if ((ecctype == SCRUB_MODE_SECDED) && - ((dt == DEV_X2) || (dt == DEV_X4) || (dt == DEV_X8))) - return true; - - return false; + return (regval == SCRUB_MODE_SECDED); } /** From patchwork Wed Sep 20 19:10:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142634 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4481760vqi; Wed, 20 Sep 2023 16:04:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEasGBX7jSKuLmEtWwgfjGnLULg9Z861M1zarq4GBalAR9fe4ud4FbBecD8fNbkp8lxuaT2 X-Received: by 2002:a05:6870:d62c:b0:1d5:9b10:f777 with SMTP id a44-20020a056870d62c00b001d59b10f777mr4140845oaq.12.1695251071815; Wed, 20 Sep 2023 16:04:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695251071; cv=none; d=google.com; s=arc-20160816; b=ow0k8PvjUNbASLn9ydk4gaLhpLhAPgTao0st44vmWeHZZAT1Wauy050w0EDUV72kpJ Nck/sQCfx4guz/B/+LtpX6LgB0EKWpIWWAgYJWyz7YGjQHQbRjt1C4qGbG0eCrUHOcgJ yWi5F2duhepQ3uZp/fc/ZLlQ6X7IMUl+q4934Dtd3JVAhncGYDcF2tTiKWyArnYVhUbb 2GNP3gzZItqaYjr0VpFm9bqJ/uPH95Ke6SVew8S6oFNkzafEcQhluXo4F6NWU58M1z0n 5FKVgrwdFsaD0tswokZTkqREtiqXvmhx8sfeR0hKejDYTI/+zDQU6LxsfhQSGNdWKZqO 0LAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZnR6l+vYOh9Csf9eBwgQHTo/sUEkvBg0hJ7+UGZ8t70=; fh=8lYK+GvxwtV16oEYZuWpi1Zfk0P5EQ9jNM/pSuPN5T0=; b=OfWcZMHqB06LDc8cL+uAe5aH0ytiEraxhaDWQfUrvuXJTaWHpAQI+0ed3J4/OnDAcz 7UNJ612zHzP4bGaLBR3HI0kB8BQP3f85ZIMFSEmEAzqKA7YWKnh1uVBYNQHc/3WblrQO OEcr7jIe3jyugQcMBF9/r260IBwWdweig4LdS0Kvbti8iUw8NmhGMauH4WyzeoIoYY+7 /ZbNp3hBSaNTxLhnpCunC49xtGCeltDa50sHitTklX225GlsG8ygn/o+BxH1PMWIt1c8 OyMVuQyTbXvB2eXRW9jLVc1ZSqu9B6REN/U0DFdwRVN4i1tvwgX8b+uIxIR9hLAq1xP0 gD5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=TNMK6pnI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from agentk.vger.email (agentk.vger.email. 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Instead the driver erroneously initializes it with the SCRUB_HW_SRC flag ID. It's definitely wrong, though it hasn't caused any problem so far since the structure field isn't used by the EDAC core. Fix it anyway by using the SCRUB_FLAG_HW_SRC macro to initialize the field. Fixes: ae9b56e3996d ("EDAC, synps: Add EDAC support for zynq ddr ecc controller") Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index b463bd802961..65790097beb2 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -856,7 +856,7 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) /* Initialize controller capabilities and configuration */ mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; - mci->scrub_cap = SCRUB_HW_SRC; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; mci->scrub_mode = SCRUB_NONE; mci->edac_cap = EDAC_FLAG_SECDED; From patchwork Wed Sep 20 19:10:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142585 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4401880vqi; Wed, 20 Sep 2023 13:19:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHvVTQlwVx4pZyre0zpunFr9uXCegHxrhioNH2E8yvQkfcpWx81lLcXPqo7r9T3ABltmj2A X-Received: by 2002:a05:6a21:3e04:b0:153:3d8f:cb29 with SMTP id bk4-20020a056a213e0400b001533d8fcb29mr3539307pzc.24.1695241187990; Wed, 20 Sep 2023 13:19:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695241187; cv=none; d=google.com; s=arc-20160816; b=dOjiaU6b1OxbiUq4uv8nqGmzi/Jp6iVgM2GbcA5zcATzEYLyaoQCD8keMuOYJPgtFF Ne448oHqvGAsjtw+GYwG5rAqNOWjjDnKdyzQDtuiAMUkZ5asszkWFH9swtOp2jSSUro3 RbNbGDdigl0rngqgFFEwD40WFf8jkhmF3u/gWiyQOaWE8F71KlX679G+f6Aecm6jjIbb K4LipWimHQOw+u0Df4QloxX+F8rsRIyzTHQC8HaDNVu/tgpzjgJfJCjMMJzlvKlTsNF1 JeHFt6wFyLgrQ4t5TFn1ST7zMRPiQ7tQCAbZJWkBNGr+h8peVJ/KS99R+WQN5cWIWQoL ndGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CUQlNWBQLKx5ke9/fjvP01zDeVt7MOvvAIgh8fT+a2g=; fh=y0DcfaBYI5t0VTARY5hXWJ4aKoJbGJYwhgLbGYez5lY=; b=VdaWQ6uvr2YMWvQoXYnn0V0rLXBim4ihh0rc5U1Syxe0gw1h+S6AH/sdWmtCYx3lIf XdVs3a8IB3yAj3ffXv/y/9A7km4RdM8rnbMEcIqp5RbDlf2C2qKZYirdEDNdjDmZCQqX +YXRP1Ax7ea0oH9BAGC/Zs+4YK1II8Rsx/lkbI72WHEIJv2jS+47oMufUJl7xtusHDMW FHMhS0z7S+sh0uYVUiUnT/g+BwVt0cgRGaFGTsTGAJa+eC5dyjhBNH1JjKHJKnkj4RxP 4/yeAu6sdkoPfX14kk/gT70ozesGqPwRlMIPLkN+q5HlY6dPzUQOwUrUKy+yECpCWFtL NjHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=E5P6atyA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id q12-20020a056a00150c00b0068e405d9217si13169840pfu.302.2023.09.20.13.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 13:19:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=E5P6atyA; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 5E8B381DD7C6; Wed, 20 Sep 2023 12:11:45 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229943AbjITTLo (ORCPT + 27 others); Wed, 20 Sep 2023 15:11:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229905AbjITTLi (ORCPT ); Wed, 20 Sep 2023 15:11:38 -0400 Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A33F7E8; Wed, 20 Sep 2023 12:11:31 -0700 (PDT) Received: by mail-lj1-x236.google.com with SMTP id 38308e7fff4ca-2c008042211so2178041fa.2; Wed, 20 Sep 2023 12:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695237089; x=1695841889; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CUQlNWBQLKx5ke9/fjvP01zDeVt7MOvvAIgh8fT+a2g=; b=E5P6atyAY2PxZV1y4B8jJZPClW1EaWXyGDolN7Mv5paI5asZJvsMtZ/Yk4QBDYU4yA /uDkfiqCZWmQygprWiQYTSiySaYsIB+0tIKsa/qsvhbvdg3En2XL+SMA/LY3oNC6Al3f nTm78wpW8AjOKimkXOO2UzTfR6/iwMTpvypzSAzvZ1KBFw6FAJSaPtN5YxGO8/Ze4OEx +t96yma3uGrykGKJP6uHagbxNB0JU3+KKBIBAk9mMd9ZoYlJOreEtaYusyE7cdUpdqcS jeiwn6SbLyOOoBAoPBVPSllLnsVf2A5RW20juXpnNoVUIMwophVcx+ICcTRxZGoLgmIC 7LxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695237089; x=1695841889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CUQlNWBQLKx5ke9/fjvP01zDeVt7MOvvAIgh8fT+a2g=; b=ql5591myqz3mD92udVID9uuNHzbEYn5e5Ac2dX9FN6xPiqKK7x40WNi5D2N9ABx+Ux kvDwrXyB7q7cQApw8cHFK73tGLyWKvPIrEcJqEtSgZAfunRDXfk005VhCOQOhPuGkIlE DFsTQlhAh6xEwup7W7w7pehOWI9YdxaWmu/C8I0Pur4QgHq123T9hDOu+xSvpXJ2WbLl owFopB4/mx7SwdCC8BKUajg+qGKCT2LMp2yjG3BZBsQe4KDGKD+iF8A/CUoM0XMwdrUn K1zR6Nlcb/oTLCcW4wVbnofYzltitUuR5bKM2jY9JyQl3R8M4ZOwkjGP6HV9RFU+YDbb OOLg== X-Gm-Message-State: AOJu0YzyznBgwVHiVMOzJWNfEXfCVe0Vb2+4Ex8M6iSCM7+hBtgV6cGM /Mn+Ky8PZdO+l/bSpmXpiL0= X-Received: by 2002:ac2:5bc7:0:b0:502:a4f4:ced9 with SMTP id u7-20020ac25bc7000000b00502a4f4ced9mr2972681lfn.62.1695237089243; Wed, 20 Sep 2023 12:11:29 -0700 (PDT) Received: from localhost ([178.176.81.142]) by smtp.gmail.com with ESMTPSA id h10-20020ac25d6a000000b004f85d80ca64sm2800653lft.221.2023.09.20.12.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:11:28 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Manish Narani Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Borislav Petkov Subject: [PATCH v4 04/20] EDAC/synopsys: Drop erroneous ADDRMAP4.addrmap_col_b10 parse Date: Wed, 20 Sep 2023 22:10:28 +0300 Message-ID: <20230920191059.28395-5-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:11:45 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777589224104551191 X-GMAIL-MSGID: 1777589224104551191 Currently the ADDRMAP4.addrmap_col_b10 field gets to be parsed in case of the LPDDR3 memory and Quarter DQ bus width mode. It's wrong since that field is marked as unused for that mode in all the available DW uMCTL2 DDRC releases (up to IP-core v3.91a). Most likely the field parsing was added by mistake as a result of the copy-paste from the Half DQ bus width mode part of the same function. Even though the field is supposed to be always set to the UNUSED value (0x1F) drop parsing it anyway so to simplify the setup_column_address_map() method a tiny bit. Fixes: 1a81361f75d8 ("EDAC, synopsys: Add Error Injection support for ZynqMP DDR controller") Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 65790097beb2..308da6f82d3d 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1237,10 +1237,6 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + COL_B9_BASE); - priv->col_shift[13] = ((addrmap[4] & - COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : - ((addrmap[4] & COL_MAX_VAL_MASK) + - COL_B10_BASE); } else { priv->col_shift[11] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : From patchwork Wed Sep 20 19:10:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4487974vqi; Wed, 20 Sep 2023 16:16:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE/F3sUQkGLUocZyb1Qh+x4/MpcJA5qjYKJlh9tBTskbbqclnZipCnJViSCvqDZNVv2hApw X-Received: by 2002:a17:902:ecc8:b0:1c3:432f:9f69 with SMTP id a8-20020a170902ecc800b001c3432f9f69mr6213837plh.23.1695251785199; Wed, 20 Sep 2023 16:16:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695251785; cv=none; d=google.com; s=arc-20160816; b=Er8wQuQV19nQU/jS0KMJklBkMOBxGiYIcX0bpSIM8aLUb8fELcws+Gt+pPpFRqqcBX a7SRpn+emIOUH9G7Oh6iOwDwF/SiVrDHq9s/Cb2LUzdTx0uPXdicW4XGGza95Q+NfhrT 4CDa1PUdAxVtYKIoNjrsCMgsad+9JzUK0Zq8PhJDEE/H8QfDuAfuXRdcn3zKtAjNaBog VYSvRIrklRXwWAu6gAGQ4jKP1fqOXJnKT5ZywX6Rcqiaeq2XiMlU18lP7VvQqgKBFORL 73VXEkGmpi6oOndKC0+/Pm1I2k7o4Y2LJvRnDwgyXFRZrqxMjFpgaxzFxHqCtXXe1exQ jiNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=osBqvthiVpODVt2c1wzVUJqaUOTaV5YdFAQXjwCgrOg=; fh=RJG5TS5hvLciLIcK4vCQlwfT5qo5cdcunmEMyeiOMJY=; b=C3QE0q9c7DvgQU2000XmzIBpVX382pjhApsl5J66sAg8hCfU7hRFkblb+S71QPnxuj 5qDdeLrCZZ/m4+B+qsf/qLskAMIY/eqj3CxpSIR+Is4e+bLDg5yd4QB9RdkrDFyv+eNt zvXredexASr61qzsLXE03Vs2sIrWXtnEcnJK1L44jboYOLbaO5HdjJmTY/N1iWjEpgVw BC4sZ9dgXnxJl3gEizGbB5x9T1jxFX2H4Yy4zYW2MyACHynkxiLTaDMgb+FBF97x1hV6 AXFWX1CmkwYJM5fcsr6OkfbnOnXXRkSNs1jrMw8NwNYEPfJni6JyTOucnk+9oEWuERaq sV7w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=efQrtZSo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from morse.vger.email (morse.vger.email. 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Wed, 20 Sep 2023 12:11:31 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Shubhrajyoti Datta Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, Shubhrajyoti Datta , Borislav Petkov Subject: [PATCH v4 05/20] EDAC/synopsys: Fix reading errors count before ECC status Date: Wed, 20 Sep 2023 22:10:29 +0300 Message-ID: <20230920191059.28395-6-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:11:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777600335707917581 X-GMAIL-MSGID: 1777600335707917581 Aside with fixing the errors count CSR usage the commit e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct register") all of the sudden has also changed the order of the errors status check procedure. So now the errors handler method first reads the number of CE and UE and only then makes sure that any of these errors have actually happened. It doesn't make sense. Fix that by getting back the correct procedures order: first check the ECC status, then read the number of errors. Fixes: e2932d1f6f05 ("EDAC/synopsys: Read the error count from the correct register") Signed-off-by: Serge Semin Reviewed-by: Shubhrajyoti Datta --- drivers/edac/synopsys_edac.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 308da6f82d3d..fff4b07ff6ac 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -419,18 +419,18 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) base = priv->baseaddr; p = &priv->stat; - regval = readl(base + ECC_ERRCNT_OFST); - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; - if (!p->ce_cnt) - goto ue_err; - regval = readl(base + ECC_STAT_OFST); if (!regval) return 1; p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); + regval = readl(base + ECC_ERRCNT_OFST); + p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; + p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; + if (!p->ce_cnt) + goto ue_err; + regval = readl(base + ECC_CEADDR0_OFST); p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); regval = readl(base + ECC_CEADDR1_OFST); From patchwork Wed Sep 20 19:10:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142560 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4367654vqi; Wed, 20 Sep 2023 12:14:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFvzt3jvMCo92EIUWuyPLCUsFCvqYME/s2O3gxQiLgDMSmFfQDTQLkT8nlAH1oQzt+eyue8 X-Received: by 2002:a17:90a:3188:b0:274:6cc9:ec6d with SMTP id j8-20020a17090a318800b002746cc9ec6dmr3315068pjb.44.1695237286991; Wed, 20 Sep 2023 12:14:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695237286; cv=none; d=google.com; s=arc-20160816; b=o0Rd25wqmipy7TP1sMW8QL0t4JQnnSzEyr4zDvQPRKoxiOF4QsxWKH/FNkr3dobCvz NUb/hycYhRZ4q/ueA2kACzc+LH1yvR4s6MsVGnZ9XtMMuoH1Mh6Pi5G+HjPH4SieJ4j2 HImg0ddBmaFr+IJeTukb2EGxa7SJNs2zVIO5zJsN1/8u7lJzqMC9/ydVGAst6mH367F8 nWpX8pSOskwr5Kf/lVGAwvxtIbdNOZZpgtm6pf7UylllkoIDNDvlUjWZpFTh3uWrHGgV NfwPfcWchLDGcLRjLud0+Bgtq6j8NtmzOHTnAUMTIkrH6KgrHN8ysQlMdw5iW+zMEns/ dIDg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g/PgPh5sPZyXwcbz4sY57Qw/OU8U8ZUgcMaSG4iKyvE=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=yZ7e7+libVv71kDu2MAFPlMPM/S0afsvEMTV90X3XfOdZaKy50g9qLzN05v+SfK7Jb 1eUmjpEDlqb113Rq8M+GRXsawsuwmTmxAcT+yuk6sgvOBwwGsJ+16iw/DIF+orlsMCNq P56dEKJD1mo2G1P8xhuGy+C/Cw1YTQ8yE4jekNPPmVdPh17qO44ckjkOLbylrr7DbPib mxqK5gjQ6BnD7Jd5qIE+YZe1E4/pxr0U9a7+w7R14nx/BoBhODQ37aCEIUvOJx0L/OxE 62k/f+kwskIxXmjdhEPDVuzCwyMbw7KhCjhs46DY4cL1CpKzw3/xbUsi1Qpn5CStHVG4 U2Ug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=nB4AXPrd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from morse.vger.email (morse.vger.email. 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Wed, 20 Sep 2023 12:11:35 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 06/20] EDAC/synopsys: Fix misleading IRQ self-cleared quirk flag Date: Wed, 20 Sep 2023 22:10:30 +0300 Message-ID: <20230920191059.28395-7-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777585133671028811 X-GMAIL-MSGID: 1777585133671028811 The DDR_ECC_INTR_SELF_CLEAR quirk flag was initially added in the commit f7824ded4149 ("EDAC/synopsys: Add support for version 3 of the Synopsys EDAC DDR") in order to distinguish the ZynqMP DDRC (based on DW uMCTL2 DDRC v2.40a) and the announced in that commit Synopsys DDR controller v3.80a. The selected name is misleading for the next reasons: 1. None of the Synopsys DW uMCTL2 DDR IP-core has the UE/CE IRQs auto or self cleared. The IRQ signals (ecc_corrected_err_intr and ecc_uncorrected_err_intr) are cleared together with the rest of the ECC error data by means of writing 1's to the respective ECCCLR bits. It worked like that in DW uMCTL2 DDRC v2.x IP-core and it's still true for the modern DW uMCTL2 DDRC v3.x. 2. The IRQ-related registers accessed unless the denoted quirk is specified are actually Xilinx Zynq-specific. None of the Synopsys DW uMCTL DDRC IP-core have any registers at the offsets 0x20200/0x20208/0x2020C. The most modern DW uMCTL2 DDRC v3.91a IP-core available has CSRs space end at the 0x43dc offset. The older IP-cores have even smaller registers space. 3. What was actually introduced in the DW uMCTL2 DDRC v3.10 by Synopsys is the IRQ enable flags which older DW uMCTL2 DDRC IP-core didn't have. They were added to the ECCCLR register (the CSR was also renamed to ECCCTL in the v3.10 IP-core HW databook). So since then there have been no point in having a vendor-specific IRQs masking solution like described in 2. and the IRQ signal can be now shared even for the native DW uMCTL2 DDR controllers. So let's harmonize the quirked IRQs code based on the statements above: rename the DDR_ECC_INTR_SELF_CLEAR quirk flag to SYNPS_ZYNQMP_IRQ_REGS thus indicating the ZynqMP-specific IRQ CSRs; add the new quirk flag to the ZynqMP platform data; drop the misleading comments about the auto-cleared ue/ce flags; add a comment about the new IRQ enable flags added in v3.10 IP-core. Signed-off-by: Serge Semin --- Changelog v4: - This is a new patch detached from [PATCH v3 01/17] EDAC/synopsys: Fix native uMCTL2 IRQs handling procedure --- drivers/edac/synopsys_edac.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index fff4b07ff6ac..6b81ac9dda8b 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -89,7 +89,7 @@ /* DDR ECC Quirks */ #define DDR_ECC_INTR_SUPPORT BIT(0) #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) -#define DDR_ECC_INTR_SELF_CLEAR BIT(2) +#define SYNPS_ZYNQMP_IRQ_REGS BIT(2) /* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */ /* ECC Configuration Registers */ @@ -527,7 +527,7 @@ static void enable_intr(struct synps_edac_priv *priv) unsigned long flags; /* Enable UE/CE Interrupts */ - if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { + if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_EN_OFST); @@ -536,6 +536,10 @@ static void enable_intr(struct synps_edac_priv *priv) spin_lock_irqsave(&priv->reglock, flags); + /* + * IRQs Enable/Disable flags have been available since v3.10a. + * This is noop for the older controllers. + */ writel(DDR_UE_MASK | DDR_CE_MASK, priv->baseaddr + ECC_CLR_OFST); @@ -547,7 +551,7 @@ static void disable_intr(struct synps_edac_priv *priv) unsigned long flags; /* Disable UE/CE Interrupts */ - if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { + if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, priv->baseaddr + DDR_QOS_IRQ_DB_OFST); @@ -578,11 +582,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id) priv = mci->pvt_info; p_data = priv->p_data; - /* - * v3.0 of the controller has the ce/ue bits cleared automatically, - * so this condition does not apply. - */ - if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) { + if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); if (!(regval & ECC_CE_UE_INTR_MASK)) @@ -599,8 +599,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id) edac_dbg(3, "Total error count CE %d UE %d\n", priv->ce_cnt, priv->ue_cnt); - /* v3.0 of the controller does not have this register */ - if (!(priv->p_data->quirks & DDR_ECC_INTR_SELF_CLEAR)) + + if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); return IRQ_HANDLED; @@ -914,7 +914,7 @@ static const struct synps_platform_data zynqmp_edac_def = { .get_mtype = zynqmp_get_mtype, .get_dtype = zynqmp_get_dtype, .get_ecc_state = zynqmp_get_ecc_state, - .quirks = (DDR_ECC_INTR_SUPPORT + .quirks = (DDR_ECC_INTR_SUPPORT | SYNPS_ZYNQMP_IRQ_REGS #ifdef CONFIG_EDAC_DEBUG | DDR_ECC_DATA_POISON_SUPPORT #endif @@ -926,7 +926,7 @@ static const struct synps_platform_data synopsys_edac_def = { .get_mtype = zynqmp_get_mtype, .get_dtype = zynqmp_get_dtype, .get_ecc_state = zynqmp_get_ecc_state, - .quirks = (DDR_ECC_INTR_SUPPORT | DDR_ECC_INTR_SELF_CLEAR + .quirks = (DDR_ECC_INTR_SUPPORT #ifdef CONFIG_EDAC_DEBUG | DDR_ECC_DATA_POISON_SUPPORT #endif From patchwork Wed Sep 20 19:10:31 2023 Content-Type: text/plain; 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Wed, 20 Sep 2023 12:11:38 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 07/20] EDAC/synopsys: Use platform device devm ioremap method Date: Wed, 20 Sep 2023 22:10:31 +0300 Message-ID: <20230920191059.28395-8-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777585535617712054 X-GMAIL-MSGID: 1777585535617712054 DW DDRs CSRs resource descriptor is used by the devm_ioremap_resource() function invocation only in the driver probe method. Thus convert the platform_get_resource() and devm_ioremap_resource() couple to just a single devm_platform_ioremap_resource() method call. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 6b81ac9dda8b..afe9f475cb4e 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1335,11 +1335,9 @@ static int mc_probe(struct platform_device *pdev) struct synps_edac_priv *priv; struct mem_ctl_info *mci; void __iomem *baseaddr; - struct resource *res; int rc; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - baseaddr = devm_ioremap_resource(&pdev->dev, res); + baseaddr = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(baseaddr)) return PTR_ERR(baseaddr); From patchwork Wed Sep 20 19:10:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142598 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4419388vqi; Wed, 20 Sep 2023 13:55:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGK70FmcHWmTlrx2Jfu3MS9deeFTMEMLu3Dvfep9l/6dQokSV2FYoxjg1963etHjg7SiDiU X-Received: by 2002:a05:6870:304c:b0:1a9:caa6:1337 with SMTP id u12-20020a056870304c00b001a9caa61337mr3902290oau.23.1695243340655; Wed, 20 Sep 2023 13:55:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695243340; cv=none; d=google.com; s=arc-20160816; b=pKsdMydi5MgoPPqoHTmO43qKq79f4SHqNJq5pU6dOjAKLn4dNMQJYu/lGPY8M0GFCH WbsQFV9ge4roDWVQNI9E1yrOSuqS0jSegC1AnHbX8tqFIaJNVck4kj19Trvj6qoi9iXP zCg0RWU4ifsFJUWf6rmOs/v/WL9S8GWPPXsGizuO6TDE21FSjW9rEewrh6xSkdcqJEn7 gY1WraJiEdjko3SR48PHl24dzPlubUpeQsuNZPm2sBjut6Ph7a8TIrRP3ZKy9BecZDt3 bN8IC8Qa3DX5agClMvFASIjvgLkcgKlCfoDiSVlOVece3VMK7ES5cNXWZHnc6dBpQ13M XEBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=EgoOFuIOH/yTjnEmwXNjUQs0ssos4vCiXDfBrtR+jUo=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=0+ZceHSXsNXzcwh1xqi9j7XatmxjVF+S+obVdkcXj/DQpodOKYOesiQsHiZU/UpaHA FqUQmzbj2cNKdSbcnSHcNCs4SMv3/BEc98R/nf28zxf0LnuINVN/885hjUuq6B1d7zkS WSrSWM+iW1efN0iSZOKdttPjsrjOdzTYbJGS2YV6tpI838EQkV8CSxnHbDhvNJCJFrdr cHBIQh85/dL4FSZQ7q8F4eelnxk4XxUmMR+fQZTcKY6DsIBd5Gxnz9NYGwN43W1eW+9/ KaGXPlNjcWqQTMA9MLHO5pAva6HYVjqGmhPSF2Trxsn4GYcyZIuQcukeOembZcc6eP1o JsCA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=mTsCNcIh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. 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Secondly the EDAC core already tracks the total amount of the correctable and uncorrectable errors (see mem_ctl_info.{ce_mc,ue_mc} fields usage). Drop the useless internal counters then for good. Signed-off-by: Serge Semin --- Changelog v4: - Drop redundant empty line. - Drop private counters access from the check_errors() method too. --- drivers/edac/synopsys_edac.c | 14 -------------- 1 file changed, 14 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index afe9f475cb4e..c2ac2eb64642 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -305,8 +305,6 @@ struct synps_ecc_status { * @message: Buffer for framing the event specific info. * @stat: ECC status information. * @p_data: Platform data. - * @ce_cnt: Correctable Error count. - * @ue_cnt: Uncorrectable Error count. * @poison_addr: Data poison address. * @row_shift: Bit shifts for row bit. * @col_shift: Bit shifts for column bit. @@ -320,8 +318,6 @@ struct synps_edac_priv { char message[SYNPS_EDAC_MSG_SIZE]; struct synps_ecc_status stat; const struct synps_platform_data *p_data; - u32 ce_cnt; - u32 ue_cnt; #ifdef CONFIG_EDAC_DEBUG ulong poison_addr; u32 row_shift[18]; @@ -593,13 +589,8 @@ static irqreturn_t intr_handler(int irq, void *dev_id) if (status) return IRQ_NONE; - priv->ce_cnt += priv->stat.ce_cnt; - priv->ue_cnt += priv->stat.ue_cnt; handle_error(mci, &priv->stat); - edac_dbg(3, "Total error count CE %d UE %d\n", - priv->ce_cnt, priv->ue_cnt); - if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); @@ -625,12 +616,7 @@ static void check_errors(struct mem_ctl_info *mci) if (status) return; - priv->ce_cnt += priv->stat.ce_cnt; - priv->ue_cnt += priv->stat.ue_cnt; handle_error(mci, &priv->stat); - - edac_dbg(3, "Total error count CE %d UE %d\n", - priv->ce_cnt, priv->ue_cnt); } /** From patchwork Wed Sep 20 19:10:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4487063vqi; Wed, 20 Sep 2023 16:14:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHgmPNZ1X2qCjwKuyI60/MTFpjdw8gAUb8vlAr2jjZZK104C8xFUcx+Sa8surr+jydM+gB9 X-Received: by 2002:a05:6870:ec92:b0:1d5:a6ac:ac92 with SMTP id eo18-20020a056870ec9200b001d5a6acac92mr4486501oab.38.1695251683670; Wed, 20 Sep 2023 16:14:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695251683; cv=none; d=google.com; s=arc-20160816; b=QK+kUyjAUEMjCqlYU3v4NMGOkmm1AgK1x6rOqFas94f7stX6K5aBtN05BM5AzebyKy OoGNL7/rN4pEsx7bjIPxzNpow1eW86bkuy8pK0H4NLo6lzT6+1aroWjSnk9MVB9mB7FK xTqj4aMoUov0M61s6J2hktDIaVw1Jvg1Q2mzEHcrEq/BNWnCKApDhoiU9PdAt0t6g4No xQ3lyf3w7iKKep8LdqsZxIu87J4nXCmAoBMvuVASKkuOCDodpeFH7okJUlGea2swsI8U hqrgbFoOmLu90XMsa2d8TZGSJsMsuybMlsxV87Evj996/RXop+dlPx/5jp01s94wBbB8 SxeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yHRQdHA2TrKcClwyZPJGHcHGoAWxrLE4S/rv0kc+7Gc=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=G0HKuGLVggi8v5WjT5X70aXsJylVsG612mTX0RJpLgS5zWxafTEYAmZeAK3D7LQBVW N+YbC0teUpekMFjU+7pSMs4Hn4xd0iJmiWlYm8jiINRew/2GYifzSKBtOMcIeVvsbATB xvRCgAhBYpeT75DNzOWlb+tZx8IsxyG9+SnG9+1F5HmgiqyW3KhtfjdJWk/dFkqF5di5 0VzPKJfaUV6WaVKs0gzDZPBzt0TDzfwR2OzTFykEEuDK+/wuvY3hWVnoyAtBPoWAGqHV oTC/WULGyWVYi1tzSeK15r0aUbonjxNkm3a64gmaiYA42CacC/QtfyREE9ysZpm9XZHg 9PNg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=RFN2Ovla; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from agentk.vger.email (agentk.vger.email. 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Wed, 20 Sep 2023 12:11:44 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 09/20] EDAC/synopsys: Drop local to_mci() macro definition Date: Wed, 20 Sep 2023 22:10:33 +0300 Message-ID: <20230920191059.28395-10-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777600229594065266 X-GMAIL-MSGID: 1777600229594065266 The to_mci() macro was added in commit 1a81361f75d8 ("EDAC, synopsys: Add Error Injection support for ZynqMP DDR controller") together with the errors injection debug feature. It turns out the absolutely the same macro-function has already been defined in the edac_mc.h (former edac_core.h) header file. No idea why it was needed to have a local version of the macro, but there is no point in it now. Drop the local macro-function definition for good. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index c2ac2eb64642..0c6441719215 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -941,7 +941,6 @@ static const struct of_device_id synps_edac_match[] = { MODULE_DEVICE_TABLE(of, synps_edac_match); #ifdef CONFIG_EDAC_DEBUG -#define to_mci(k) container_of(k, struct mem_ctl_info, dev) /** * ddr_poison_setup - Update poison registers. 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Wed, 20 Sep 2023 12:11:46 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 10/20] EDAC/synopsys: Drop struct ecc_error_info.blknr field Date: Wed, 20 Sep 2023 22:10:34 +0300 Message-ID: <20230920191059.28395-11-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777602341109505737 X-GMAIL-MSGID: 1777602341109505737 Even though the ECC(C|U)ADDR1 CSR description indeed says it's a "Block number" in the DW uMCTL2 DDRC IP-core databooks, the corresponding register field is named as ECC(C|U)ADDR1.ecc_(un)corr_col (which means ECC (un)corrected column) and in the rest of the document it's referred as the SDRAM address column. Thus use the already available ecc_error_info.col field to read the column number to and drop the questionable ecc_error_info.blknr field for good. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 21 +++++++++------------ 1 file changed, 9 insertions(+), 12 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 0c6441719215..f2bcc3f79bf2 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -174,7 +174,7 @@ #define ECC_CEADDR0_RNK_MASK BIT(24) #define ECC_CEADDR1_BNKGRP_MASK 0x3000000 #define ECC_CEADDR1_BNKNR_MASK 0x70000 -#define ECC_CEADDR1_BLKNR_MASK 0xFFF +#define ECC_CEADDR1_COL_MASK 0xFFF #define ECC_CEADDR1_BNKGRP_SHIFT 24 #define ECC_CEADDR1_BNKNR_SHIFT 16 @@ -272,7 +272,6 @@ * @bitpos: Bit position. * @data: Data causing the error. * @bankgrpnr: Bank group number. - * @blknr: Block number. */ struct ecc_error_info { u32 row; @@ -281,7 +280,6 @@ struct ecc_error_info { u32 bitpos; u32 data; u32 bankgrpnr; - u32 blknr; }; /** @@ -434,7 +432,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) ECC_CEADDR1_BNKNR_SHIFT; p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> ECC_CEADDR1_BNKGRP_SHIFT; - p->ceinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); + p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK); p->ceinfo.data = readl(base + ECC_CSYND0_OFST); edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), @@ -450,7 +448,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) ECC_CEADDR1_BNKGRP_SHIFT; p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> ECC_CEADDR1_BNKNR_SHIFT; - p->ueinfo.blknr = (regval & ECC_CEADDR1_BLKNR_MASK); + p->ueinfo.col = (regval & ECC_CEADDR1_COL_MASK); p->ueinfo.data = readl(base + ECC_UESYND0_OFST); out: spin_lock_irqsave(&priv->reglock, flags); @@ -481,10 +479,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ceinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Bank %d BankGroup Number %d Block Number %d Bit Position: %d Data: 0x%08x", - "CE", pinf->row, pinf->bank, - pinf->bankgrpnr, pinf->blknr, - pinf->bitpos, pinf->data); + "DDR ECC error type:%s Row %d Col %d Bank %d BankGroup Number %d Bit Position: %d Data: 0x%08x", + "CE", pinf->row, pinf->col, pinf->bank, + pinf->bankgrpnr, pinf->bitpos, pinf->data); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", @@ -501,9 +498,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ueinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type :%s Row %d Bank %d BankGroup Number %d Block Number %d", - "UE", pinf->row, pinf->bank, - pinf->bankgrpnr, pinf->blknr); + "DDR ECC error type :%s Row %d Col %d Bank %d BankGroup Number %d", + "UE", pinf->row, pinf->col, pinf->bank, + pinf->bankgrpnr); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, "DDR ECC error type :%s Row %d Bank %d Col %d ", From patchwork Wed Sep 20 19:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142645 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4487854vqi; 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Wed, 20 Sep 2023 12:11:49 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 11/20] EDAC/synopsys: Shorten out struct ecc_error_info.bankgrpnr field name Date: Wed, 20 Sep 2023 22:10:35 +0300 Message-ID: <20230920191059.28395-12-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777600323867069626 X-GMAIL-MSGID: 1777600323867069626 None of the ecc_error_info structure fields have "nr" suffix even though each of them do represent some number (row number, column number, bank number). Drop the suffix from the bankgrpnr field name for the sake of unification then. Similarly drop the word "Number" from the CE/UE error messages too since it doesn't give any helpful info there. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index f2bcc3f79bf2..f1ec44cdd87f 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -269,17 +269,17 @@ * @row: Row number. * @col: Column number. * @bank: Bank number. + * @bankgrp: Bank group number. * @bitpos: Bit position. * @data: Data causing the error. - * @bankgrpnr: Bank group number. */ struct ecc_error_info { u32 row; u32 col; u32 bank; + u32 bankgrp; u32 bitpos; u32 data; - u32 bankgrpnr; }; /** @@ -430,7 +430,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) regval = readl(base + ECC_CEADDR1_OFST); p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> ECC_CEADDR1_BNKNR_SHIFT; - p->ceinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> + p->ceinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> ECC_CEADDR1_BNKGRP_SHIFT; p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK); p->ceinfo.data = readl(base + ECC_CSYND0_OFST); @@ -444,7 +444,7 @@ static int zynqmp_get_error_info(struct synps_edac_priv *priv) regval = readl(base + ECC_UEADDR0_OFST); p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); regval = readl(base + ECC_UEADDR1_OFST); - p->ueinfo.bankgrpnr = (regval & ECC_CEADDR1_BNKGRP_MASK) >> + p->ueinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> ECC_CEADDR1_BNKGRP_SHIFT; p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> ECC_CEADDR1_BNKNR_SHIFT; @@ -479,9 +479,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ceinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Col %d Bank %d BankGroup Number %d Bit Position: %d Data: 0x%08x", + "DDR ECC error type:%s Row %d Col %d Bank %d Bank Group %d Bit Position: %d Data: 0x%08x", "CE", pinf->row, pinf->col, pinf->bank, - pinf->bankgrpnr, pinf->bitpos, pinf->data); + pinf->bankgrp, pinf->bitpos, pinf->data); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", @@ -498,9 +498,9 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ueinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type :%s Row %d Col %d Bank %d BankGroup Number %d", + "DDR ECC error type :%s Row %d Col %d Bank %d Bank Group %d", "UE", pinf->row, pinf->col, pinf->bank, - pinf->bankgrpnr); + pinf->bankgrp); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, "DDR ECC error type :%s Row %d Bank %d Col %d ", From patchwork Wed Sep 20 19:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142628 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4460620vqi; Wed, 20 Sep 2023 15:17:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOsBHJusOuYUvQkZTrn4IVUdAH3cj/N5N85uDLaapmic0qkgY+jEFyhKL/+5AHJ12ci2Xe X-Received: by 2002:a17:902:da8a:b0:1c5:b1cc:fe16 with SMTP id j10-20020a170902da8a00b001c5b1ccfe16mr4903949plx.20.1695248247429; Wed, 20 Sep 2023 15:17:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695248247; cv=none; d=google.com; s=arc-20160816; b=WAFzkhWMVeuyJvHn5lSvl9WcnagoN+yKE8Agu1TMJWghEHHNVUL9heJ6iqyfh7nkeU +PUi0BEDqtcaxogM/OQ9WgVOROfU0I+tyVVnMoecT+sCYBEjVhxeaXS+Mn1/2lwPQPKH NKix7v/Vb2awBZLAFvOZBGOi5pVRezSH0NCl9sgtBz0DKSer1XEoJ+aq56abVI2zQ9X8 b+p93+ZII/WVEzsoYsw3lvtf4qpy6Wju0F4mCa0EBMJxlmWbl/8oK9WweCi2E2OBN7m3 GMAU3WzUXQJtkmsH3hF1NL61mmV7jPp9sc4+MXcOFIQWVyLM899Jgs7uQsgUofcg11Uq If+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=fcL6jVEgRGh/qyB/fYgM+LhUsSDKaUSeMRlsor46jHo=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=dWD3+8tBHGkbtFWRFWbJXRnUUSxbCFvaMR+ROS9w+ri7k+u8HSg5c35BMajfKEa4s+ jMgt2LwIPLHsYFrTirRp9zEZ1ktER8yrsPR2WAV8Jij4b5xjuofP3fPI/svlGeD4m900 t7bMgyDLhWsiVoLQD0bUkMGe6dVcKVvtypgRvGrZ/K/97KrzEnRSO9acT53Cifsz+Gty 7BgemPAGaa93nQDimX8U51fy8K6lxOJ0zDipPnEi/cyM7B3Cg3R9jhJZlMa6yYOiXARG yMGNx44VW5Ac51O3WE3xNZR+scY9g7+7L1RtOKtCOLUQxPzo4laEZaxhxhsfFShwSSEB zIYg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=A0ILyv7k; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from snail.vger.email (snail.vger.email. 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There is some duplicated/redundant information which can be freely removed from it: drop the message prefix "DDR ECC error type:%s" since the resultant text printed to the log by the edac_mc_printk() method will contain the error type and the memory controller id referring to the device detected the error anyway; with no harm to readability shorten out the phrase "Bit Position" to being just "Bit". Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index f1ec44cdd87f..62f498b6dfed 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -479,13 +479,13 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ceinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Col %d Bank %d Bank Group %d Bit Position: %d Data: 0x%08x", - "CE", pinf->row, pinf->col, pinf->bank, - pinf->bankgrp, pinf->bitpos, pinf->data); + "Row %d Col %d Bank %d Bank Group %d Bit %d Data 0x%08x", + pinf->row, pinf->col, pinf->bank, pinf->bankgrp, + pinf->bitpos, pinf->data); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type:%s Row %d Bank %d Col %d Bit Position: %d Data: 0x%08x", - "CE", pinf->row, pinf->bank, pinf->col, + "Row %d Bank %d Col %d Bit: %d Data: 0x%08x", + pinf->row, pinf->bank, pinf->col, pinf->bitpos, pinf->data); } @@ -498,13 +498,12 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) pinf = &p->ueinfo; if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type :%s Row %d Col %d Bank %d Bank Group %d", - "UE", pinf->row, pinf->col, pinf->bank, - pinf->bankgrp); + "Row %d Col %d Bank %d Bank Group %d", + pinf->row, pinf->col, pinf->bank, pinf->bankgrp); } else { snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "DDR ECC error type :%s Row %d Bank %d Col %d ", - "UE", pinf->row, pinf->bank, pinf->col); + "Row %d Bank %d Col %d", + pinf->row, pinf->bank, pinf->col); } edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, From patchwork Wed Sep 20 19:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142565 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4371422vqi; Wed, 20 Sep 2023 12:21:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpZPQMChifzM1tSHXeJEUoEpVJ2i3w2CZUTGwH4dl2PeOvwisjCqZ4OHtCFKspbIc4TQsL X-Received: by 2002:a05:6870:6487:b0:1c8:bf19:e1e4 with SMTP id cz7-20020a056870648700b001c8bf19e1e4mr3577043oab.37.1695237701488; Wed, 20 Sep 2023 12:21:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695237701; cv=none; d=google.com; s=arc-20160816; b=APtL0mbgycfJf54h7fi7MeP5BxKIbEj+k11XrXJ6F1vcmvW401kx34Y5ydsgrRlcXP GXj+kplY2MX2UR3+dJea8mlNR/Ijjc544gV3xuKjSr7RaDo0fBKP+D+gzboN3++BShGm AqZHAWambnBwUt9Ito+l8eYTDnSuhrRIGq3blulknl/+FSljUpmp8BPNb2cFEjvZIw4Z l0vmU+IiW7fjH287tHwQhUfVtgUWMeFVfkGHWwP2G71QwA4rwUVBYhwkmTKTW6iIiezy UoNWFrNNBw+lm8kZuGxOd1Mbqhi/eJoiPafho0fykU4T9+g24rEAd5ApLFEPqRXT4GXJ vRcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=v+zg14s+8ZGl4N+E2RwxXEDbGvXikDYsUs+6iexwq0A=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=vFSkmAa8KO63ZiTlLQdE9R62yGbPU/x6MlM7iUg4HtdZJuenZSm6RNNONjXHzs7bZV N4778Hho2xy1Jex9r9ojFDvbY8J1mWIYH0jyGAAQoi0KA3mgarat4d/Jaa0A2ty6YAyr Qwja/GVO4Sm38v+RjYyNN0CTJJgO1Bz1Bgzo5YRbwMDK+Rjb7Cu0umQhSEAi8fHqpKyp +qsNQ/Oz33u6Z+8CQAEvXgll80+olFkeD7ITVIdWZkLAeZcNDFMLLWxjDhWaNWCul5XN l/Z2UCrpR8bVpgwgKo2UkBIvAII05PP3P6uEgbQw/F4sVnaAWWjDXVYuiL1gUFxqhPzy jxvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="iMpwe/bG"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from pete.vger.email (pete.vger.email. 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Wed, 20 Sep 2023 12:11:55 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 13/20] EDAC/mc: Init DIMM labels in MC registration method Date: Wed, 20 Sep 2023 22:10:37 +0300 Message-ID: <20230920191059.28395-14-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:52 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777585568092924376 X-GMAIL-MSGID: 1777585568092924376 Move the DIMM labels initialization to the memory controller registration method as a preparation before adding the generic procedure to allocate an unique MC index. It's required because the DIMM labels contain the MC index as the "mc%u" part of the string, which in case of the auto-generated index isn't available at the moment of the MCI/csrow/dimms descriptor allocation. Signed-off-by: Serge Semin --- drivers/edac/edac_mc.c | 48 +++++++++++++++++++++++++++--------------- 1 file changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 6faeb2ab3960..24814839d885 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -256,7 +256,6 @@ static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) unsigned int pos[EDAC_MAX_LAYERS]; unsigned int row, chn, idx; int layer; - void *p; /* * Allocate and fill the dimm structs @@ -271,7 +270,6 @@ static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) for (idx = 0; idx < mci->tot_dimms; idx++) { struct dimm_info *dimm; struct rank_info *chan; - int n, len; chan = mci->csrows[row]->channels[chn]; @@ -282,22 +280,9 @@ static int edac_mc_alloc_dimms(struct mem_ctl_info *mci) dimm->mci = mci; dimm->idx = idx; - /* - * Copy DIMM location and initialize it. - */ - len = sizeof(dimm->label); - p = dimm->label; - n = scnprintf(p, len, "mc#%u", mci->mc_idx); - p += n; - len -= n; - for (layer = 0; layer < mci->n_layers; layer++) { - n = scnprintf(p, len, "%s#%u", - edac_layer_name[mci->layers[layer].type], - pos[layer]); - p += n; - len -= n; + /* Copy DIMM location */ + for (layer = 0; layer < mci->n_layers; layer++) dimm->location[layer] = pos[layer]; - } /* Link it to the csrows old API data */ chan->dimm = dimm; @@ -510,6 +495,33 @@ void edac_mc_reset_delay_period(unsigned long value) +/** + * edac_mc_init_labels() - Initialize DIMM labels + * + * @mci: pointer to the mci structure which DIMM labels need to be initialized + * + * .. note:: + * locking model: must be called with the mem_ctls_mutex lock held + */ +static void edac_mc_init_labels(struct mem_ctl_info *mci) +{ + int n, len, layer; + unsigned int idx; + char *p; + + for (idx = 0; idx < mci->tot_dimms; idx++) { + len = sizeof(mci->dimms[idx]->label); + p = mci->dimms[idx]->label; + + n = scnprintf(p, len, "mc#%u", mci->mc_idx); + for (layer = 0; layer < mci->n_layers; layer++) { + n += scnprintf(p + n, len - n, "%s#%u", + edac_layer_name[mci->layers[layer].type], + mci->dimms[idx]->location[layer]); + } + } +} + /* Return 0 on success, 1 on failure. * Before calling this function, caller must * assign a unique value to mci->mc_idx. @@ -637,6 +649,8 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, goto fail0; } + edac_mc_init_labels(mci); + if (add_mc_to_global_list(mci)) goto fail0; From patchwork Wed Sep 20 19:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142606 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4427695vqi; Wed, 20 Sep 2023 14:10:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHVfDplm3xf2pGEXRX8obuvbCtanI0BUE70F+T2i4HXFiWjN3LaZd83thWWsQmUXwPKV3kR X-Received: by 2002:a17:902:d48c:b0:1c5:6f4d:d6dd with SMTP id c12-20020a170902d48c00b001c56f4dd6ddmr9822757plg.24.1695244203835; Wed, 20 Sep 2023 14:10:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695244203; cv=none; d=google.com; s=arc-20160816; b=Vj3vcB1vC5pFaQTBJ77cEV/NcutoThSaV9+6JYgFeN7eO4m/qeZbotvKyCD2FqK5at cIPZV9vF8PBAOTh2wlgw90bQj/4FY/o2ReGDU3eQtao4AN4hqskm97h7p3M397hcy81T Qxr16lE+DeYjUedUTWMCAWizS5BJey0JFdhbZD+rgIxRvZAgQ7uFk4HABN7IQKv3iPO/ CovJRXmnYwNom7cxJxMA0uJAMnFJuDBBo6E/s0fkr1aZ4nB2ZWyzdZQrG+945dTq7Qup jJXnUFgESW59Gyg6ORVR8ENrFi7gwSnGQkp7/73uTw61ui/7YKR/MGjjHRpWn7gPScLt C/LA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=imtUzm6BSk9S5Zn88Nu5Ur68x7dQT0fyS8OcYR+/2Ug=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=j3WpwA5/1u1Qzl28AlqRe4ZBr+YAzx1WXqjmQGfyH792VgpQ26fcK3pRKKw6Y7mOEi YhFpuVxkbj1rGHUUodWSH83OmTiGFx12SQeLQHET7A7qYxzfdc3B87X5GG+5R8NFVdj7 VMKqJwy5fFOPK1IlaEH5jbxAp4JSUcSM9CZ+PyVV5T7Jgq2nSxiaNTwZNI9X94FD7FNZ lRtkGV91eKEVtlgMbtZMHAxae2IgLiA0JJp2fZaIP43vtZ7Pwfb0CfjV6K8d7hyEej1m JD+dbZAv1yk/1HwJ+QguzVMNOAma0mwAByaDA5MWr50eY/k4CdBQsl5XzdiMHPij9utD YDHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=GafjPM1Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. 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Wed, 20 Sep 2023 12:12:02 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 14/20] EDAC/mc: Add generic unique MC index allocation procedure Date: Wed, 20 Sep 2023 22:10:38 +0300 Message-ID: <20230920191059.28395-15-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777592386438267524 X-GMAIL-MSGID: 1777592386438267524 Currently the EDAC subsystem relies on the low-level device drivers to select an unique index for each memory controller available in the system. Here are the already implemented approaches: 1. Fixed zero id. The vast majority of the drivers expect to have a single memory controller in the system. 2. Calculate based on a platform-specific way (Pre-defined devices order, PCIe-bus address, Numa node ID + PCIe-function number, etc). 3. Use platform_device->id. 4. Use custom ACPI/OF property value. 5. Use locally maintained static MC counter. Create a generic method of the MC index allocation which could be utilized for the case 5 (it doesn't imply any strict memory controller order) and which would prevent the new MC EDAC drivers re-implementing the approaches 3 and 4. Moreover it will be useful for the cases when a platform is equipped with memory-controllers of different types [1] and which are probed by different drivers [2]. [1] Link: https://lore.kernel.org/all/9dc2a947-d2ab-4f00-8ed3-d2499cb6fdfd@BN1BFFO11FD002.protection.gbl/ [2] Link: https://lore.kernel.org/linux-edac/BY5PR12MB4258CB67B70D71F107EC1E9DDB3E9@BY5PR12MB4258.namprd12.prod.outlook.com The suggested implementation is based on the IDA kernel API and implies the next semantics: 1. If a particular MC index is specified it will be registered in the IDR pool unless the specified ID has already been reserved. 2. If a special MC index is specified (EDAC_AUTO_MC_NUM) the EDAC core will check whether there is a "mcID" alias is defined in the device tree and use the ID from there if it's found. 3. Otherwise a next free index will be allocated and assigned to the registered memory controller. Signed-off-by: Serge Semin --- Note the approach implemented here has been partly ported from the SPI core driver using IDA to track/allocate SPI bus numbers. Link: https://elixir.bootlin.com/linux/latest/source/drivers/spi/spi.c#L2957 --- drivers/edac/edac_mc.c | 89 +++++++++++++++++++++++++++++++++++++++--- drivers/edac/edac_mc.h | 4 ++ 2 files changed, 87 insertions(+), 6 deletions(-) diff --git a/drivers/edac/edac_mc.c b/drivers/edac/edac_mc.c index 24814839d885..634c41ea7804 100644 --- a/drivers/edac/edac_mc.c +++ b/drivers/edac/edac_mc.c @@ -29,6 +29,9 @@ #include #include #include +#include +#include + #include #include "edac_mc.h" #include "edac_module.h" @@ -46,6 +49,7 @@ EXPORT_SYMBOL_GPL(edac_op_state); /* lock to memory controller's control array */ static DEFINE_MUTEX(mem_ctls_mutex); static LIST_HEAD(mc_devices); +static DEFINE_IDR(mc_idr); /* * Used to lock EDAC MC to just one module, avoiding two drivers e. g. @@ -493,7 +497,64 @@ void edac_mc_reset_delay_period(unsigned long value) mutex_unlock(&mem_ctls_mutex); } +/** + * edac_mc_alloc_id() - Allocate unique Memory Controller identifier + * + * @mci: pointer to the mci structure to allocate ID for + * + * Use edac_mc_free_id() to coherently free the MC identifier. + * + * .. note:: + * locking model: must be called with the mem_ctls_mutex lock held + * + * Returns: + * 0 on Success, or an error code on failure + */ +static int edac_mc_alloc_id(struct mem_ctl_info *mci) +{ + struct device_node *np = dev_of_node(mci->pdev); + int ret, min, max; + + if (mci->mc_idx == EDAC_AUTO_MC_NUM) { + ret = of_alias_get_id(np, "mc"); + if (ret >= 0) { + min = ret; + max = ret + 1; + } else { + min = of_alias_get_highest_id("mc"); + if (min >= 0) + min++; + else + min = 0; + + max = 0; + } + } else { + min = mci->mc_idx; + max = mci->mc_idx + 1; + } + + ret = idr_alloc(&mc_idr, mci, min, max, GFP_KERNEL); + if (ret < 0) + return ret == -ENOSPC ? -EBUSY : ret; + + mci->mc_idx = ret; + + return 0; +} +/** + * edac_mc_free_id() - Free Memory Controller identifier + * + * @mci: pointer to the mci structure to free ID from + * + * .. note:: + * locking model: must be called with the mem_ctls_mutex lock held + */ +static void edac_mc_free_id(struct mem_ctl_info *mci) +{ + idr_remove(&mc_idr, mci->mc_idx); +} /** * edac_mc_init_labels() - Initialize DIMM labels @@ -612,7 +673,8 @@ EXPORT_SYMBOL_GPL(edac_get_owner); int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, const struct attribute_group **groups) { - int ret = -EINVAL; + int ret; + edac_dbg(0, "\n"); #ifdef CONFIG_EDAC_DEBUG @@ -649,20 +711,30 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, goto fail0; } + ret = edac_mc_alloc_id(mci); + if (ret) { + edac_printk(KERN_ERR, EDAC_MC, "failed to allocate MC idx %u\n", + mci->mc_idx); + goto fail0; + } + edac_mc_init_labels(mci); - if (add_mc_to_global_list(mci)) - goto fail0; + if (add_mc_to_global_list(mci)) { + ret = -EINVAL; + goto fail1; + } /* set load time so that error rate can be tracked */ mci->start_time = jiffies; mci->bus = edac_get_sysfs_subsys(); - if (edac_create_sysfs_mci_device(mci, groups)) { + ret = edac_create_sysfs_mci_device(mci, groups); + if (ret) { edac_mc_printk(mci, KERN_WARNING, "failed to create sysfs device\n"); - goto fail1; + goto fail2; } if (mci->edac_check) { @@ -686,9 +758,12 @@ int edac_mc_add_mc_with_groups(struct mem_ctl_info *mci, mutex_unlock(&mem_ctls_mutex); return 0; -fail1: +fail2: del_mc_from_global_list(mci); +fail1: + edac_mc_free_id(mci); + fail0: mutex_unlock(&mem_ctls_mutex); return ret; @@ -716,6 +791,8 @@ struct mem_ctl_info *edac_mc_del_mc(struct device *dev) if (del_mc_from_global_list(mci)) edac_mc_owner = NULL; + edac_mc_free_id(mci); + mutex_unlock(&mem_ctls_mutex); if (mci->edac_check) diff --git a/drivers/edac/edac_mc.h b/drivers/edac/edac_mc.h index 881b00eadf7a..4b6676235b1b 100644 --- a/drivers/edac/edac_mc.h +++ b/drivers/edac/edac_mc.h @@ -23,6 +23,7 @@ #define _EDAC_MC_H_ #include +#include #include #include #include @@ -37,6 +38,9 @@ #include #include +/* Generate MC identifier automatically */ +#define EDAC_AUTO_MC_NUM UINT_MAX + #if PAGE_SHIFT < 20 #define PAGES_TO_MiB(pages) ((pages) >> (20 - PAGE_SHIFT)) #define MiB_TO_PAGES(mb) ((mb) << (20 - PAGE_SHIFT)) From patchwork Wed Sep 20 19:10:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142608 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4430615vqi; Wed, 20 Sep 2023 14:15:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXSZ0eHtKndkHGipFpev49Q+MoG6hRr9SQp6XgRrrAH8S/AJxmGUj6McPwGrxp3c74KFO2 X-Received: by 2002:a17:902:76ca:b0:1b8:94e9:e7cb with SMTP id j10-20020a17090276ca00b001b894e9e7cbmr2945101plt.21.1695244535854; Wed, 20 Sep 2023 14:15:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695244535; cv=none; d=google.com; s=arc-20160816; b=jS4OyqGaQjMYoNjHZzKPC/PxOLrjqjza2y0tdSjLjpxZN7LQgswnerQg14dzKY7TOn rDyTdbzjISM3JUNlseYTeu+EJMxOKGENzAWFI+2PHAugBUkrSYfIKVy6OKm6Vaad/2bX or1KLbGM5iPBmKFT1Y3ihB2AuwswrSUptj88jKQZS0lf16/hTMGBHVw6YUILExvTI1Uc OdIDMbCfIZzYKZCigJFBaXsd3g/ciQWSe/Q9LLEJ9RMc7K9Awk4/IZzmN0tafvnkJkeU VNhZVxcAzj3JDmj5m5egEc2PsUDctwEkT1bvAmFDVFjdP0dIe1VRvSpZ0i+8p125QP5t BrQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AS2hrfFTOSsFmGDoeV3Bz2HwRNoskotCiooG8ue6RgE=; fh=334/EUfTOrsSpyElwNoJNJ4mXsXK4Khv85Favbd9Ohw=; b=0LRaEnKPez53S//pU6toHC0HlzBXvVpe4QJKW05jpZJqmzEdLGp4TpJv9Cu0mo56Pc o7UNGPLVt7NpqHIe6AHFEFxieIUkMZCvlZBWePcUcD4GNZGfZcN48Bhn1Eru+8/+NL5u ed4ZgiK7Qyb5QH2AlyxLbZVqCTD5H6Wxd2X4f3MQnToRGqm90NNF4+xPNnE3B14Wcysv 0sC1OeV4bbJLY9It4DgnvW20GirEZxzqdWgbyDZ+8VHpy8G2Po4IQNKjvJI8x2fU2zex BXDoiWU0bwIAxc5hw+4T+zCWc2kI8QG/2J1Hz9Zh89nULQU1rmIfyX543hwt9WjGVxJY Sr1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=iDHAmEMH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from pete.vger.email (pete.vger.email. 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Wed, 20 Sep 2023 12:12:06 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter , Lei Wang , Michael Ellerman , Nicholas Piggin , Christophe Leroy , Egor Martovetsky Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org Subject: [PATCH v4 15/20] EDAC/mc: Re-use generic unique MC index allocation procedure Date: Wed, 20 Sep 2023 22:10:39 +0300 Message-ID: <20230920191059.28395-16-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:13:27 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777592734713204517 X-GMAIL-MSGID: 1777592734713204517 The EDAC drivers locally maintaining a statically defined memory-controllers counter don't care much about the MC index assigned as long as it's unique so the EDAC core perceives it. Convert these drivers to be using the generic MC index allocation procedure recently added to the EDAC core. Signed-off-by: Serge Semin --- Changelog v4: - Initial patch introduction. --- drivers/edac/dmc520_edac.c | 4 +--- drivers/edac/pasemi_edac.c | 5 +---- drivers/edac/ppc4xx_edac.c | 5 +---- 3 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/edac/dmc520_edac.c b/drivers/edac/dmc520_edac.c index 1fa5ca57e9ec..abd73ed0ad89 100644 --- a/drivers/edac/dmc520_edac.c +++ b/drivers/edac/dmc520_edac.c @@ -173,8 +173,6 @@ struct dmc520_edac { int masks[NUMBER_OF_IRQS]; }; -static int dmc520_mc_idx; - static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset) { return readl(pvt->reg_base + offset); @@ -517,7 +515,7 @@ static int dmc520_edac_probe(struct platform_device *pdev) layers[0].size = dmc520_get_rank_count(reg_base); layers[0].is_virt_csrow = true; - mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt)); + mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, sizeof(*pvt)); if (!mci) { edac_printk(KERN_ERR, EDAC_MOD_NAME, "Failed to allocate memory for mc instance\n"); diff --git a/drivers/edac/pasemi_edac.c b/drivers/edac/pasemi_edac.c index 1a1c3296ccc8..afebfbda1ea0 100644 --- a/drivers/edac/pasemi_edac.c +++ b/drivers/edac/pasemi_edac.c @@ -57,8 +57,6 @@ #define PASEMI_EDAC_ERROR_GRAIN 64 static int last_page_in_mmc; -static int system_mmc_id; - static u32 pasemi_edac_get_error_info(struct mem_ctl_info *mci) { @@ -203,8 +201,7 @@ static int pasemi_edac_probe(struct pci_dev *pdev, layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = PASEMI_EDAC_NR_CHANS; layers[1].is_virt_csrow = false; - mci = edac_mc_alloc(system_mmc_id++, ARRAY_SIZE(layers), layers, - 0); + mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, 0); if (mci == NULL) return -ENOMEM; diff --git a/drivers/edac/ppc4xx_edac.c b/drivers/edac/ppc4xx_edac.c index 046969b4e82e..2b3d66bd0c28 100644 --- a/drivers/edac/ppc4xx_edac.c +++ b/drivers/edac/ppc4xx_edac.c @@ -1214,7 +1214,6 @@ static int ppc4xx_edac_probe(struct platform_device *op) const struct device_node *np = op->dev.of_node; struct mem_ctl_info *mci = NULL; struct edac_mc_layer layers[2]; - static int ppc4xx_edac_instance; /* * At this point, we only support the controller realized on @@ -1265,7 +1264,7 @@ static int ppc4xx_edac_probe(struct platform_device *op) layers[1].type = EDAC_MC_LAYER_CHANNEL; layers[1].size = ppc4xx_edac_nr_chans; layers[1].is_virt_csrow = false; - mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers, + mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, sizeof(struct ppc4xx_edac_pdata)); if (mci == NULL) { ppc4xx_edac_printk(KERN_ERR, "%pOF: " @@ -1303,8 +1302,6 @@ static int ppc4xx_edac_probe(struct platform_device *op) goto fail1; } - ppc4xx_edac_instance++; - return 0; fail1: From patchwork Wed Sep 20 19:10:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142657 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4506201vqi; Wed, 20 Sep 2023 17:02:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE2OpLb+RbuhZMIn2emvzuRrcpJvyzFXNPhOYuHfMukgZfpjlK8eM8RpVDN3iQc4goN7AZK X-Received: by 2002:a05:6e02:1bce:b0:34c:f2cb:b2c with SMTP id x14-20020a056e021bce00b0034cf2cb0b2cmr5127529ilv.19.1695254527358; Wed, 20 Sep 2023 17:02:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695254527; cv=none; d=google.com; s=arc-20160816; b=qzeQNMh6gyBxBg4HhkVkLfJxPi1LMTLrllAWcAvG+N8q23mX11m842VSU+EC9imLAW sah3SNNa2ZDkpF+P3VUw5fpZiG/bY0myUjoV2StIxGHqruCAyMs03i+S6knnAUJCp2sH KFEngAk2wyjOE1JeAqQqRP+DqH4TgeTT3OakaLZgVXuQJvHcK9o2jvXBYnxO2WdJ0Vcm jvn7vcdapR5h/5tEVK5oS90sRkR81wj6XdmT8FOViVHP1QKm/JYTNSxkBhue4W3hemFE 83FipvyytLoue/5c9RE0mtwkbVfmPMVdyvsJMPTJLF12nW6xnvRQB8sq1ruQYvJdKZXB aJLA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZDWGOcB/XNLWBgvGUvlChtIdjFViSo8WAZuKFQ14Sow=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=RuXNiIJkZZRbWQWsBP3vdc4fsJgXx8ll5TJhexpS9f8plDWniXiNQl/LkhMdS1vkxH JQsw08PrFgFzk/fhB3fZQWvo7z0TdpNXhzg+OHjFLDr+TWlYOHCAkwf5QjUH5FDXv/Hm QKu1zCPlxKgm8NgNFL5aEw1A/MqPK9ThZ73DbLjMqevEMjZKOKWhUXeApB+0vG91jX6d oK+1S5J5WyKiaaPNvtD1NlyCEvW4ROpPFar1MfOamAm897BDRhqPHXuIhhhYyY328TXI 9wikC/cy8IG96oBJ7daY4u/Ev2lCdMmXCChbN9v5yXu6umWH55ApiVJEHNTL3M0Hxrpx YeGw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=YrsI0g48; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. [23.128.96.34]) by mx.google.com with ESMTPS id bw25-20020a056a00409900b00690dbcb75d8si222650pfb.386.2023.09.20.17.02.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 17:02:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) client-ip=23.128.96.34; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=YrsI0g48; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id DC05082BB1BC; Wed, 20 Sep 2023 12:12:50 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230113AbjITTMs (ORCPT + 27 others); Wed, 20 Sep 2023 15:12:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229832AbjITTMh (ORCPT ); Wed, 20 Sep 2023 15:12:37 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 89362F5; Wed, 20 Sep 2023 12:12:12 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-50307759b65so382986e87.0; Wed, 20 Sep 2023 12:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1695237131; x=1695841931; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZDWGOcB/XNLWBgvGUvlChtIdjFViSo8WAZuKFQ14Sow=; b=YrsI0g48ic1xez8i5oB1I4d6FaCyUQ138ZLmkXbVItsrNiShse2rINhYXQOXMaYdyW 6cynEcMjzHHS7T44P5v3IfSrcQCfERonOEt/ldZpvpUJb03/0edgTK0jXMpdZb9OoY9F lXEbSZSmoyWkoTdYwOHojRuzzUFNL3XmexlkoOyE0qhRBM/65DNNKLSDr3W3/OZOmN8e w2trrJjEQJrdDdDDjpq1xcbOwrscijKZBUZd/bip3g+vG4YMvm3FnOUap12Ln03FiKud 9t6FXwphV8oRQrJHy98lg0z/MDFURmM1zx0AyHHrlS4Ztiogoz3CoG7/g+HGX3EyFfZ1 d2MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1695237131; x=1695841931; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZDWGOcB/XNLWBgvGUvlChtIdjFViSo8WAZuKFQ14Sow=; b=eHjctkvfyja1KXXX5eMae0c7VnxiDZbZ8peqTS2uVDssq5Bno9epGyyZN0LC5d5tzu YoYDJnixFsVzpeY1kwOkNY93Yasi0zahbSqGtJxpRkeRobmoQvVrsqye5hL6MvsBVr/R HQp4LuSmLfMytRGoDsrbvCdEJfstfmOtkovjT7SFZptigKcjuKRazPCCwy4Hd15EsHa1 kjgWeUPAuxPxSNmHAYAITwdrdGW/HUH8uS8GokkW4I3WI3ErOrD+LnN8gVKq8nfLUqMI YO3hM6sUs/yrB8U2aGoNQ0EAwiyaA/d4htGJSctrDvDndIxQsQVsRAMtUeA1I2dXf30u HgDA== X-Gm-Message-State: AOJu0Yyo6re5i8KQAXYoVsnlkgbdm6TqT5D2qBUnRvKwDiJsrjFIEBq7 pA7KGWrsbs19xcrcXga+1sN+2beHxwc= X-Received: by 2002:ac2:4e8b:0:b0:503:442:5957 with SMTP id o11-20020ac24e8b000000b0050304425957mr3155014lfr.41.1695237130497; Wed, 20 Sep 2023 12:12:10 -0700 (PDT) Received: from localhost ([85.26.234.143]) by smtp.gmail.com with ESMTPSA id v26-20020ac2559a000000b0050331960776sm810496lfg.34.2023.09.20.12.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Sep 2023 12:12:09 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 16/20] EDAC/synopsys: Detach Zynq A05 DDRC support to separate driver Date: Wed, 20 Sep 2023 22:10:40 +0300 Message-ID: <20230920191059.28395-17-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:12:50 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777603211200103365 X-GMAIL-MSGID: 1777603211200103365 The synopsys_edac.c driver currently supports three memory-controllers: 1. Synopsys DW uMCTL2 DDRC v3.80 (with the ZynqMP-specific params). 2. Xilinx ZynqMP DDRC Synopsys DW uMCTL2 DDRC v2.40. 3. Xilinx Zynq A05 DDR controller. If the first two devices are based on the Synopsys DW uMCTL2 IP-cores (ZynqMP MC is based on the DW uMCTL2 v2.40) the later device has absolutely nothing in common with the Synopsys DW uMCTL2 DDR controllers: the CSRs map is absolutely different; it doesn't support IRQs unlike the Synopsys memory controllers. Having the driver to support so different devices caused implementing an additional level of abstraction, which will be a great deal of obstacle in about to be added comprehensive set of the Synopsys DDR-controller features (DW uCMTL2 IP-core parameters auto-detection, common SDRAM<->phys address translation, multi-ranked memory, ECC scrubber, individual IRQs, DFI alert_n IRQ, and so on). Moreover the original reason of having these devices support living in a single driver hasn't been introduced for all these years: the synopsys_edac.c driver currently supports only a single memory controller detected on the system. So in order to make the Synopsys driver ready for the new features added move the Xilinx Zynq A05 DDRC support into a separate driver: detach the Zynq-specific callbacks, init/probe/remove methods and move them into the new zynq_edac.c driver. The resultant driver will mostly look similar to the code submitted in the initial commit ae9b56e3996d ("EDAC, synps: Add EDAC support for zynq ddr ecc controller") except a few fixes added afterwards. Note several Zynq-specific macros have been used in the DW uMCTL2 DDRC-specific functions. These macros just for a mere coincident have values suitable for the DW uMCTL2 code but their names either partly or fully unrelated with the Synopsys memory controllers. Since these macros are now moved to another driver introduce a new Synopsys-specific ones and fix the places where the macros have been improperly utilized. Signed-off-by: Serge Semin --- Changelog v3: - Drop the no longer used "priv" pointer from the zynq_mc_init() function. (@tbot) --- MAINTAINERS | 1 + drivers/edac/Kconfig | 9 +- drivers/edac/Makefile | 1 + drivers/edac/synopsys_edac.c | 239 ++--------------- drivers/edac/zynq_edac.c | 501 +++++++++++++++++++++++++++++++++++ 5 files changed, 531 insertions(+), 220 deletions(-) create mode 100644 drivers/edac/zynq_edac.c diff --git a/MAINTAINERS b/MAINTAINERS index 53b7ca804465..bd03b98b5e47 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2977,6 +2977,7 @@ F: arch/arm/mach-zynq/ F: drivers/clocksource/timer-cadence-ttc.c F: drivers/cpuidle/cpuidle-zynq.c F: drivers/edac/synopsys_edac.c +F: drivers/edac/zynq_edac.c F: drivers/i2c/busses/i2c-cadence.c F: drivers/i2c/busses/i2c-xiic.c F: drivers/mmc/host/sdhci-of-arasan.c diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig index 110e99b86a66..eaac35c27e5c 100644 --- a/drivers/edac/Kconfig +++ b/drivers/edac/Kconfig @@ -487,7 +487,7 @@ config EDAC_ARMADA_XP config EDAC_SYNOPSYS tristate "Synopsys DDR Memory Controller" - depends on ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC + depends on ARCH_ZYNQMP || ARCH_INTEL_SOCFPGA || ARCH_MXC help Support for error detection and correction on the Synopsys DDR memory controller. @@ -561,4 +561,11 @@ config EDAC_NPCM error detection (in-line ECC in which a section 1/8th of the memory device used to store data is used for ECC storage). +config EDAC_ZYNQ + tristate "Xilinx Zynq A05 DDR Memory Controller" + depends on ARCH_ZYNQ || COMPILE_TEST + help + Support for error detection and correction on the Xilinx Zynq A05 + DDR memory controller. + endif # EDAC diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile index 61945d3113cc..4f85923e18ec 100644 --- a/drivers/edac/Makefile +++ b/drivers/edac/Makefile @@ -85,4 +85,5 @@ obj-$(CONFIG_EDAC_ASPEED) += aspeed_edac.o obj-$(CONFIG_EDAC_BLUEFIELD) += bluefield_edac.o obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o obj-$(CONFIG_EDAC_NPCM) += npcm_edac.o +obj-$(CONFIG_EDAC_ZYNQ) += zynq_edac.o obj-$(CONFIG_EDAC_ZYNQMP) += zynqmp_edac.o diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 62f498b6dfed..783a4df7eeac 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -30,68 +30,16 @@ #define SYNPS_EDAC_MOD_STRING "synps_edac" #define SYNPS_EDAC_MOD_VER "1" -/* Synopsys DDR memory controller registers that are relevant to ECC */ -#define CTRL_OFST 0x0 -#define T_ZQ_OFST 0xA4 - -/* ECC control register */ -#define ECC_CTRL_OFST 0xC4 -/* ECC log register */ -#define CE_LOG_OFST 0xC8 -/* ECC address register */ -#define CE_ADDR_OFST 0xCC -/* ECC data[31:0] register */ -#define CE_DATA_31_0_OFST 0xD0 - -/* Uncorrectable error info registers */ -#define UE_LOG_OFST 0xDC -#define UE_ADDR_OFST 0xE0 -#define UE_DATA_31_0_OFST 0xE4 - -#define STAT_OFST 0xF0 -#define SCRUB_OFST 0xF4 - -/* Control register bit field definitions */ -#define CTRL_BW_MASK 0xC -#define CTRL_BW_SHIFT 2 - -#define DDRCTL_WDTH_16 1 -#define DDRCTL_WDTH_32 0 - -/* ZQ register bit field definitions */ -#define T_ZQ_DDRMODE_MASK 0x2 - -/* ECC control register bit field definitions */ -#define ECC_CTRL_CLR_CE_ERR 0x2 -#define ECC_CTRL_CLR_UE_ERR 0x1 - -/* ECC correctable/uncorrectable error log register definitions */ -#define LOG_VALID 0x1 -#define CE_LOG_BITPOS_MASK 0xFE -#define CE_LOG_BITPOS_SHIFT 1 - -/* ECC correctable/uncorrectable error address register definitions */ -#define ADDR_COL_MASK 0xFFF -#define ADDR_ROW_MASK 0xFFFF000 -#define ADDR_ROW_SHIFT 12 -#define ADDR_BANK_MASK 0x70000000 -#define ADDR_BANK_SHIFT 28 - -/* ECC statistic register definitions */ -#define STAT_UECNT_MASK 0xFF -#define STAT_CECNT_MASK 0xFF00 -#define STAT_CECNT_SHIFT 8 - -/* ECC scrub register definitions */ -#define SCRUB_MODE_MASK 0x7 -#define SCRUB_MODE_SECDED 0x4 - /* DDR ECC Quirks */ #define DDR_ECC_INTR_SUPPORT BIT(0) #define DDR_ECC_DATA_POISON_SUPPORT BIT(1) #define SYNPS_ZYNQMP_IRQ_REGS BIT(2) -/* ZynqMP Enhanced DDR memory controller registers that are relevant to ECC */ +/* Synopsys DDR memory controller registers that are relevant to ECC */ + +/* DDRC Master 0 Register */ +#define DDR_MSTR_OFST 0x0 + /* ECC Configuration Registers */ #define ECC_CFG0_OFST 0x70 #define ECC_CFG1_OFST 0x74 @@ -135,16 +83,22 @@ #define ECC_ADDRMAP0_OFFSET 0x200 /* Control register bitfield definitions */ -#define ECC_CTRL_BUSWIDTH_MASK 0x3000 -#define ECC_CTRL_BUSWIDTH_SHIFT 12 +#define ECC_CTRL_CLR_CE_ERR BIT(0) +#define ECC_CTRL_CLR_UE_ERR BIT(1) #define ECC_CTRL_CLR_CE_ERRCNT BIT(2) #define ECC_CTRL_CLR_UE_ERRCNT BIT(3) /* DDR Control Register width definitions */ +#define DDR_MSTR_BUSWIDTH_MASK 0x3000 +#define DDR_MSTR_BUSWIDTH_SHIFT 12 #define DDRCTL_EWDTH_16 2 #define DDRCTL_EWDTH_32 1 #define DDRCTL_EWDTH_64 0 +/* ECC CFG0 register definitions */ +#define ECC_CFG0_MODE_MASK 0x7 +#define ECC_CFG0_MODE_SECDED 0x4 + /* ECC status register definitions */ #define ECC_STAT_UECNT_MASK 0xF0000 #define ECC_STAT_UECNT_SHIFT 16 @@ -342,61 +296,6 @@ struct synps_platform_data { int quirks; }; -/** - * zynq_get_error_info - Get the current ECC error info. - * @priv: DDR memory controller private instance data. - * - * Return: one if there is no error, otherwise zero. - */ -static int zynq_get_error_info(struct synps_edac_priv *priv) -{ - struct synps_ecc_status *p; - u32 regval, clearval = 0; - void __iomem *base; - - base = priv->baseaddr; - p = &priv->stat; - - regval = readl(base + STAT_OFST); - if (!regval) - return 1; - - p->ce_cnt = (regval & STAT_CECNT_MASK) >> STAT_CECNT_SHIFT; - p->ue_cnt = regval & STAT_UECNT_MASK; - - regval = readl(base + CE_LOG_OFST); - if (!(p->ce_cnt && (regval & LOG_VALID))) - goto ue_err; - - p->ceinfo.bitpos = (regval & CE_LOG_BITPOS_MASK) >> CE_LOG_BITPOS_SHIFT; - regval = readl(base + CE_ADDR_OFST); - p->ceinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; - p->ceinfo.col = regval & ADDR_COL_MASK; - p->ceinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; - p->ceinfo.data = readl(base + CE_DATA_31_0_OFST); - edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, - p->ceinfo.data); - clearval = ECC_CTRL_CLR_CE_ERR; - -ue_err: - regval = readl(base + UE_LOG_OFST); - if (!(p->ue_cnt && (regval & LOG_VALID))) - goto out; - - regval = readl(base + UE_ADDR_OFST); - p->ueinfo.row = (regval & ADDR_ROW_MASK) >> ADDR_ROW_SHIFT; - p->ueinfo.col = regval & ADDR_COL_MASK; - p->ueinfo.bank = (regval & ADDR_BANK_MASK) >> ADDR_BANK_SHIFT; - p->ueinfo.data = readl(base + UE_DATA_31_0_OFST); - clearval |= ECC_CTRL_CLR_UE_ERR; - -out: - writel(clearval, base + ECC_CTRL_OFST); - writel(0x0, base + ECC_CTRL_OFST); - - return 0; -} - /** * zynqmp_get_error_info - Get the current ECC error info. * @priv: DDR memory controller private instance data. @@ -615,37 +514,6 @@ static void check_errors(struct mem_ctl_info *mci) handle_error(mci, &priv->stat); } -/** - * zynq_get_dtype - Return the controller memory width. - * @base: DDR memory controller base address. - * - * Get the EDAC device type width appropriate for the current controller - * configuration. - * - * Return: a device type width enumeration. - */ -static enum dev_type zynq_get_dtype(const void __iomem *base) -{ - enum dev_type dt; - u32 width; - - width = readl(base + CTRL_OFST); - width = (width & CTRL_BW_MASK) >> CTRL_BW_SHIFT; - - switch (width) { - case DDRCTL_WDTH_16: - dt = DEV_X2; - break; - case DDRCTL_WDTH_32: - dt = DEV_X4; - break; - default: - dt = DEV_UNKNOWN; - } - - return dt; -} - /** * zynqmp_get_dtype - Return the controller memory width. * @base: DDR memory controller base address. @@ -659,7 +527,7 @@ static enum dev_type zynqmp_get_dtype(const void __iomem *base) { u32 regval; - regval = readl(base + CTRL_OFST); + regval = readl(base + DDR_MSTR_OFST); if (!(regval & MEM_TYPE_DDR4)) return DEV_UNKNOWN; @@ -678,30 +546,6 @@ static enum dev_type zynqmp_get_dtype(const void __iomem *base) return DEV_UNKNOWN; } -/** - * zynq_get_ecc_state - Return the controller ECC enable/disable status. - * @base: DDR memory controller base address. - * - * Get the ECC enable/disable status of the controller. - * - * Return: true if enabled, otherwise false. - */ -static bool zynq_get_ecc_state(void __iomem *base) -{ - enum dev_type dt; - u32 ecctype; - - dt = zynq_get_dtype(base); - if (dt == DEV_UNKNOWN) - return false; - - ecctype = readl(base + SCRUB_OFST) & SCRUB_MODE_MASK; - if ((ecctype == SCRUB_MODE_SECDED) && (dt == DEV_X2)) - return true; - - return false; -} - /** * zynqmp_get_ecc_state - Return the controller ECC enable/disable status. * @base: DDR memory controller base address. @@ -714,9 +558,9 @@ static bool zynqmp_get_ecc_state(void __iomem *base) { u32 regval; - regval = readl(base + ECC_CFG0_OFST) & SCRUB_MODE_MASK; + regval = readl(base + ECC_CFG0_OFST) & ECC_CFG0_MODE_MASK; - return (regval == SCRUB_MODE_SECDED); + return (regval == ECC_CFG0_MODE_SECDED); } /** @@ -733,30 +577,6 @@ static u32 get_memsize(void) return inf.totalram * inf.mem_unit; } -/** - * zynq_get_mtype - Return the controller memory type. - * @base: Synopsys ECC status structure. - * - * Get the EDAC memory type appropriate for the current controller - * configuration. - * - * Return: a memory type enumeration. - */ -static enum mem_type zynq_get_mtype(const void __iomem *base) -{ - enum mem_type mt; - u32 memtype; - - memtype = readl(base + T_ZQ_OFST); - - if (memtype & T_ZQ_DDRMODE_MASK) - mt = MEM_DDR3; - else - mt = MEM_DDR2; - - return mt; -} - /** * zynqmp_get_mtype - Returns controller memory type. * @base: Synopsys ECC status structure. @@ -771,7 +591,7 @@ static enum mem_type zynqmp_get_mtype(const void __iomem *base) enum mem_type mt; u32 memtype; - memtype = readl(base + CTRL_OFST); + memtype = readl(base + DDR_MSTR_OFST); if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3)) mt = MEM_DDR3; @@ -883,14 +703,6 @@ static int setup_irq(struct mem_ctl_info *mci, return 0; } -static const struct synps_platform_data zynq_edac_def = { - .get_error_info = zynq_get_error_info, - .get_mtype = zynq_get_mtype, - .get_dtype = zynq_get_dtype, - .get_ecc_state = zynq_get_ecc_state, - .quirks = 0, -}; - static const struct synps_platform_data zynqmp_edac_def = { .get_error_info = zynqmp_get_error_info, .get_mtype = zynqmp_get_mtype, @@ -917,10 +729,6 @@ static const struct synps_platform_data synopsys_edac_def = { static const struct of_device_id synps_edac_match[] = { - { - .compatible = "xlnx,zynq-ddrc-a05", - .data = (void *)&zynq_edac_def - }, { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = (void *)&zynqmp_edac_def @@ -1142,8 +950,8 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) u32 width, memtype; int index; - memtype = readl(priv->baseaddr + CTRL_OFST); - width = (memtype & ECC_CTRL_BUSWIDTH_MASK) >> ECC_CTRL_BUSWIDTH_SHIFT; + memtype = readl(priv->baseaddr + DDR_MSTR_OFST); + width = (memtype & DDR_MSTR_BUSWIDTH_MASK) >> DDR_MSTR_BUSWIDTH_SHIFT; priv->col_shift[0] = 0; priv->col_shift[1] = 1; @@ -1338,7 +1146,7 @@ static int mc_probe(struct platform_device *pdev) layers[1].size = SYNPS_EDAC_NR_CHANS; layers[1].is_virt_csrow = false; - mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, + mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, sizeof(struct synps_edac_priv)); if (!mci) { edac_printk(KERN_ERR, EDAC_MC, @@ -1380,13 +1188,6 @@ static int mc_probe(struct platform_device *pdev) setup_address_map(priv); #endif - /* - * Start capturing the correctable and uncorrectable errors. A write of - * 0 starts the counters. - */ - if (!(priv->p_data->quirks & DDR_ECC_INTR_SUPPORT)) - writel(0x0, baseaddr + ECC_CTRL_OFST); - return rc; free_edac_mc: diff --git a/drivers/edac/zynq_edac.c b/drivers/edac/zynq_edac.c new file mode 100644 index 000000000000..0781e69e019c --- /dev/null +++ b/drivers/edac/zynq_edac.c @@ -0,0 +1,501 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Zynq DDR ECC Driver + * This driver is based on ppc4xx_edac.c drivers + * + * Copyright (C) 2012 - 2014 Xilinx, Inc. + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "edac_module.h" + +/* Number of cs_rows needed per memory controller */ +#define ZYNQ_EDAC_NR_CSROWS 1 + +/* Number of channels per memory controller */ +#define ZYNQ_EDAC_NR_CHANS 1 + +/* Granularity of reported error in bytes */ +#define ZYNQ_EDAC_ERR_GRAIN 1 + +#define ZYNQ_EDAC_MSG_SIZE 256 + +#define ZYNQ_EDAC_MOD_STRING "zynq_edac" +#define ZYNQ_EDAC_MOD_VER "1" + +/* Zynq DDR memory controller ECC registers */ +#define ZYNQ_CTRL_OFST 0x0 +#define ZYNQ_T_ZQ_OFST 0xA4 + +/* ECC control register */ +#define ZYNQ_ECC_CTRL_OFST 0xC4 +/* ECC log register */ +#define ZYNQ_CE_LOG_OFST 0xC8 +/* ECC address register */ +#define ZYNQ_CE_ADDR_OFST 0xCC +/* ECC data[31:0] register */ +#define ZYNQ_CE_DATA_31_0_OFST 0xD0 + +/* Uncorrectable error info registers */ +#define ZYNQ_UE_LOG_OFST 0xDC +#define ZYNQ_UE_ADDR_OFST 0xE0 +#define ZYNQ_UE_DATA_31_0_OFST 0xE4 + +#define ZYNQ_STAT_OFST 0xF0 +#define ZYNQ_SCRUB_OFST 0xF4 + +/* Control register bit field definitions */ +#define ZYNQ_CTRL_BW_MASK 0xC +#define ZYNQ_CTRL_BW_SHIFT 2 + +#define ZYNQ_DDRCTL_WDTH_16 1 +#define ZYNQ_DDRCTL_WDTH_32 0 + +/* ZQ register bit field definitions */ +#define ZYNQ_T_ZQ_DDRMODE_MASK 0x2 + +/* ECC control register bit field definitions */ +#define ZYNQ_ECC_CTRL_CLR_CE_ERR 0x2 +#define ZYNQ_ECC_CTRL_CLR_UE_ERR 0x1 + +/* ECC correctable/uncorrectable error log register definitions */ +#define ZYNQ_LOG_VALID 0x1 +#define ZYNQ_CE_LOG_BITPOS_MASK 0xFE +#define ZYNQ_CE_LOG_BITPOS_SHIFT 1 + +/* ECC correctable/uncorrectable error address register definitions */ +#define ZYNQ_ADDR_COL_MASK 0xFFF +#define ZYNQ_ADDR_ROW_MASK 0xFFFF000 +#define ZYNQ_ADDR_ROW_SHIFT 12 +#define ZYNQ_ADDR_BANK_MASK 0x70000000 +#define ZYNQ_ADDR_BANK_SHIFT 28 + +/* ECC statistic register definitions */ +#define ZYNQ_STAT_UECNT_MASK 0xFF +#define ZYNQ_STAT_CECNT_MASK 0xFF00 +#define ZYNQ_STAT_CECNT_SHIFT 8 + +/* ECC scrub register definitions */ +#define ZYNQ_SCRUB_MODE_MASK 0x7 +#define ZYNQ_SCRUB_MODE_SECDED 0x4 + +/** + * struct zynq_ecc_error_info - ECC error log information. + * @row: Row number. + * @col: Column number. + * @bank: Bank number. + * @bitpos: Bit position. + * @data: Data causing the error. + */ +struct zynq_ecc_error_info { + u32 row; + u32 col; + u32 bank; + u32 bitpos; + u32 data; +}; + +/** + * struct zynq_ecc_status - ECC status information to report. + * @ce_cnt: Correctable error count. + * @ue_cnt: Uncorrectable error count. + * @ceinfo: Correctable error log information. + * @ueinfo: Uncorrectable error log information. + */ +struct zynq_ecc_status { + u32 ce_cnt; + u32 ue_cnt; + struct zynq_ecc_error_info ceinfo; + struct zynq_ecc_error_info ueinfo; +}; + +/** + * struct zynq_edac_priv - DDR memory controller private instance data. + * @baseaddr: Base address of the DDR controller. + * @message: Buffer for framing the event specific info. + * @stat: ECC status information. + */ +struct zynq_edac_priv { + void __iomem *baseaddr; + char message[ZYNQ_EDAC_MSG_SIZE]; + struct zynq_ecc_status stat; +}; + +/** + * zynq_get_error_info - Get the current ECC error info. + * @priv: DDR memory controller private instance data. + * + * Return: one if there is no error, otherwise zero. + */ +static int zynq_get_error_info(struct zynq_edac_priv *priv) +{ + struct zynq_ecc_status *p; + u32 regval, clearval = 0; + void __iomem *base; + + base = priv->baseaddr; + p = &priv->stat; + + regval = readl(base + ZYNQ_STAT_OFST); + if (!regval) + return 1; + + p->ce_cnt = (regval & ZYNQ_STAT_CECNT_MASK) >> ZYNQ_STAT_CECNT_SHIFT; + p->ue_cnt = regval & ZYNQ_STAT_UECNT_MASK; + + regval = readl(base + ZYNQ_CE_LOG_OFST); + if (!(p->ce_cnt && (regval & ZYNQ_LOG_VALID))) + goto ue_err; + + p->ceinfo.bitpos = (regval & ZYNQ_CE_LOG_BITPOS_MASK) >> ZYNQ_CE_LOG_BITPOS_SHIFT; + regval = readl(base + ZYNQ_CE_ADDR_OFST); + p->ceinfo.row = (regval & ZYNQ_ADDR_ROW_MASK) >> ZYNQ_ADDR_ROW_SHIFT; + p->ceinfo.col = regval & ZYNQ_ADDR_COL_MASK; + p->ceinfo.bank = (regval & ZYNQ_ADDR_BANK_MASK) >> ZYNQ_ADDR_BANK_SHIFT; + p->ceinfo.data = readl(base + ZYNQ_CE_DATA_31_0_OFST); + edac_dbg(3, "CE bit position: %d data: %d\n", p->ceinfo.bitpos, + p->ceinfo.data); + clearval = ZYNQ_ECC_CTRL_CLR_CE_ERR; + +ue_err: + regval = readl(base + ZYNQ_UE_LOG_OFST); + if (!(p->ue_cnt && (regval & ZYNQ_LOG_VALID))) + goto out; + + regval = readl(base + ZYNQ_UE_ADDR_OFST); + p->ueinfo.row = (regval & ZYNQ_ADDR_ROW_MASK) >> ZYNQ_ADDR_ROW_SHIFT; + p->ueinfo.col = regval & ZYNQ_ADDR_COL_MASK; + p->ueinfo.bank = (regval & ZYNQ_ADDR_BANK_MASK) >> ZYNQ_ADDR_BANK_SHIFT; + p->ueinfo.data = readl(base + ZYNQ_UE_DATA_31_0_OFST); + clearval |= ZYNQ_ECC_CTRL_CLR_UE_ERR; + +out: + writel(clearval, base + ZYNQ_ECC_CTRL_OFST); + writel(0x0, base + ZYNQ_ECC_CTRL_OFST); + + return 0; +} + +/** + * handle_error - Handle Correctable and Uncorrectable errors. + * @mci: EDAC memory controller instance. + * @p: Zynq ECC status structure. + * + * Handles ECC correctable and uncorrectable errors. + */ +static void zynq_handle_error(struct mem_ctl_info *mci, struct zynq_ecc_status *p) +{ + struct zynq_edac_priv *priv = mci->pvt_info; + struct zynq_ecc_error_info *pinf; + + if (p->ce_cnt) { + pinf = &p->ceinfo; + + snprintf(priv->message, ZYNQ_EDAC_MSG_SIZE, + "Row %d Bank %d Col %d Bit %d Data 0x%08x", + pinf->row, pinf->bank, pinf->col, + pinf->bitpos, pinf->data); + + edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, + p->ce_cnt, 0, 0, 0, 0, 0, -1, + priv->message, ""); + } + + if (p->ue_cnt) { + pinf = &p->ueinfo; + + snprintf(priv->message, ZYNQ_EDAC_MSG_SIZE, + "Row %d Bank %d Col %d", + pinf->row, pinf->bank, pinf->col); + + edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, + p->ue_cnt, 0, 0, 0, 0, 0, -1, + priv->message, ""); + } + + memset(p, 0, sizeof(*p)); +} + +/** + * check_errors - Check controller for ECC errors. + * @mci: EDAC memory controller instance. + * + * Check and post ECC errors. Called by the polling thread. + */ +static void zynq_check_errors(struct mem_ctl_info *mci) +{ + struct zynq_edac_priv *priv = mci->pvt_info; + int status; + + status = zynq_get_error_info(priv); + if (status) + return; + + zynq_handle_error(mci, &priv->stat); +} + +/** + * zynq_get_dtype - Return the controller memory width. + * @base: DDR memory controller base address. + * + * Get the EDAC device type width appropriate for the current controller + * configuration. + * + * Return: a device type width enumeration. + */ +static enum dev_type zynq_get_dtype(const void __iomem *base) +{ + enum dev_type dt; + u32 width; + + width = readl(base + ZYNQ_CTRL_OFST); + width = (width & ZYNQ_CTRL_BW_MASK) >> ZYNQ_CTRL_BW_SHIFT; + + switch (width) { + case ZYNQ_DDRCTL_WDTH_16: + dt = DEV_X2; + break; + case ZYNQ_DDRCTL_WDTH_32: + dt = DEV_X4; + break; + default: + dt = DEV_UNKNOWN; + } + + return dt; +} + +/** + * zynq_get_ecc_state - Return the controller ECC enable/disable status. + * @base: DDR memory controller base address. + * + * Get the ECC enable/disable status of the controller. + * + * Return: true if enabled, otherwise false. + */ +static bool zynq_get_ecc_state(void __iomem *base) +{ + enum dev_type dt; + u32 ecctype; + + dt = zynq_get_dtype(base); + if (dt == DEV_UNKNOWN) + return false; + + ecctype = readl(base + ZYNQ_SCRUB_OFST) & ZYNQ_SCRUB_MODE_MASK; + if ((ecctype == ZYNQ_SCRUB_MODE_SECDED) && (dt == DEV_X2)) + return true; + + return false; +} + +/** + * zynq_get_memsize - Read the size of the attached memory device. + * + * Return: the memory size in bytes. + */ +static u32 zynq_get_memsize(void) +{ + struct sysinfo inf; + + si_meminfo(&inf); + + return inf.totalram * inf.mem_unit; +} + +/** + * zynq_get_mtype - Return the controller memory type. + * @base: Zynq ECC status structure. + * + * Get the EDAC memory type appropriate for the current controller + * configuration. + * + * Return: a memory type enumeration. + */ +static enum mem_type zynq_get_mtype(const void __iomem *base) +{ + enum mem_type mt; + u32 memtype; + + memtype = readl(base + ZYNQ_T_ZQ_OFST); + + if (memtype & ZYNQ_T_ZQ_DDRMODE_MASK) + mt = MEM_DDR3; + else + mt = MEM_DDR2; + + return mt; +} + +/** + * zynq_init_csrows - Initialize the csrow data. + * @mci: EDAC memory controller instance. + * + * Initialize the chip select rows associated with the EDAC memory + * controller instance. + */ +static void zynq_init_csrows(struct mem_ctl_info *mci) +{ + struct zynq_edac_priv *priv = mci->pvt_info; + struct csrow_info *csi; + struct dimm_info *dimm; + u32 size, row; + int j; + + for (row = 0; row < mci->nr_csrows; row++) { + csi = mci->csrows[row]; + size = zynq_get_memsize(); + + for (j = 0; j < csi->nr_channels; j++) { + dimm = csi->channels[j]->dimm; + dimm->edac_mode = EDAC_SECDED; + dimm->mtype = zynq_get_mtype(priv->baseaddr); + dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; + dimm->grain = ZYNQ_EDAC_ERR_GRAIN; + dimm->dtype = zynq_get_dtype(priv->baseaddr); + } + } +} + +/** + * zynq_mc_init - Initialize one driver instance. + * @mci: EDAC memory controller instance. + * @pdev: platform device. + * + * Perform initialization of the EDAC memory controller instance and + * related driver-private data associated with the memory controller the + * instance is bound to. + */ +static void zynq_mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) +{ + mci->pdev = &pdev->dev; + platform_set_drvdata(pdev, mci); + + /* Initialize controller capabilities and configuration */ + mci->mtype_cap = MEM_FLAG_DDR3 | MEM_FLAG_DDR2; + mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED; + mci->scrub_cap = SCRUB_FLAG_HW_SRC; + mci->scrub_mode = SCRUB_NONE; + + mci->edac_cap = EDAC_FLAG_SECDED; + mci->ctl_name = "zynq_ddr_controller"; + mci->dev_name = ZYNQ_EDAC_MOD_STRING; + mci->mod_name = ZYNQ_EDAC_MOD_VER; + + edac_op_state = EDAC_OPSTATE_POLL; + mci->edac_check = zynq_check_errors; + + mci->ctl_page_to_phys = NULL; + + zynq_init_csrows(mci); +} + +/** + * zynq_mc_probe - Check controller and bind driver. + * @pdev: platform device. + * + * Probe a specific controller instance for binding with the driver. + * + * Return: 0 if the controller instance was successfully bound to the + * driver; otherwise, < 0 on error. + */ +static int zynq_mc_probe(struct platform_device *pdev) +{ + struct edac_mc_layer layers[2]; + struct zynq_edac_priv *priv; + struct mem_ctl_info *mci; + void __iomem *baseaddr; + int rc; + + baseaddr = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(baseaddr)) + return PTR_ERR(baseaddr); + + if (!zynq_get_ecc_state(baseaddr)) { + edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); + return -ENXIO; + } + + layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; + layers[0].size = ZYNQ_EDAC_NR_CSROWS; + layers[0].is_virt_csrow = true; + layers[1].type = EDAC_MC_LAYER_CHANNEL; + layers[1].size = ZYNQ_EDAC_NR_CHANS; + layers[1].is_virt_csrow = false; + + mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, + sizeof(struct zynq_edac_priv)); + if (!mci) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed memory allocation for mc instance\n"); + return -ENOMEM; + } + + priv = mci->pvt_info; + priv->baseaddr = baseaddr; + + zynq_mc_init(mci, pdev); + + rc = edac_mc_add_mc(mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, + "Failed to register with EDAC core\n"); + goto free_edac_mc; + } + + /* + * Start capturing the correctable and uncorrectable errors. A write of + * 0 starts the counters. + */ + writel(0x0, baseaddr + ZYNQ_ECC_CTRL_OFST); + + return 0; + +free_edac_mc: + edac_mc_free(mci); + + return rc; +} + +/** + * zynq_mc_remove - Unbind driver from controller. + * @pdev: Platform device. + * + * Return: Unconditionally 0 + */ +static int zynq_mc_remove(struct platform_device *pdev) +{ + struct mem_ctl_info *mci = platform_get_drvdata(pdev); + + edac_mc_del_mc(&pdev->dev); + edac_mc_free(mci); + + return 0; +} + +static const struct of_device_id zynq_edac_match[] = { + { .compatible = "xlnx,zynq-ddrc-a05" }, + {} +}; +MODULE_DEVICE_TABLE(of, zynq_edac_match); + +static struct platform_driver zynq_edac_mc_driver = { + .driver = { + .name = "zynq-edac", + .of_match_table = zynq_edac_match, + }, + .probe = zynq_mc_probe, + .remove = zynq_mc_remove, +}; +module_platform_driver(zynq_edac_mc_driver); + +MODULE_AUTHOR("Xilinx Inc"); +MODULE_DESCRIPTION("Zynq DDR ECC driver"); +MODULE_LICENSE("GPL v2"); From patchwork Wed Sep 20 19:10:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142633 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4471295vqi; Wed, 20 Sep 2023 15:41:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHqrZDaf7bX0lNvQOFK0fNP078D5ldEonMdF72738EvSgZ1LMSwfqK/S0fC+1c4GCshmE/o X-Received: by 2002:a05:6a20:8413:b0:149:700e:f50a with SMTP id c19-20020a056a20841300b00149700ef50amr9956069pzd.29.1695249680959; Wed, 20 Sep 2023 15:41:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695249680; cv=none; d=google.com; s=arc-20160816; b=sJd44OCbihy0lwZTAy0OxWUeLxg3e3OfN5Gbt3WSs5iKX4GzEfXPlx2sHtXSnVJ05D gTW1AIYx8qLd0gGyaS+iQ66IGc4gti3gN1Ar7aTy4zaGacusWqTMQa+Ybe8k+VbsAHtU QI7Dj9OvtZ0EB3XEO/+QzThHXUTu3U1ePfkvdW7Pk9reBRUSgFELa9BWWKPM/FKeYxXm a+/T7VW7qARDIqy9W3uXRKoYbhhczFiDjAJnx0Tty4dbKBs7dOXVI8KQAI1UarZNr0b5 sWsTLteZPyUfJFx0LktP8OoFUVmtL3b1uObgtIT1uUMS00NrbuWuF5U2cPaPpGa2+jY4 MJdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PfDjZiE6WtfVCxrr3EXQZanb/Ejq/36l5KB3TsJFTIM=; fh=Dnqcu1G7YxMiPJ+rEGjOOR/MtvfjezykDSRJXQQtmAE=; b=Qe8twaQWDIPCtvu8DgniiqxSL/FhJnpqja378ysXwfYIF81dV8WVr81UgbWrL/L/K2 m7QD7JJQmrkkQ9j9bUwXXbhMBOl2UxaryKWSQ4ZukdswyN4M0DR7qeKo/uR0DWf2N32a pYZ3Gcrah2ly7UM/B0r2Sx904sQYLVtSZOMb80wY31BetqoxTsuO9yOvLaYyvzwQh0H8 0P/DiKgotHZlRK+d8vuKmz2AkQxoAw/J0hO0dSpblTiXtpFj5bMn6DLsNyIweB9B9+H3 LU5ercy545xJvohxx2W3h1EDSYmdsuQoGETlNpFn0gP9o9kWHVNjvnPJWHiHffXtzIA+ No7g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="HvQRQYi/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from howler.vger.email (howler.vger.email. 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All the currently available IP-core revisions have got almost the same ECC and main part of the DDR-config CSRs map. Thus there is no point in supporting the no longer used internal abstraction layer like the callbacks responsible for getting the ECC errors info, memory and device types, ECC state. All of that data can be retrieved in the same way from all the Synopys DW uMCTL2 DDR controller versions. Similarly there is no longer need in the DDR_ECC_INTR_SUPPORT and DDR_ECC_DATA_POISON_SUPPORT quirk flags since DW uMCTL2 always supports IRQs and data poisoning (as long as the ECC is supported). Drop that infrastructure for good then. While at it move the module device table to being defined at the bottom of the file, above the platform driver descriptor definition. Signed-off-by: Serge Semin --- Changelog v2: - Drop the no longer used "priv" pointer from the mc_init() function. (@tbot) --- drivers/edac/synopsys_edac.c | 192 ++++++++++------------------------- 1 file changed, 51 insertions(+), 141 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 783a4df7eeac..655a32792883 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -31,9 +31,7 @@ #define SYNPS_EDAC_MOD_VER "1" /* DDR ECC Quirks */ -#define DDR_ECC_INTR_SUPPORT BIT(0) -#define DDR_ECC_DATA_POISON_SUPPORT BIT(1) -#define SYNPS_ZYNQMP_IRQ_REGS BIT(2) +#define SYNPS_ZYNQMP_IRQ_REGS BIT(0) /* Synopsys DDR memory controller registers that are relevant to ECC */ @@ -281,28 +279,20 @@ struct synps_edac_priv { }; /** - * struct synps_platform_data - synps platform data structure. - * @get_error_info: Get EDAC error info. - * @get_mtype: Get mtype. - * @get_dtype: Get dtype. - * @get_ecc_state: Get ECC state. - * @quirks: To differentiate IPs. + * struct synps_platform_data - Synopsys uMCTL2 DDRC platform data. + * @quirks: IP-core specific quirks. */ struct synps_platform_data { - int (*get_error_info)(struct synps_edac_priv *priv); - enum mem_type (*get_mtype)(const void __iomem *base); - enum dev_type (*get_dtype)(const void __iomem *base); - bool (*get_ecc_state)(void __iomem *base); - int quirks; + u32 quirks; }; /** - * zynqmp_get_error_info - Get the current ECC error info. + * synps_get_error_info - Get the current ECC error info. * @priv: DDR memory controller private instance data. * * Return: one if there is no error otherwise returns zero. */ -static int zynqmp_get_error_info(struct synps_edac_priv *priv) +static int synps_get_error_info(struct synps_edac_priv *priv) { struct synps_ecc_status *p; u32 regval, clearval; @@ -376,17 +366,11 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) if (p->ce_cnt) { pinf = &p->ceinfo; - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "Row %d Col %d Bank %d Bank Group %d Bit %d Data 0x%08x", - pinf->row, pinf->col, pinf->bank, pinf->bankgrp, - pinf->bitpos, pinf->data); - } else { - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "Row %d Bank %d Col %d Bit: %d Data: 0x%08x", - pinf->row, pinf->bank, pinf->col, - pinf->bitpos, pinf->data); - } + + snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + "Row %d Col %d Bank %d Bank Group %d Bit %d Data 0x%08x", + pinf->row, pinf->col, pinf->bank, pinf->bankgrp, + pinf->bitpos, pinf->data); edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, p->ce_cnt, 0, 0, 0, 0, 0, -1, @@ -395,15 +379,10 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) if (p->ue_cnt) { pinf = &p->ueinfo; - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "Row %d Col %d Bank %d Bank Group %d", - pinf->row, pinf->col, pinf->bank, pinf->bankgrp); - } else { - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, - "Row %d Bank %d Col %d", - pinf->row, pinf->bank, pinf->col); - } + + snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + "Row %d Col %d Bank %d Bank Group %d", + pinf->row, pinf->col, pinf->bank, pinf->bankgrp); edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, p->ue_cnt, 0, 0, 0, 0, 0, -1, @@ -465,13 +444,11 @@ static void disable_intr(struct synps_edac_priv *priv) */ static irqreturn_t intr_handler(int irq, void *dev_id) { - const struct synps_platform_data *p_data; struct mem_ctl_info *mci = dev_id; struct synps_edac_priv *priv; int status, regval; priv = mci->pvt_info; - p_data = priv->p_data; if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); @@ -480,7 +457,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id) return IRQ_NONE; } - status = p_data->get_error_info(priv); + status = synps_get_error_info(priv); if (status) return IRQ_NONE; @@ -493,29 +470,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id) } /** - * check_errors - Check controller for ECC errors. - * @mci: EDAC memory controller instance. - * - * Check and post ECC errors. Called by the polling thread. - */ -static void check_errors(struct mem_ctl_info *mci) -{ - const struct synps_platform_data *p_data; - struct synps_edac_priv *priv; - int status; - - priv = mci->pvt_info; - p_data = priv->p_data; - - status = p_data->get_error_info(priv); - if (status) - return; - - handle_error(mci, &priv->stat); -} - -/** - * zynqmp_get_dtype - Return the controller memory width. + * synps_get_dtype - Return the controller memory width. * @base: DDR memory controller base address. * * Get the EDAC device type width appropriate for the current controller @@ -523,7 +478,7 @@ static void check_errors(struct mem_ctl_info *mci) * * Return: a device type width enumeration. */ -static enum dev_type zynqmp_get_dtype(const void __iomem *base) +static enum dev_type synps_get_dtype(const void __iomem *base) { u32 regval; @@ -547,14 +502,14 @@ static enum dev_type zynqmp_get_dtype(const void __iomem *base) } /** - * zynqmp_get_ecc_state - Return the controller ECC enable/disable status. + * synps_get_ecc_state - Return the controller ECC enable/disable status. * @base: DDR memory controller base address. * * Get the ECC enable/disable status for the controller. * * Return: a ECC status boolean i.e true/false - enabled/disabled. */ -static bool zynqmp_get_ecc_state(void __iomem *base) +static bool synps_get_ecc_state(void __iomem *base) { u32 regval; @@ -578,7 +533,7 @@ static u32 get_memsize(void) } /** - * zynqmp_get_mtype - Returns controller memory type. + * synps_get_mtype - Returns controller memory type. * @base: Synopsys ECC status structure. * * Get the EDAC memory type appropriate for the current controller @@ -586,7 +541,7 @@ static u32 get_memsize(void) * * Return: a memory type enumeration. */ -static enum mem_type zynqmp_get_mtype(const void __iomem *base) +static enum mem_type synps_get_mtype(const void __iomem *base) { enum mem_type mt; u32 memtype; @@ -615,14 +570,11 @@ static enum mem_type zynqmp_get_mtype(const void __iomem *base) static void init_csrows(struct mem_ctl_info *mci) { struct synps_edac_priv *priv = mci->pvt_info; - const struct synps_platform_data *p_data; struct csrow_info *csi; struct dimm_info *dimm; u32 size, row; int j; - p_data = priv->p_data; - for (row = 0; row < mci->nr_csrows; row++) { csi = mci->csrows[row]; size = get_memsize(); @@ -630,10 +582,10 @@ static void init_csrows(struct mem_ctl_info *mci) for (j = 0; j < csi->nr_channels; j++) { dimm = csi->channels[j]->dimm; dimm->edac_mode = EDAC_SECDED; - dimm->mtype = p_data->get_mtype(priv->baseaddr); + dimm->mtype = synps_get_mtype(priv->baseaddr); dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; dimm->grain = SYNPS_EDAC_ERR_GRAIN; - dimm->dtype = p_data->get_dtype(priv->baseaddr); + dimm->dtype = synps_get_dtype(priv->baseaddr); } } } @@ -649,10 +601,7 @@ static void init_csrows(struct mem_ctl_info *mci) */ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) { - struct synps_edac_priv *priv; - mci->pdev = &pdev->dev; - priv = mci->pvt_info; platform_set_drvdata(pdev, mci); /* Initialize controller capabilities and configuration */ @@ -666,12 +615,7 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) mci->dev_name = SYNPS_EDAC_MOD_STRING; mci->mod_name = SYNPS_EDAC_MOD_VER; - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { - edac_op_state = EDAC_OPSTATE_INT; - } else { - edac_op_state = EDAC_OPSTATE_POLL; - mci->edac_check = check_errors; - } + edac_op_state = EDAC_OPSTATE_INT; mci->ctl_page_to_phys = NULL; @@ -703,47 +647,6 @@ static int setup_irq(struct mem_ctl_info *mci, return 0; } -static const struct synps_platform_data zynqmp_edac_def = { - .get_error_info = zynqmp_get_error_info, - .get_mtype = zynqmp_get_mtype, - .get_dtype = zynqmp_get_dtype, - .get_ecc_state = zynqmp_get_ecc_state, - .quirks = (DDR_ECC_INTR_SUPPORT | SYNPS_ZYNQMP_IRQ_REGS -#ifdef CONFIG_EDAC_DEBUG - | DDR_ECC_DATA_POISON_SUPPORT -#endif - ), -}; - -static const struct synps_platform_data synopsys_edac_def = { - .get_error_info = zynqmp_get_error_info, - .get_mtype = zynqmp_get_mtype, - .get_dtype = zynqmp_get_dtype, - .get_ecc_state = zynqmp_get_ecc_state, - .quirks = (DDR_ECC_INTR_SUPPORT -#ifdef CONFIG_EDAC_DEBUG - | DDR_ECC_DATA_POISON_SUPPORT -#endif - ), -}; - - -static const struct of_device_id synps_edac_match[] = { - { - .compatible = "xlnx,zynqmp-ddrc-2.40a", - .data = (void *)&zynqmp_edac_def - }, - { - .compatible = "snps,ddrc-3.80a", - .data = (void *)&synopsys_edac_def - }, - { - /* end of table */ - } -}; - -MODULE_DEVICE_TABLE(of, synps_edac_match); - #ifdef CONFIG_EDAC_DEBUG /** @@ -1134,7 +1037,7 @@ static int mc_probe(struct platform_device *pdev) if (!p_data) return -ENODEV; - if (!p_data->get_ecc_state(baseaddr)) { + if (!synps_get_ecc_state(baseaddr)) { edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); return -ENXIO; } @@ -1161,11 +1064,9 @@ static int mc_probe(struct platform_device *pdev) mc_init(mci, pdev); - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) { - rc = setup_irq(mci, pdev); - if (rc) - goto free_edac_mc; - } + rc = setup_irq(mci, pdev); + if (rc) + goto free_edac_mc; rc = edac_mc_add_mc(mci); if (rc) { @@ -1175,17 +1076,13 @@ static int mc_probe(struct platform_device *pdev) } #ifdef CONFIG_EDAC_DEBUG - if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) { - rc = edac_create_sysfs_attributes(mci); - if (rc) { - edac_printk(KERN_ERR, EDAC_MC, - "Failed to create sysfs entries\n"); - goto free_edac_mc; - } + rc = edac_create_sysfs_attributes(mci); + if (rc) { + edac_printk(KERN_ERR, EDAC_MC, "Failed to create sysfs entries\n"); + goto free_edac_mc; } - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) - setup_address_map(priv); + setup_address_map(priv); #endif return rc; @@ -1207,12 +1104,10 @@ static int mc_remove(struct platform_device *pdev) struct mem_ctl_info *mci = platform_get_drvdata(pdev); struct synps_edac_priv *priv = mci->pvt_info; - if (priv->p_data->quirks & DDR_ECC_INTR_SUPPORT) - disable_intr(priv); + disable_intr(priv); #ifdef CONFIG_EDAC_DEBUG - if (priv->p_data->quirks & DDR_ECC_DATA_POISON_SUPPORT) - edac_remove_sysfs_attributes(mci); + edac_remove_sysfs_attributes(mci); #endif edac_mc_del_mc(&pdev->dev); @@ -1221,6 +1116,21 @@ static int mc_remove(struct platform_device *pdev) return 0; } +static const struct synps_platform_data zynqmp_edac_def = { + .quirks = SYNPS_ZYNQMP_IRQ_REGS, +}; + +static const struct synps_platform_data synopsys_edac_def = { + .quirks = 0, +}; + +static const struct of_device_id synps_edac_match[] = { + { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = &zynqmp_edac_def }, + { .compatible = "snps,ddrc-3.80a", .data = &synopsys_edac_def }, + { } +}; +MODULE_DEVICE_TABLE(of, synps_edac_match); + static struct platform_driver synps_edac_mc_driver = { .driver = { .name = "synopsys-edac", From patchwork Wed Sep 20 19:10:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142607 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4430570vqi; Wed, 20 Sep 2023 14:15:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHwmWNGwrtquTquqTqVG/RvkcD4KPEBXxBoCNtt25IQMhO6xWrkoS73ITELp65zIwbLzNSA X-Received: by 2002:a05:6e02:4c9:b0:350:f0bb:6a39 with SMTP id f9-20020a056e0204c900b00350f0bb6a39mr3558387ils.10.1695244531285; Wed, 20 Sep 2023 14:15:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1695244531; cv=none; d=google.com; s=arc-20160816; b=DbaJPiq7dZxYSl5zG+3kL6a4kcqRTuvDo6PlE+8R3PePTemMWm1mx5oHeda84tLfGo LVKzl+wVVee4m00OLiEQ+Stln9R/SpruqQDptAEXap5TmQ0zcK5jixUMpJpida4Ahry9 eMVuIn0OAWr9EU41Keb8K3nmMFhJp6LmOuTSkd5kfmlufvzfXTte4OL2RyvbDtjctqaf dCrseFRAJafNl+WBQKdH2+DDHUQa2UmIoAf8i8y2VIf01DUr90mzDxUDUzCNBS4ZDL6Q 2SVfDWLZOtT1XCYtf2Yi4fXDsdd6ag/TdGxxxg2Y5Y4bG7Ab+uoE3H9TVXU7HO32zIsN /FcA== ARC-Message-Signature: i=1; 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Wed, 20 Sep 2023 12:12:16 -0700 (PDT) From: Serge Semin To: Michal Simek , Alexander Stein , Borislav Petkov , Tony Luck , James Morse , Mauro Carvalho Chehab , Robert Richter Cc: Serge Semin , Punnaiah Choudary Kalluri , Dinh Nguyen , Arnd Bergmann , Greg Kroah-Hartman , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 18/20] EDAC/synopsys: Unify CSRs macro declarations Date: Wed, 20 Sep 2023 22:10:42 +0300 Message-ID: <20230920191059.28395-19-fancer.lancer@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230920191059.28395-1-fancer.lancer@gmail.com> References: <20230920191059.28395-1-fancer.lancer@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 20 Sep 2023 12:13:13 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1777592730059335825 X-GMAIL-MSGID: 1777592730059335825 Originally the device CSR macros were supposed to be defined following the next local convention: first CSR offsets are listed, then their fields and flags are described in the same order; CSRs offset macros are supposed to have _OFST suffix; ECC-related macros shall have ECC_ prefix, generic DDR-related macros - DDR_ prefix. After all the years the driver has been living in kernel the CSRs macros have turned to be partly deviated away from the denoted convention. Fix all the related inconsistencies: move several CSRs offset macros to be defined before the CSRs fields and flags macros; replace OFFSET suffix with OFST; replace DDRC_ prefix with DDR_ and ECC_ with DDR_ where it's appropriate; group DDR_MSTR and ECC_CTRL (ECC_CLR) sibling fields macros together and make sure their prefixes match to the CSRs offset macros. In addition to that drop _MASK suffix from the macros which aren't used as masks and add ZYNQMP_ prefix to the ZYNQMP-specific macros to distinguish them from the generic Synopsys memory controller macros. Signed-off-by: Serge Semin --- Changelog v4: - This is a new patch collected from the rest of the series to simplify the review process. --- drivers/edac/synopsys_edac.c | 134 +++++++++++++++++------------------ 1 file changed, 66 insertions(+), 68 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 655a32792883..315eebe52923 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -78,20 +78,34 @@ #define ECC_POISON0_OFST 0xB8 #define ECC_POISON1_OFST 0xBC -#define ECC_ADDRMAP0_OFFSET 0x200 - -/* Control register bitfield definitions */ -#define ECC_CTRL_CLR_CE_ERR BIT(0) -#define ECC_CTRL_CLR_UE_ERR BIT(1) -#define ECC_CTRL_CLR_CE_ERRCNT BIT(2) -#define ECC_CTRL_CLR_UE_ERRCNT BIT(3) - -/* DDR Control Register width definitions */ +/* DDR Address Map Registers */ +#define DDR_ADDRMAP0_OFST 0x200 + +/* DDR Software Control Register */ +#define DDR_SWCTL 0x320 + +/* ZynqMP DDR QOS Registers */ +#define ZYNQMP_DDR_QOS_IRQ_STAT_OFST 0x20200 +#define ZYNQMP_DDR_QOS_IRQ_EN_OFST 0x20208 +#define ZYNQMP_DDR_QOS_IRQ_DB_OFST 0x2020C + +/* DDR Master register definitions */ +#define DDR_MSTR_DEV_CFG_MASK 0xC0000000 +#define DDR_MSTR_DEV_CFG_SHIFT 30 +#define DDR_MSTR_DEV_X4 0 +#define DDR_MSTR_DEV_X8 1 +#define DDR_MSTR_DEV_X16 2 +#define DDR_MSTR_DEV_X32 3 #define DDR_MSTR_BUSWIDTH_MASK 0x3000 #define DDR_MSTR_BUSWIDTH_SHIFT 12 -#define DDRCTL_EWDTH_16 2 -#define DDRCTL_EWDTH_32 1 -#define DDRCTL_EWDTH_64 0 +#define DDR_MSTR_BUSWIDTH_16 2 +#define DDR_MSTR_BUSWIDTH_32 1 +#define DDR_MSTR_BUSWIDTH_64 0 +#define DDR_MSTR_MEM_LPDDR4 0x20 +#define DDR_MSTR_MEM_DDR4 0x10 +#define DDR_MSTR_MEM_LPDDR3 0x8 +#define DDR_MSTR_MEM_DDR2 0x4 +#define DDR_MSTR_MEM_DDR3 0x1 /* ECC CFG0 register definitions */ #define ECC_CFG0_MODE_MASK 0x7 @@ -104,23 +118,19 @@ #define ECC_STAT_CECNT_SHIFT 8 #define ECC_STAT_BITNUM_MASK 0x7F +/* ECC control/clear register definitions */ +#define ECC_CTRL_CLR_CE_ERR BIT(0) +#define ECC_CTRL_CLR_UE_ERR BIT(1) +#define ECC_CTRL_CLR_CE_ERRCNT BIT(2) +#define ECC_CTRL_CLR_UE_ERRCNT BIT(3) +#define ECC_CTRL_EN_CE_IRQ BIT(8) +#define ECC_CTRL_EN_UE_IRQ BIT(9) + /* ECC error count register definitions */ #define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 #define ECC_ERRCNT_UECNT_SHIFT 16 #define ECC_ERRCNT_CECNT_MASK 0xFFFF -/* DDR QOS Interrupt register definitions */ -#define DDR_QOS_IRQ_STAT_OFST 0x20200 -#define DDR_QOSUE_MASK 0x4 -#define DDR_QOSCE_MASK 0x2 -#define ECC_CE_UE_INTR_MASK 0x6 -#define DDR_QOS_IRQ_EN_OFST 0x20208 -#define DDR_QOS_IRQ_DB_OFST 0x2020C - -/* DDR QOS Interrupt register definitions */ -#define DDR_UE_MASK BIT(9) -#define DDR_CE_MASK BIT(8) - /* ECC Corrected Error Register Mask and Shifts*/ #define ECC_CEADDR0_RW_MASK 0x3FFFF #define ECC_CEADDR0_RNK_MASK BIT(24) @@ -142,28 +152,11 @@ #define ECC_POISON1_ROW_SHIFT 0 #define ECC_POISON1_ROW_MASK 0x3FFFF -/* DDR Memory type defines */ -#define MEM_TYPE_DDR3 0x1 -#define MEM_TYPE_LPDDR3 0x8 -#define MEM_TYPE_DDR2 0x4 -#define MEM_TYPE_DDR4 0x10 -#define MEM_TYPE_LPDDR4 0x20 - -/* DDRC Software control register */ -#define DDRC_SWCTL 0x320 - /* DDRC ECC CE & UE poison mask */ #define ECC_CEPOISON_MASK 0x3 #define ECC_UEPOISON_MASK 0x1 -/* DDRC Device config masks */ -#define DDRC_MSTR_CFG_MASK 0xC0000000 -#define DDRC_MSTR_CFG_SHIFT 30 -#define DDRC_MSTR_CFG_X4_MASK 0x0 -#define DDRC_MSTR_CFG_X8_MASK 0x1 -#define DDRC_MSTR_CFG_X16_MASK 0x2 -#define DDRC_MSTR_CFG_X32_MASK 0x3 - +/* DDRC Device config shifts/masks */ #define DDR_MAX_ROW_SHIFT 18 #define DDR_MAX_COL_SHIFT 14 #define DDR_MAX_BANK_SHIFT 3 @@ -216,6 +209,11 @@ #define RANK_B0_BASE 6 +/* ZynqMP DDR QOS Interrupt register definitions */ +#define ZYNQMP_DDR_QOS_UE_MASK 0x4 +#define ZYNQMP_DDR_QOS_CE_MASK 0x2 +#define ZYNQMP_DDR_QOS_IRQ_MASK 0x6 + /** * struct ecc_error_info - ECC error log information. * @row: Row number. @@ -398,8 +396,8 @@ static void enable_intr(struct synps_edac_priv *priv) /* Enable UE/CE Interrupts */ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { - writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, - priv->baseaddr + DDR_QOS_IRQ_EN_OFST); + writel(ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK, + priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_EN_OFST); return; } @@ -410,7 +408,7 @@ static void enable_intr(struct synps_edac_priv *priv) * IRQs Enable/Disable flags have been available since v3.10a. * This is noop for the older controllers. */ - writel(DDR_UE_MASK | DDR_CE_MASK, + writel(ECC_CTRL_EN_CE_IRQ | ECC_CTRL_EN_UE_IRQ, priv->baseaddr + ECC_CLR_OFST); spin_unlock_irqrestore(&priv->reglock, flags); @@ -422,8 +420,8 @@ static void disable_intr(struct synps_edac_priv *priv) /* Disable UE/CE Interrupts */ if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { - writel(DDR_QOSUE_MASK | DDR_QOSCE_MASK, - priv->baseaddr + DDR_QOS_IRQ_DB_OFST); + writel(ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK, + priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_DB_OFST); return; } @@ -451,9 +449,9 @@ static irqreturn_t intr_handler(int irq, void *dev_id) priv = mci->pvt_info; if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { - regval = readl(priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); - regval &= (DDR_QOSCE_MASK | DDR_QOSUE_MASK); - if (!(regval & ECC_CE_UE_INTR_MASK)) + regval = readl(priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); + regval &= (ZYNQMP_DDR_QOS_CE_MASK | ZYNQMP_DDR_QOS_UE_MASK); + if (!(regval & ZYNQMP_DDR_QOS_IRQ_MASK)) return IRQ_NONE; } @@ -464,7 +462,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id) handle_error(mci, &priv->stat); if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) - writel(regval, priv->baseaddr + DDR_QOS_IRQ_STAT_OFST); + writel(regval, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); return IRQ_HANDLED; } @@ -483,18 +481,18 @@ static enum dev_type synps_get_dtype(const void __iomem *base) u32 regval; regval = readl(base + DDR_MSTR_OFST); - if (!(regval & MEM_TYPE_DDR4)) + if (!(regval & DDR_MSTR_MEM_DDR4)) return DEV_UNKNOWN; - regval = (regval & DDRC_MSTR_CFG_MASK) >> DDRC_MSTR_CFG_SHIFT; + regval = (regval & DDR_MSTR_DEV_CFG_MASK) >> DDR_MSTR_DEV_CFG_SHIFT; switch (regval) { - case DDRC_MSTR_CFG_X4_MASK: + case DDR_MSTR_DEV_X4: return DEV_X4; - case DDRC_MSTR_CFG_X8_MASK: + case DDR_MSTR_DEV_X8: return DEV_X8; - case DDRC_MSTR_CFG_X16_MASK: + case DDR_MSTR_DEV_X16: return DEV_X16; - case DDRC_MSTR_CFG_X32_MASK: + case DDR_MSTR_DEV_X32: return DEV_X32; } @@ -548,11 +546,11 @@ static enum mem_type synps_get_mtype(const void __iomem *base) memtype = readl(base + DDR_MSTR_OFST); - if ((memtype & MEM_TYPE_DDR3) || (memtype & MEM_TYPE_LPDDR3)) + if ((memtype & DDR_MSTR_MEM_DDR3) || (memtype & DDR_MSTR_MEM_LPDDR3)) mt = MEM_DDR3; - else if (memtype & MEM_TYPE_DDR2) + else if (memtype & DDR_MSTR_MEM_DDR2) mt = MEM_RDDR2; - else if ((memtype & MEM_TYPE_LPDDR4) || (memtype & MEM_TYPE_DDR4)) + else if ((memtype & DDR_MSTR_MEM_LPDDR4) || (memtype & DDR_MSTR_MEM_DDR4)) mt = MEM_DDR4; else mt = MEM_EMPTY; @@ -757,12 +755,12 @@ static ssize_t inject_data_poison_store(struct device *dev, struct mem_ctl_info *mci = to_mci(dev); struct synps_edac_priv *priv = mci->pvt_info; - writel(0, priv->baseaddr + DDRC_SWCTL); + writel(0, priv->baseaddr + DDR_SWCTL); if (strncmp(data, "CE", 2) == 0) writel(ECC_CEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); else writel(ECC_UEPOISON_MASK, priv->baseaddr + ECC_CFG1_OFST); - writel(1, priv->baseaddr + DDRC_SWCTL); + writel(1, priv->baseaddr + DDR_SWCTL); return count; } @@ -879,8 +877,8 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) priv->col_shift[9] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + COL_B9_BASE); - if (width == DDRCTL_EWDTH_64) { - if (memtype & MEM_TYPE_LPDDR3) { + if (width == DDR_MSTR_BUSWIDTH_64) { + if (memtype & DDR_MSTR_MEM_LPDDR3) { priv->col_shift[10] = ((addrmap[4] & COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : ((addrmap[4] & COL_MAX_VAL_MASK) + @@ -899,8 +897,8 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) (((addrmap[4] >> 8) & COL_MAX_VAL_MASK) + COL_B11_BASE); } - } else if (width == DDRCTL_EWDTH_32) { - if (memtype & MEM_TYPE_LPDDR3) { + } else if (width == DDR_MSTR_BUSWIDTH_32) { + if (memtype & DDR_MSTR_MEM_LPDDR3) { priv->col_shift[10] = (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 24) & COL_MAX_VAL_MASK) + @@ -920,7 +918,7 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) COL_B10_BASE); } } else { - if (memtype & MEM_TYPE_LPDDR3) { + if (memtype & DDR_MSTR_MEM_LPDDR3) { priv->col_shift[10] = (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) == COL_MAX_VAL_MASK) ? 0 : (((addrmap[3] >> 16) & COL_MAX_VAL_MASK) + @@ -995,7 +993,7 @@ static void setup_address_map(struct synps_edac_priv *priv) for (index = 0; index < 12; index++) { u32 addrmap_offset; - addrmap_offset = ECC_ADDRMAP0_OFFSET + (index * 4); + addrmap_offset = DDR_ADDRMAP0_OFST + (index * 4); addrmap[index] = readl(priv->baseaddr + addrmap_offset); } From patchwork Wed Sep 20 19:10:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142615 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4439006vqi; Wed, 20 Sep 2023 14:32:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH2maXYQ69BrbsXD22UhLHu24Rx0vegWXjPWc/YajHdfc6vPKC0VuMjNWxw83CIcvpN2Omd X-Received: by 2002:a05:6358:998a:b0:142:d678:f708 with SMTP id j10-20020a056358998a00b00142d678f708mr5353889rwb.19.1695245565433; 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There are structures and methods with the "synps" prefix, there are structures and methods with no driver-specific prefix, there are methods with the "edac" prefix, there are structure instances with "zynqmp" and "synopsys" prefixes, there are macros with "SYNPS", "ECC" and "DDR" prefixes. Moreover some time ago some of function names were shortened out by completely removing the vendor-specific prefixes thus leaving the driver with no strict entities naming convention (see commit bb894bc46ed0 ("EDAC, synopsys: Shorten static function names")). All of that makes the code much harder to read for no much reason (except shorter names utilization) since there is no easy way to distinguish now the local, EDAC core and global name spaces right from the code context. Similarly the kernel code index services (like elixir) gets to find the different functions with the same name, which harden the kernel hacking. Fix all of that by unifying the driver local entity names like functions, structures and non-CSR-related macros especially seeing the same approach has been used in the most of the EDAC LLDD. Use the "snps" prefix here as the shortest version of the controller vendor name. While at it add a more detailed controller name (DW uMCTL2 DDRC) to the driver comments and string literals where it's appropriate. Signed-off-by: Serge Semin --- Note "dw" prefix would be even shorter alternative. But we decided to stick with "snps" since "synopsys" has already been used in the module name. Changelog v2: - Forgot to fix some of the SYNPS_ZYNQMP_IRQ_REGS macro utilizations. (@tbot) --- drivers/edac/synopsys_edac.c | 240 +++++++++++++++++------------------ 1 file changed, 120 insertions(+), 120 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index 315eebe52923..bf23ed6e1779 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Synopsys DDR ECC Driver + * Synopsys DW uMCTL2 DDR ECC Driver * This driver is based on ppc4xx_edac.c drivers * * Copyright (C) 2012 - 2014 Xilinx, Inc. @@ -17,23 +17,23 @@ #include "edac_module.h" /* Number of cs_rows needed per memory controller */ -#define SYNPS_EDAC_NR_CSROWS 1 +#define SNPS_EDAC_NR_CSROWS 1 /* Number of channels per memory controller */ -#define SYNPS_EDAC_NR_CHANS 1 +#define SNPS_EDAC_NR_CHANS 1 /* Granularity of reported error in bytes */ -#define SYNPS_EDAC_ERR_GRAIN 1 +#define SNPS_EDAC_ERR_GRAIN 1 -#define SYNPS_EDAC_MSG_SIZE 256 +#define SNPS_EDAC_MSG_SIZE 256 -#define SYNPS_EDAC_MOD_STRING "synps_edac" -#define SYNPS_EDAC_MOD_VER "1" +#define SNPS_EDAC_MOD_STRING "snps_edac" +#define SNPS_EDAC_MOD_VER "1" /* DDR ECC Quirks */ -#define SYNPS_ZYNQMP_IRQ_REGS BIT(0) +#define SNPS_ZYNQMP_IRQ_REGS BIT(0) -/* Synopsys DDR memory controller registers that are relevant to ECC */ +/* Synopsys uMCTL2 DDR controller registers that are relevant to ECC */ /* DDRC Master 0 Register */ #define DDR_MSTR_OFST 0x0 @@ -215,7 +215,7 @@ #define ZYNQMP_DDR_QOS_IRQ_MASK 0x6 /** - * struct ecc_error_info - ECC error log information. + * struct snps_ecc_error_info - ECC error log information. * @row: Row number. * @col: Column number. * @bank: Bank number. @@ -223,7 +223,7 @@ * @bitpos: Bit position. * @data: Data causing the error. */ -struct ecc_error_info { +struct snps_ecc_error_info { u32 row; u32 col; u32 bank; @@ -233,21 +233,21 @@ struct ecc_error_info { }; /** - * struct synps_ecc_status - ECC status information to report. + * struct snps_ecc_status - ECC status information to report. * @ce_cnt: Correctable error count. * @ue_cnt: Uncorrectable error count. * @ceinfo: Correctable error log information. * @ueinfo: Uncorrectable error log information. */ -struct synps_ecc_status { +struct snps_ecc_status { u32 ce_cnt; u32 ue_cnt; - struct ecc_error_info ceinfo; - struct ecc_error_info ueinfo; + struct snps_ecc_error_info ceinfo; + struct snps_ecc_error_info ueinfo; }; /** - * struct synps_edac_priv - DDR memory controller private instance data. + * struct snps_edac_priv - DDR memory controller private data. * @baseaddr: Base address of the DDR controller. * @reglock: Concurrent CSRs access lock. * @message: Buffer for framing the event specific info. @@ -260,12 +260,12 @@ struct synps_ecc_status { * @bankgrp_shift: Bit shifts for bank group bit. * @rank_shift: Bit shifts for rank bit. */ -struct synps_edac_priv { +struct snps_edac_priv { void __iomem *baseaddr; spinlock_t reglock; - char message[SYNPS_EDAC_MSG_SIZE]; - struct synps_ecc_status stat; - const struct synps_platform_data *p_data; + char message[SNPS_EDAC_MSG_SIZE]; + struct snps_ecc_status stat; + const struct snps_platform_data *p_data; #ifdef CONFIG_EDAC_DEBUG ulong poison_addr; u32 row_shift[18]; @@ -277,22 +277,22 @@ struct synps_edac_priv { }; /** - * struct synps_platform_data - Synopsys uMCTL2 DDRC platform data. + * struct snps_platform_data - Synopsys uMCTL2 DDRC platform data. * @quirks: IP-core specific quirks. */ -struct synps_platform_data { +struct snps_platform_data { u32 quirks; }; /** - * synps_get_error_info - Get the current ECC error info. + * snps_get_error_info - Get the current ECC error info. * @priv: DDR memory controller private instance data. * * Return: one if there is no error otherwise returns zero. */ -static int synps_get_error_info(struct synps_edac_priv *priv) +static int snps_get_error_info(struct snps_edac_priv *priv) { - struct synps_ecc_status *p; + struct snps_ecc_status *p; u32 regval, clearval; unsigned long flags; void __iomem *base; @@ -351,21 +351,21 @@ static int synps_get_error_info(struct synps_edac_priv *priv) } /** - * handle_error - Handle Correctable and Uncorrectable errors. + * snps_handle_error - Handle Correctable and Uncorrectable errors. * @mci: EDAC memory controller instance. * @p: Synopsys ECC status structure. * * Handles ECC correctable and uncorrectable errors. */ -static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) +static void snps_handle_error(struct mem_ctl_info *mci, struct snps_ecc_status *p) { - struct synps_edac_priv *priv = mci->pvt_info; - struct ecc_error_info *pinf; + struct snps_edac_priv *priv = mci->pvt_info; + struct snps_ecc_error_info *pinf; if (p->ce_cnt) { pinf = &p->ceinfo; - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + snprintf(priv->message, SNPS_EDAC_MSG_SIZE, "Row %d Col %d Bank %d Bank Group %d Bit %d Data 0x%08x", pinf->row, pinf->col, pinf->bank, pinf->bankgrp, pinf->bitpos, pinf->data); @@ -378,7 +378,7 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) if (p->ue_cnt) { pinf = &p->ueinfo; - snprintf(priv->message, SYNPS_EDAC_MSG_SIZE, + snprintf(priv->message, SNPS_EDAC_MSG_SIZE, "Row %d Col %d Bank %d Bank Group %d", pinf->row, pinf->col, pinf->bank, pinf->bankgrp); @@ -390,12 +390,12 @@ static void handle_error(struct mem_ctl_info *mci, struct synps_ecc_status *p) memset(p, 0, sizeof(*p)); } -static void enable_intr(struct synps_edac_priv *priv) +static void snps_enable_irq(struct snps_edac_priv *priv) { unsigned long flags; /* Enable UE/CE Interrupts */ - if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { + if (priv->p_data->quirks & SNPS_ZYNQMP_IRQ_REGS) { writel(ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_EN_OFST); @@ -414,12 +414,12 @@ static void enable_intr(struct synps_edac_priv *priv) spin_unlock_irqrestore(&priv->reglock, flags); } -static void disable_intr(struct synps_edac_priv *priv) +static void snps_disable_irq(struct snps_edac_priv *priv) { unsigned long flags; /* Disable UE/CE Interrupts */ - if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { + if (priv->p_data->quirks & SNPS_ZYNQMP_IRQ_REGS) { writel(ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_DB_OFST); @@ -434,41 +434,41 @@ static void disable_intr(struct synps_edac_priv *priv) } /** - * intr_handler - Interrupt Handler for ECC interrupts. + * snps_irq_handler - Interrupt Handler for ECC interrupts. * @irq: IRQ number. * @dev_id: Device ID. * * Return: IRQ_NONE, if interrupt not set or IRQ_HANDLED otherwise. */ -static irqreturn_t intr_handler(int irq, void *dev_id) +static irqreturn_t snps_irq_handler(int irq, void *dev_id) { struct mem_ctl_info *mci = dev_id; - struct synps_edac_priv *priv; + struct snps_edac_priv *priv; int status, regval; priv = mci->pvt_info; - if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) { + if (priv->p_data->quirks & SNPS_ZYNQMP_IRQ_REGS) { regval = readl(priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); regval &= (ZYNQMP_DDR_QOS_CE_MASK | ZYNQMP_DDR_QOS_UE_MASK); if (!(regval & ZYNQMP_DDR_QOS_IRQ_MASK)) return IRQ_NONE; } - status = synps_get_error_info(priv); + status = snps_get_error_info(priv); if (status) return IRQ_NONE; - handle_error(mci, &priv->stat); + snps_handle_error(mci, &priv->stat); - if (priv->p_data->quirks & SYNPS_ZYNQMP_IRQ_REGS) + if (priv->p_data->quirks & SNPS_ZYNQMP_IRQ_REGS) writel(regval, priv->baseaddr + ZYNQMP_DDR_QOS_IRQ_STAT_OFST); return IRQ_HANDLED; } /** - * synps_get_dtype - Return the controller memory width. + * snps_get_dtype - Return the controller memory width. * @base: DDR memory controller base address. * * Get the EDAC device type width appropriate for the current controller @@ -476,7 +476,7 @@ static irqreturn_t intr_handler(int irq, void *dev_id) * * Return: a device type width enumeration. */ -static enum dev_type synps_get_dtype(const void __iomem *base) +static enum dev_type snps_get_dtype(const void __iomem *base) { u32 regval; @@ -500,14 +500,14 @@ static enum dev_type synps_get_dtype(const void __iomem *base) } /** - * synps_get_ecc_state - Return the controller ECC enable/disable status. + * snps_get_ecc_state - Return the controller ECC enable/disable status. * @base: DDR memory controller base address. * * Get the ECC enable/disable status for the controller. * * Return: a ECC status boolean i.e true/false - enabled/disabled. */ -static bool synps_get_ecc_state(void __iomem *base) +static bool snps_get_ecc_state(void __iomem *base) { u32 regval; @@ -517,11 +517,11 @@ static bool synps_get_ecc_state(void __iomem *base) } /** - * get_memsize - Read the size of the attached memory device. + * snps_get_memsize - Read the size of the attached memory device. * * Return: the memory size in bytes. */ -static u32 get_memsize(void) +static u32 snps_get_memsize(void) { struct sysinfo inf; @@ -531,7 +531,7 @@ static u32 get_memsize(void) } /** - * synps_get_mtype - Returns controller memory type. + * snps_get_mtype - Returns controller memory type. * @base: Synopsys ECC status structure. * * Get the EDAC memory type appropriate for the current controller @@ -539,7 +539,7 @@ static u32 get_memsize(void) * * Return: a memory type enumeration. */ -static enum mem_type synps_get_mtype(const void __iomem *base) +static enum mem_type snps_get_mtype(const void __iomem *base) { enum mem_type mt; u32 memtype; @@ -559,15 +559,15 @@ static enum mem_type synps_get_mtype(const void __iomem *base) } /** - * init_csrows - Initialize the csrow data. + * snps_init_csrows - Initialize the csrow data. * @mci: EDAC memory controller instance. * * Initialize the chip select rows associated with the EDAC memory * controller instance. */ -static void init_csrows(struct mem_ctl_info *mci) +static void snps_init_csrows(struct mem_ctl_info *mci) { - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; struct csrow_info *csi; struct dimm_info *dimm; u32 size, row; @@ -575,21 +575,21 @@ static void init_csrows(struct mem_ctl_info *mci) for (row = 0; row < mci->nr_csrows; row++) { csi = mci->csrows[row]; - size = get_memsize(); + size = snps_get_memsize(); for (j = 0; j < csi->nr_channels; j++) { dimm = csi->channels[j]->dimm; dimm->edac_mode = EDAC_SECDED; - dimm->mtype = synps_get_mtype(priv->baseaddr); + dimm->mtype = snps_get_mtype(priv->baseaddr); dimm->nr_pages = (size >> PAGE_SHIFT) / csi->nr_channels; - dimm->grain = SYNPS_EDAC_ERR_GRAIN; - dimm->dtype = synps_get_dtype(priv->baseaddr); + dimm->grain = SNPS_EDAC_ERR_GRAIN; + dimm->dtype = snps_get_dtype(priv->baseaddr); } } } /** - * mc_init - Initialize one driver instance. + * snps_mc_init - Initialize one driver instance. * @mci: EDAC memory controller instance. * @pdev: platform device. * @@ -597,7 +597,7 @@ static void init_csrows(struct mem_ctl_info *mci) * related driver-private data associated with the memory controller the * instance is bound to. */ -static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) +static void snps_mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) { mci->pdev = &pdev->dev; platform_set_drvdata(pdev, mci); @@ -609,21 +609,22 @@ static void mc_init(struct mem_ctl_info *mci, struct platform_device *pdev) mci->scrub_mode = SCRUB_NONE; mci->edac_cap = EDAC_FLAG_SECDED; - mci->ctl_name = "synps_ddr_controller"; - mci->dev_name = SYNPS_EDAC_MOD_STRING; - mci->mod_name = SYNPS_EDAC_MOD_VER; + mci->ctl_name = "snps_umctl2_ddrc"; + mci->dev_name = SNPS_EDAC_MOD_STRING; + mci->mod_name = SNPS_EDAC_MOD_VER; edac_op_state = EDAC_OPSTATE_INT; mci->ctl_page_to_phys = NULL; - init_csrows(mci); + snps_init_csrows(mci); } -static int setup_irq(struct mem_ctl_info *mci, - struct platform_device *pdev) + + +static int snps_setup_irq(struct mem_ctl_info *mci, struct platform_device *pdev) { - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; int ret, irq; irq = platform_get_irq(pdev, 0); @@ -633,14 +634,14 @@ static int setup_irq(struct mem_ctl_info *mci, return irq; } - ret = devm_request_irq(&pdev->dev, irq, intr_handler, + ret = devm_request_irq(&pdev->dev, irq, snps_irq_handler, 0, dev_name(&pdev->dev), mci); if (ret < 0) { edac_printk(KERN_ERR, EDAC_MC, "Failed to request IRQ\n"); return ret; } - enable_intr(priv); + snps_enable_irq(priv); return 0; } @@ -648,13 +649,13 @@ static int setup_irq(struct mem_ctl_info *mci, #ifdef CONFIG_EDAC_DEBUG /** - * ddr_poison_setup - Update poison registers. + * snps_data_poison_setup - Update poison registers. * @priv: DDR memory controller private instance data. * * Update poison registers as per DDR mapping. * Return: none. */ -static void ddr_poison_setup(struct synps_edac_priv *priv) +static void snps_data_poison_setup(struct snps_edac_priv *priv) { int col = 0, row = 0, bank = 0, bankgrp = 0, rank = 0, regval; int index; @@ -712,7 +713,7 @@ static ssize_t inject_data_error_show(struct device *dev, char *data) { struct mem_ctl_info *mci = to_mci(dev); - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; return sprintf(data, "Poison0 Addr: 0x%08x\n\rPoison1 Addr: 0x%08x\n\r" "Error injection Address: 0x%lx\n\r", @@ -726,12 +727,12 @@ static ssize_t inject_data_error_store(struct device *dev, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; if (kstrtoul(data, 0, &priv->poison_addr)) return -EINVAL; - ddr_poison_setup(priv); + snps_data_poison_setup(priv); return count; } @@ -741,7 +742,7 @@ static ssize_t inject_data_poison_show(struct device *dev, char *data) { struct mem_ctl_info *mci = to_mci(dev); - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; return sprintf(data, "Data Poisoning: %s\n\r", (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) @@ -753,7 +754,7 @@ static ssize_t inject_data_poison_store(struct device *dev, const char *data, size_t count) { struct mem_ctl_info *mci = to_mci(dev); - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; writel(0, priv->baseaddr + DDR_SWCTL); if (strncmp(data, "CE", 2) == 0) @@ -768,7 +769,7 @@ static ssize_t inject_data_poison_store(struct device *dev, static DEVICE_ATTR_RW(inject_data_error); static DEVICE_ATTR_RW(inject_data_poison); -static int edac_create_sysfs_attributes(struct mem_ctl_info *mci) +static int snps_create_sysfs_attributes(struct mem_ctl_info *mci) { int rc; @@ -781,13 +782,13 @@ static int edac_create_sysfs_attributes(struct mem_ctl_info *mci) return 0; } -static void edac_remove_sysfs_attributes(struct mem_ctl_info *mci) +static void snps_remove_sysfs_attributes(struct mem_ctl_info *mci) { device_remove_file(&mci->dev, &dev_attr_inject_data_error); device_remove_file(&mci->dev, &dev_attr_inject_data_poison); } -static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap) +static void snps_setup_row_address_map(struct snps_edac_priv *priv, u32 *addrmap) { u32 addrmap_row_b2_10; int index; @@ -846,7 +847,7 @@ static void setup_row_address_map(struct synps_edac_priv *priv, u32 *addrmap) ROW_MAX_VAL_MASK) + ROW_B17_BASE); } -static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) +static void snps_setup_column_address_map(struct snps_edac_priv *priv, u32 *addrmap) { u32 width, memtype; int index; @@ -948,7 +949,7 @@ static void setup_column_address_map(struct synps_edac_priv *priv, u32 *addrmap) } -static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap) +static void snps_setup_bank_address_map(struct snps_edac_priv *priv, u32 *addrmap) { priv->bank_shift[0] = (addrmap[1] & BANK_MAX_VAL_MASK) + BANK_B0_BASE; priv->bank_shift[1] = ((addrmap[1] >> 8) & @@ -960,7 +961,7 @@ static void setup_bank_address_map(struct synps_edac_priv *priv, u32 *addrmap) } -static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap) +static void snps_setup_bg_address_map(struct snps_edac_priv *priv, u32 *addrmap) { priv->bankgrp_shift[0] = (addrmap[8] & BANKGRP_MAX_VAL_MASK) + BANKGRP_B0_BASE; @@ -970,7 +971,7 @@ static void setup_bg_address_map(struct synps_edac_priv *priv, u32 *addrmap) } -static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap) +static void snps_setup_rank_address_map(struct snps_edac_priv *priv, u32 *addrmap) { priv->rank_shift[0] = ((addrmap[0] & RANK_MAX_VAL_MASK) == RANK_MAX_VAL_MASK) ? 0 : ((addrmap[0] & @@ -978,14 +979,14 @@ static void setup_rank_address_map(struct synps_edac_priv *priv, u32 *addrmap) } /** - * setup_address_map - Set Address Map by querying ADDRMAP registers. + * snps_setup_address_map - Set Address Map by querying ADDRMAP registers. * @priv: DDR memory controller private instance data. * * Set Address Map by querying ADDRMAP registers. * * Return: none. */ -static void setup_address_map(struct synps_edac_priv *priv) +static void snps_setup_address_map(struct snps_edac_priv *priv) { u32 addrmap[12]; int index; @@ -997,20 +998,20 @@ static void setup_address_map(struct synps_edac_priv *priv) addrmap[index] = readl(priv->baseaddr + addrmap_offset); } - setup_row_address_map(priv, addrmap); + snps_setup_row_address_map(priv, addrmap); - setup_column_address_map(priv, addrmap); + snps_setup_column_address_map(priv, addrmap); - setup_bank_address_map(priv, addrmap); + snps_setup_bank_address_map(priv, addrmap); - setup_bg_address_map(priv, addrmap); + snps_setup_bg_address_map(priv, addrmap); - setup_rank_address_map(priv, addrmap); + snps_setup_rank_address_map(priv, addrmap); } #endif /* CONFIG_EDAC_DEBUG */ /** - * mc_probe - Check controller and bind driver. + * snps_mc_probe - Check controller and bind driver. * @pdev: platform device. * * Probe a specific controller instance for binding with the driver. @@ -1018,11 +1019,11 @@ static void setup_address_map(struct synps_edac_priv *priv) * Return: 0 if the controller instance was successfully bound to the * driver; otherwise, < 0 on error. */ -static int mc_probe(struct platform_device *pdev) +static int snps_mc_probe(struct platform_device *pdev) { - const struct synps_platform_data *p_data; + const struct snps_platform_data *p_data; struct edac_mc_layer layers[2]; - struct synps_edac_priv *priv; + struct snps_edac_priv *priv; struct mem_ctl_info *mci; void __iomem *baseaddr; int rc; @@ -1035,20 +1036,20 @@ static int mc_probe(struct platform_device *pdev) if (!p_data) return -ENODEV; - if (!synps_get_ecc_state(baseaddr)) { + if (!snps_get_ecc_state(baseaddr)) { edac_printk(KERN_INFO, EDAC_MC, "ECC not enabled\n"); return -ENXIO; } layers[0].type = EDAC_MC_LAYER_CHIP_SELECT; - layers[0].size = SYNPS_EDAC_NR_CSROWS; + layers[0].size = SNPS_EDAC_NR_CSROWS; layers[0].is_virt_csrow = true; layers[1].type = EDAC_MC_LAYER_CHANNEL; - layers[1].size = SYNPS_EDAC_NR_CHANS; + layers[1].size = SNPS_EDAC_NR_CHANS; layers[1].is_virt_csrow = false; mci = edac_mc_alloc(EDAC_AUTO_MC_NUM, ARRAY_SIZE(layers), layers, - sizeof(struct synps_edac_priv)); + sizeof(struct snps_edac_priv)); if (!mci) { edac_printk(KERN_ERR, EDAC_MC, "Failed memory allocation for mc instance\n"); @@ -1060,9 +1061,9 @@ static int mc_probe(struct platform_device *pdev) priv->p_data = p_data; spin_lock_init(&priv->reglock); - mc_init(mci, pdev); + snps_mc_init(mci, pdev); - rc = setup_irq(mci, pdev); + rc = snps_setup_irq(mci, pdev); if (rc) goto free_edac_mc; @@ -1074,13 +1075,13 @@ static int mc_probe(struct platform_device *pdev) } #ifdef CONFIG_EDAC_DEBUG - rc = edac_create_sysfs_attributes(mci); + rc = snps_create_sysfs_attributes(mci); if (rc) { edac_printk(KERN_ERR, EDAC_MC, "Failed to create sysfs entries\n"); goto free_edac_mc; } - setup_address_map(priv); + snps_setup_address_map(priv); #endif return rc; @@ -1092,20 +1093,20 @@ static int mc_probe(struct platform_device *pdev) } /** - * mc_remove - Unbind driver from controller. + * snps_mc_remove - Unbind driver from device. * @pdev: Platform device. * * Return: Unconditionally 0 */ -static int mc_remove(struct platform_device *pdev) +static int snps_mc_remove(struct platform_device *pdev) { struct mem_ctl_info *mci = platform_get_drvdata(pdev); - struct synps_edac_priv *priv = mci->pvt_info; + struct snps_edac_priv *priv = mci->pvt_info; - disable_intr(priv); + snps_disable_irq(priv); #ifdef CONFIG_EDAC_DEBUG - edac_remove_sysfs_attributes(mci); + snps_remove_sysfs_attributes(mci); #endif edac_mc_del_mc(&pdev->dev); @@ -1114,32 +1115,31 @@ static int mc_remove(struct platform_device *pdev) return 0; } -static const struct synps_platform_data zynqmp_edac_def = { - .quirks = SYNPS_ZYNQMP_IRQ_REGS, +static const struct snps_platform_data zynqmp_edac_def = { + .quirks = SNPS_ZYNQMP_IRQ_REGS, }; -static const struct synps_platform_data synopsys_edac_def = { +static const struct snps_platform_data snps_edac_def = { .quirks = 0, }; -static const struct of_device_id synps_edac_match[] = { +static const struct of_device_id snps_edac_match[] = { { .compatible = "xlnx,zynqmp-ddrc-2.40a", .data = &zynqmp_edac_def }, - { .compatible = "snps,ddrc-3.80a", .data = &synopsys_edac_def }, + { .compatible = "snps,ddrc-3.80a", .data = &snps_edac_def }, { } }; -MODULE_DEVICE_TABLE(of, synps_edac_match); +MODULE_DEVICE_TABLE(of, snps_edac_match); -static struct platform_driver synps_edac_mc_driver = { +static struct platform_driver snps_edac_mc_driver = { .driver = { - .name = "synopsys-edac", - .of_match_table = synps_edac_match, + .name = "snps-edac", + .of_match_table = snps_edac_match, }, - .probe = mc_probe, - .remove = mc_remove, + .probe = snps_mc_probe, + .remove = snps_mc_remove, }; - -module_platform_driver(synps_edac_mc_driver); +module_platform_driver(snps_edac_mc_driver); MODULE_AUTHOR("Xilinx Inc"); -MODULE_DESCRIPTION("Synopsys DDR ECC driver"); +MODULE_DESCRIPTION("Synopsys uMCTL2 DDR ECC driver"); MODULE_LICENSE("GPL v2"); From patchwork Wed Sep 20 19:10:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Serge Semin X-Patchwork-Id: 142682 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:172:b0:3f2:4152:657d with SMTP id h50csp4542985vqi; Wed, 20 Sep 2023 18:28:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGImJ+NGBeDWPbKqKdhZ3VZMK5DDFh/tMT1/88Rj9iVOWbhz3Tl+Jmy4U7guH+lIq18iZ0i X-Received: by 2002:a05:6358:7212:b0:13a:a85b:a4dc with SMTP id h18-20020a056358721200b0013aa85ba4dcmr5693727rwa.29.1695259718435; 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It makes the code bulky, prone to mistakes and much harder to read. Seeing there are many places in the driver implementing the CSR fields get/set pattern use the FIELD_GET()/FIELD_PREP() macros introduced in the kernel specifically for that case. In addition use the BIT() and GENMASK() macros to generate the CSR flags/masks. While at it unify the row, column, rank, bank and bank group macros names to be having a suffix similar to the snps_ecc_error_info structure fields name. Signed-off-by: Serge Semin --- drivers/edac/synopsys_edac.c | 137 +++++++++++++++++------------------ 1 file changed, 67 insertions(+), 70 deletions(-) diff --git a/drivers/edac/synopsys_edac.c b/drivers/edac/synopsys_edac.c index bf23ed6e1779..327023e35d42 100644 --- a/drivers/edac/synopsys_edac.c +++ b/drivers/edac/synopsys_edac.c @@ -6,6 +6,8 @@ * Copyright (C) 2012 - 2014 Xilinx, Inc. */ +#include +#include #include #include #include @@ -90,33 +92,29 @@ #define ZYNQMP_DDR_QOS_IRQ_DB_OFST 0x2020C /* DDR Master register definitions */ -#define DDR_MSTR_DEV_CFG_MASK 0xC0000000 -#define DDR_MSTR_DEV_CFG_SHIFT 30 +#define DDR_MSTR_DEV_CFG_MASK GENMASK(31, 30) #define DDR_MSTR_DEV_X4 0 #define DDR_MSTR_DEV_X8 1 #define DDR_MSTR_DEV_X16 2 #define DDR_MSTR_DEV_X32 3 -#define DDR_MSTR_BUSWIDTH_MASK 0x3000 -#define DDR_MSTR_BUSWIDTH_SHIFT 12 +#define DDR_MSTR_BUSWIDTH_MASK GENMASK(13, 12) #define DDR_MSTR_BUSWIDTH_16 2 #define DDR_MSTR_BUSWIDTH_32 1 #define DDR_MSTR_BUSWIDTH_64 0 -#define DDR_MSTR_MEM_LPDDR4 0x20 -#define DDR_MSTR_MEM_DDR4 0x10 -#define DDR_MSTR_MEM_LPDDR3 0x8 -#define DDR_MSTR_MEM_DDR2 0x4 -#define DDR_MSTR_MEM_DDR3 0x1 +#define DDR_MSTR_MEM_LPDDR4 BIT(5) +#define DDR_MSTR_MEM_DDR4 BIT(4) +#define DDR_MSTR_MEM_LPDDR3 BIT(3) +#define DDR_MSTR_MEM_DDR2 BIT(2) +#define DDR_MSTR_MEM_DDR3 BIT(0) /* ECC CFG0 register definitions */ -#define ECC_CFG0_MODE_MASK 0x7 +#define ECC_CFG0_MODE_MASK GENMASK(2, 0) #define ECC_CFG0_MODE_SECDED 0x4 /* ECC status register definitions */ -#define ECC_STAT_UECNT_MASK 0xF0000 -#define ECC_STAT_UECNT_SHIFT 16 -#define ECC_STAT_CECNT_MASK 0xF00 -#define ECC_STAT_CECNT_SHIFT 8 -#define ECC_STAT_BITNUM_MASK 0x7F +#define ECC_STAT_UE_MASK GENMASK(23, 16) +#define ECC_STAT_CE_MASK GENMASK(15, 8) +#define ECC_STAT_BITNUM_MASK GENMASK(6, 0) /* ECC control/clear register definitions */ #define ECC_CTRL_CLR_CE_ERR BIT(0) @@ -127,34 +125,26 @@ #define ECC_CTRL_EN_UE_IRQ BIT(9) /* ECC error count register definitions */ -#define ECC_ERRCNT_UECNT_MASK 0xFFFF0000 -#define ECC_ERRCNT_UECNT_SHIFT 16 -#define ECC_ERRCNT_CECNT_MASK 0xFFFF - -/* ECC Corrected Error Register Mask and Shifts*/ -#define ECC_CEADDR0_RW_MASK 0x3FFFF -#define ECC_CEADDR0_RNK_MASK BIT(24) -#define ECC_CEADDR1_BNKGRP_MASK 0x3000000 -#define ECC_CEADDR1_BNKNR_MASK 0x70000 -#define ECC_CEADDR1_COL_MASK 0xFFF -#define ECC_CEADDR1_BNKGRP_SHIFT 24 -#define ECC_CEADDR1_BNKNR_SHIFT 16 - -/* ECC Poison register shifts */ -#define ECC_POISON0_RANK_SHIFT 24 -#define ECC_POISON0_RANK_MASK BIT(24) -#define ECC_POISON0_COLUMN_SHIFT 0 -#define ECC_POISON0_COLUMN_MASK 0xFFF -#define ECC_POISON1_BG_SHIFT 28 -#define ECC_POISON1_BG_MASK 0x30000000 -#define ECC_POISON1_BANKNR_SHIFT 24 -#define ECC_POISON1_BANKNR_MASK 0x7000000 -#define ECC_POISON1_ROW_SHIFT 0 -#define ECC_POISON1_ROW_MASK 0x3FFFF +#define ECC_ERRCNT_UECNT_MASK GENMASK(31, 16) +#define ECC_ERRCNT_CECNT_MASK GENMASK(15, 0) + +/* ECC Corrected Error register definitions */ +#define ECC_CEADDR0_RANK_MASK GENMASK(27, 24) +#define ECC_CEADDR0_ROW_MASK GENMASK(17, 0) +#define ECC_CEADDR1_BANKGRP_MASK GENMASK(25, 24) +#define ECC_CEADDR1_BANK_MASK GENMASK(23, 16) +#define ECC_CEADDR1_COL_MASK GENMASK(11, 0) + +/* ECC Poison register definitions */ +#define ECC_POISON0_RANK_MASK GENMASK(27, 24) +#define ECC_POISON0_COL_MASK GENMASK(11, 0) +#define ECC_POISON1_BANKGRP_MASK GENMASK(29, 28) +#define ECC_POISON1_BANK_MASK GENMASK(26, 24) +#define ECC_POISON1_ROW_MASK GENMASK(17, 0) /* DDRC ECC CE & UE poison mask */ -#define ECC_CEPOISON_MASK 0x3 -#define ECC_UEPOISON_MASK 0x1 +#define ECC_CEPOISON_MASK GENMASK(1, 0) +#define ECC_UEPOISON_MASK BIT(0) /* DDRC Device config shifts/masks */ #define DDR_MAX_ROW_SHIFT 18 @@ -210,9 +200,9 @@ #define RANK_B0_BASE 6 /* ZynqMP DDR QOS Interrupt register definitions */ -#define ZYNQMP_DDR_QOS_UE_MASK 0x4 -#define ZYNQMP_DDR_QOS_CE_MASK 0x2 -#define ZYNQMP_DDR_QOS_IRQ_MASK 0x6 +#define ZYNQMP_DDR_QOS_UE_MASK BIT(2) +#define ZYNQMP_DDR_QOS_CE_MASK BIT(1) +#define ZYNQMP_DDR_QOS_IRQ_MASK (ZYNQMP_DDR_QOS_UE_MASK | ZYNQMP_DDR_QOS_CE_MASK) /** * struct snps_ecc_error_info - ECC error log information. @@ -304,38 +294,40 @@ static int snps_get_error_info(struct snps_edac_priv *priv) if (!regval) return 1; - p->ceinfo.bitpos = (regval & ECC_STAT_BITNUM_MASK); + p->ceinfo.bitpos = FIELD_GET(ECC_STAT_BITNUM_MASK, regval); regval = readl(base + ECC_ERRCNT_OFST); - p->ce_cnt = regval & ECC_ERRCNT_CECNT_MASK; - p->ue_cnt = (regval & ECC_ERRCNT_UECNT_MASK) >> ECC_ERRCNT_UECNT_SHIFT; + p->ce_cnt = FIELD_GET(ECC_ERRCNT_CECNT_MASK, regval); + p->ue_cnt = FIELD_GET(ECC_ERRCNT_UECNT_MASK, regval); if (!p->ce_cnt) goto ue_err; regval = readl(base + ECC_CEADDR0_OFST); - p->ceinfo.row = (regval & ECC_CEADDR0_RW_MASK); + p->ceinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + regval = readl(base + ECC_CEADDR1_OFST); - p->ceinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> - ECC_CEADDR1_BNKNR_SHIFT; - p->ceinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> - ECC_CEADDR1_BNKGRP_SHIFT; - p->ceinfo.col = (regval & ECC_CEADDR1_COL_MASK); + p->ceinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + p->ceinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + p->ceinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + p->ceinfo.data = readl(base + ECC_CSYND0_OFST); + edac_dbg(2, "ECCCSYN0: 0x%08X ECCCSYN1: 0x%08X ECCCSYN2: 0x%08X\n", readl(base + ECC_CSYND0_OFST), readl(base + ECC_CSYND1_OFST), readl(base + ECC_CSYND2_OFST)); + ue_err: if (!p->ue_cnt) goto out; regval = readl(base + ECC_UEADDR0_OFST); - p->ueinfo.row = (regval & ECC_CEADDR0_RW_MASK); + p->ueinfo.row = FIELD_GET(ECC_CEADDR0_ROW_MASK, regval); + regval = readl(base + ECC_UEADDR1_OFST); - p->ueinfo.bankgrp = (regval & ECC_CEADDR1_BNKGRP_MASK) >> - ECC_CEADDR1_BNKGRP_SHIFT; - p->ueinfo.bank = (regval & ECC_CEADDR1_BNKNR_MASK) >> - ECC_CEADDR1_BNKNR_SHIFT; - p->ueinfo.col = (regval & ECC_CEADDR1_COL_MASK); + p->ueinfo.bankgrp = FIELD_GET(ECC_CEADDR1_BANKGRP_MASK, regval); + p->ueinfo.bank = FIELD_GET(ECC_CEADDR1_BANK_MASK, regval); + p->ueinfo.col = FIELD_GET(ECC_CEADDR1_COL_MASK, regval); + p->ueinfo.data = readl(base + ECC_UESYND0_OFST); out: spin_lock_irqsave(&priv->reglock, flags); @@ -484,7 +476,7 @@ static enum dev_type snps_get_dtype(const void __iomem *base) if (!(regval & DDR_MSTR_MEM_DDR4)) return DEV_UNKNOWN; - regval = (regval & DDR_MSTR_DEV_CFG_MASK) >> DDR_MSTR_DEV_CFG_SHIFT; + regval = FIELD_GET(DDR_MSTR_DEV_CFG_MASK, regval); switch (regval) { case DDR_MSTR_DEV_X4: return DEV_X4; @@ -511,7 +503,8 @@ static bool snps_get_ecc_state(void __iomem *base) { u32 regval; - regval = readl(base + ECC_CFG0_OFST) & ECC_CFG0_MODE_MASK; + regval = readl(base + ECC_CFG0_OFST); + regval = FIELD_GET(ECC_CFG0_MODE_MASK, regval); return (regval == ECC_CFG0_MODE_SECDED); } @@ -698,13 +691,13 @@ static void snps_data_poison_setup(struct snps_edac_priv *priv) if (priv->rank_shift[0]) rank = (hif_addr >> priv->rank_shift[0]) & BIT(0); - regval = (rank << ECC_POISON0_RANK_SHIFT) & ECC_POISON0_RANK_MASK; - regval |= (col << ECC_POISON0_COLUMN_SHIFT) & ECC_POISON0_COLUMN_MASK; + regval = FIELD_PREP(ECC_POISON0_RANK_MASK, rank) | + FIELD_PREP(ECC_POISON0_COL_MASK, col); writel(regval, priv->baseaddr + ECC_POISON0_OFST); - regval = (bankgrp << ECC_POISON1_BG_SHIFT) & ECC_POISON1_BG_MASK; - regval |= (bank << ECC_POISON1_BANKNR_SHIFT) & ECC_POISON1_BANKNR_MASK; - regval |= (row << ECC_POISON1_ROW_SHIFT) & ECC_POISON1_ROW_MASK; + regval = FIELD_PREP(ECC_POISON1_BANKGRP_MASK, bankgrp) | + FIELD_PREP(ECC_POISON1_BANK_MASK, bank) | + FIELD_PREP(ECC_POISON1_ROW_MASK, row); writel(regval, priv->baseaddr + ECC_POISON1_OFST); } @@ -743,10 +736,14 @@ static ssize_t inject_data_poison_show(struct device *dev, { struct mem_ctl_info *mci = to_mci(dev); struct snps_edac_priv *priv = mci->pvt_info; + const char *errstr; + u32 regval; + + regval = readl(priv->baseaddr + ECC_CFG1_OFST); + errstr = FIELD_GET(ECC_CEPOISON_MASK, regval) == ECC_CEPOISON_MASK ? + "Correctable Error" : "UnCorrectable Error"; - return sprintf(data, "Data Poisoning: %s\n\r", - (((readl(priv->baseaddr + ECC_CFG1_OFST)) & 0x3) == 0x3) - ? ("Correctable Error") : ("UnCorrectable Error")); + return sprintf(data, "Data Poisoning: %s\n\r", errstr); } static ssize_t inject_data_poison_store(struct device *dev, @@ -853,7 +850,7 @@ static void snps_setup_column_address_map(struct snps_edac_priv *priv, u32 *addr int index; memtype = readl(priv->baseaddr + DDR_MSTR_OFST); - width = (memtype & DDR_MSTR_BUSWIDTH_MASK) >> DDR_MSTR_BUSWIDTH_SHIFT; + width = FIELD_GET(DDR_MSTR_BUSWIDTH_MASK, memtype); priv->col_shift[0] = 0; priv->col_shift[1] = 1;